CN117672288A - Ferroelectric random access memory array and control method thereof - Google Patents

Abstract

The invention provides a ferroelectric random access memory array and a control method thereof, belonging to the technical field of semiconductor memories. The invention comprises an overall array formed by repeatedly arranging a basic array along the transverse direction and the longitudinal direction, wherein the basic array comprises memory cells, word lines, control lines, basic plate lines, overall plate lines, basic bit lines and overall bit lines, and the memory cells are repeatedly arranged into a matrix structure along the transverse direction and the longitudinal direction; the memory cell comprises a transistor and a ferroelectric capacitor, wherein the grid electrode of the transistor is connected with a word line, the drain electrode of the transistor is connected with a bit line, the source electrode of the transistor is connected with the upper polar plate of the ferroelectric capacitor, and the lower polar plate of the ferroelectric capacitor is connected with a polar plate. The invention also provides a control method for carrying out data writing, data reading and data rewriting on the ferroelectric random access memory array. The hierarchical design method can increase the scale of the ferroelectric random access memory array on the premise of not sacrificing the reading time and the reading window.

Description

Ferroelectric random access memory array and control method thereof

Technical Field

The invention belongs to the technical field of semiconductor memories, and particularly relates to a ferroelectric random access memory array and a control method thereof.

Background

The memory is an integral part of the electronic information processing system. In the past, memory performance has been improved by virtue of continued progress in CMOS processing. However, in recent years, on one hand, transistor leakage caused by size shrinkage is more and more serious, memory power consumption is increased, and meanwhile, the retention characteristic of a memory unit is deteriorated, and the development of the memory encounters a relatively obvious bottleneck; on the other hand, the rapid development of the fields of artificial intelligence, the Internet of things and the like also brings higher requirements to performance indexes such as capacity, speed and power consumption of a memory. In such a background, since the embedded ferroelectric random access memory (Embedded Ferroelectric Random Access Memory, efram) has characteristics of non-volatile, high density, low power consumption, and high reading speed, etc., the overall performance of the system can be improved, and thus the embedded ferroelectric random access memory has been attracting attention in recent years.

Ferroelectric memories have two different polarization states, and both polarization states can be maintained after voltage actuation is removed. An applied voltage stimulus is applied to the ferroelectric memory, and the response charge amounts of the two different polarization states are different. Two different polarization states are defined to represent 0 and 1 respectively, so that nonvolatile storage of data can be realized. If ferroelectric memories are integrated in an array, the memory function can be implemented at a very low cost and at a very high speed by applying voltages to ferroelectric memories of different polarization states and collecting the voltage changes in response to the charges.

However, since the read time of the ferroelectric random access memory increases with the increase of the array size and the read window decreases with the increase of the array size, how to increase the ferroelectric random access memory array size without sacrificing the read time and the read window becomes an urgent problem to be solved.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a ferroelectric random access memory array and a control method thereof, and the array structure adopts a layering design method, so that the scale of the ferroelectric random access memory array can be increased on the premise of not sacrificing the reading time and the reading window.

The technical scheme of the invention is as follows:

a ferroelectric random access memory array comprising a general array of basic arrays repeatedly arranged in a lateral direction and a longitudinal direction; in the global array, each global bit line in the same column basic array is connected together according to a respective column, each word line in the same row basic array is connected together according to a respective row, the control lines of the same row basic array are connected together to form a row control line, and the global plate lines of the same column basic array are connected together to form a global plate line of the column.

The basic array comprises memory cells, word lines, control lines, basic plate lines, overall plate lines, basic bit lines and overall bit lines, and the memory cells are repeatedly arranged into a matrix structure along the transverse direction and the longitudinal direction; the word lines of the memory cells in the same row are connected to the same word line, the plate lines of the memory cells in the same row are connected to the same basic plate line, the bit lines of the memory cells in the same column are connected to the same basic bit line, the word lines are parallel to the basic plate line, and the word lines are perpendicular to the basic bit line; each basic plate line is connected to the same overall plate line of the basic array through a transistor, the drain electrode of the transistor is connected with the basic plate line, the source electrode of the transistor is connected with the overall plate line, and the grid electrode of the transistor is connected with word lines of the same row; each basic bit line is connected to the corresponding overall bit line of each column through a transistor, the source electrode of the transistor is connected with the basic bit line, the drain electrode of the transistor is connected with the overall bit line, and the grid electrode of the transistor is connected with the same control line of the basic array; when the basic array is composed of m rows and n columns of memory cells, the basic array comprises m transistors for connecting basic plate lines and global plate lines, n transistors for connecting basic bit lines and global bit lines, m basic plate lines, one global plate line, n basic bit lines, n global bit lines, m word lines and one control line, and the outgoing lines of the basic array comprise one global plate line, n global bit lines, m word lines and one control line, and the outgoing lines of the basic array are in total (m+n+2).

The memory cell comprises a transistor, a ferroelectric capacitor, a word line, a bit line and a plate line, wherein the gate electrode of the transistor is connected with the word line, the drain electrode of the transistor is connected with the bit line, the source electrode of the transistor is connected with the upper polar plate of the ferroelectric capacitor, and the lower polar plate of the ferroelectric capacitor is connected with the plate line.

Further, in the global array, each global bit line is connected to a corresponding sense amplifier circuit, each global plate line is connected to a corresponding driving circuit, each word line is connected to a corresponding driving circuit, and each control line is connected to a corresponding driving circuit.

The invention also provides a method for controlling the ferroelectric random access memory array, which comprises the following steps:

when writing data into the ferroelectric random access memory array, writing corresponding storage information into one row of storage units at a time, wherein the specific steps are as follows:

pre-charging the total bit line corresponding to the unit needing to be written with the storage information to a voltage value needing to be written, then placing the voltages of the control line and the word line at an effective voltage, turning on a transistor connecting the total bit line and the basic bit line, turning on a transistor connecting the total plate line and the basic plate line, and turning on all transistors in the selected memory units in the middle row, so that the voltages of the total bit line are all transmitted to the corresponding basic bit line, the voltages of the total plate line are all transmitted to the corresponding basic plate line, and at the moment, the voltages of the memory units needing to be written with the information '1' are high-potential, and the voltages of the memory units needing to be written with the information '0' are low-potential; firstly, setting the overall plate line voltage at a low potential to complete writing of information '1', and then setting the overall plate line voltage at a high potential to complete writing of information '0'; after the writing is completed, the voltages of the global plate line and the global bit line are restored to low potential, and the voltages of the control line and the word line are restored to invalid voltage.

When reading data in the ferroelectric random access memory array, reading information stored in one row of memory cells at a time, wherein the method comprises the following specific steps:

firstly, setting the general bit line corresponding to the unit to be read in a floating state, then setting the voltages of the control line and the word line in an effective voltage, at the moment, starting the transistors connecting the general bit line and the basic bit line, starting the transistors connecting the general plate line and the basic plate line, and completely starting the transistors in the memory units of the selected middle row, so that the voltages of the general bit line are completely transmitted to the corresponding basic bit line, and the voltages of the general plate line are completely transmitted to the corresponding basic plate line, and at the moment, the basic bit line is also in a floating state; then the overall plate line voltage is set to be high, dielectric charges are provided by the cells storing 0 in the selected row so that the corresponding overall bit line voltage is raised, ferroelectric polarization inversion can also occur to the cells storing 1 so that the overall bit line voltage corresponding to the cells storing 1 is higher than the overall bit line voltage corresponding to the cells storing 0; the global bit line voltage is compared with a reference voltage through a sense amplifier circuit, the global bit line voltage corresponding to a cell storing "1" becomes a high potential, and the global bit line voltage corresponding to a cell storing "0" becomes a low potential.

After the read operation is completed, when the read selected row information needs to be rewritten, the specific steps are as follows:

at the end of the reading operation, the total bit line voltage is compared with the reference voltage through the sense amplifying circuit, the total bit line voltage corresponding to the cell storing '1' becomes high potential, the total bit line voltage corresponding to the cell storing '0' becomes low potential, and the cell storing '0' automatically completes the rewriting because the total plate line voltage is high potential at the moment; then the overall plate line voltage is set at a low potential, and the cell storing '1' will also complete the overwriting; after the overwriting is completed, the voltages of the global bit line and the global plate line are restored to the low potential, and the voltages of the control line and the word line are restored to the invalid voltage.

The ferroelectric random access memory array and the control method thereof adopt a hierarchical design method, and the scale of the ferroelectric random access memory array can be increased on the premise of not sacrificing the reading time and the reading window.

Drawings

Fig. 1 is a schematic equivalent circuit diagram and a symbol diagram thereof of a memory cell constituting a ferroelectric random access memory array according to the present invention, wherein fig. 1 (a) is a schematic equivalent circuit diagram and fig. 1 (b) is a symbol diagram;

fig. 2 is a schematic equivalent circuit diagram and a symbol diagram thereof of a basic array constituting a ferroelectric random access memory array according to the present invention, wherein fig. 2 (a) is a schematic equivalent circuit diagram and fig. 2 (b) is a symbol diagram;

FIG. 3 is a schematic equivalent circuit diagram of a ferroelectric random access memory array according to the present invention;

fig. 4 is a schematic equivalent circuit diagram of an embodiment of a ferroelectric random access memory array according to the present invention.

Detailed Description

An exemplary embodiment of the present invention will be further described with reference to the accompanying drawings. It should be noted that the purpose of the disclosed embodiments is to aid further understanding of the present invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.

Fig. 1 is a schematic equivalent circuit diagram and a symbol diagram thereof of a memory cell constituting a ferroelectric random access memory array according to the present invention, wherein fig. 1 (a) is a schematic equivalent circuit diagram and fig. 1 (b) is a symbol diagram. In fig. 1 (a), a transistor and a ferroelectric capacitor form a memory cell, the gate of the transistor is connected to a word line WL, the drain of the transistor is connected to a bit line BL, the source of the transistor is connected to an upper plate of the ferroelectric capacitor, and the lower plate of the ferroelectric capacitor is connected to a plate line PL. The circuit shown in fig. 1 (a) can be equivalent to the symbol diagram shown in fig. 1 (b), and fig. 1 (b) shows that one memory cell has three outgoing lines in the circuit, namely, word line WL, bit line BL and plate line PL.

The memory cells shown in fig. 1 are repeatedly arranged according to the method proposed by the present invention, and a basic array can be obtained. Fig. 2 is a schematic equivalent circuit diagram and a symbol diagram thereof of a basic array constituting a ferroelectric random access memory array according to the present invention, wherein fig. 2 (a) is a schematic equivalent circuit diagram and fig. 2 (b) is a symbol diagram. In fig. 2 (a), the basic array includes m rows of memory cells and n columns of memory cells. The word lines WL of the memory cells in the same row are connected with the same word line in the basic array, and the first row to the m-th row respectively correspond to the word lines WL in the basic array ₀ To WL (WL) _m-1 . The plate line PL of the memory cells in the same row is connected with the same basic plate line in the basic array, and the first row to the m-th row respectively correspond to the basic plate line LPL in the basic array ₀ To LPL _m-1 . Bit line BL of the same column of memory cells is connected to basic arrayCorresponding to the basic bit lines LBL in the basic array from the first column to the n-th column ₀ To LBL _n-1 . In the basic array shown in fig. 2 (a), each basic plate line is connected to the same global plate line GPL through a transistor, the drain of which is connected to the basic plate line LPL, the source to the global plate line GPL, and the gate to the word line WL of the same row. In a basic array, there are m such transistors, respectively located in the 1 st to m th rows, and there are m basic plate lines LPL, and only one overall plate line GPL. Taking the first row of memory cells as an example, the base plate line LPL of the row ₀ The global plate line GPL is connected through a transistor, the gate of which is connected with the word line WL ₀ . In the basic array shown in fig. 2 (a), each basic bit line LBL is connected to the global bit line GBL of the same column through a transistor, the source of which is connected to the basic bit line LBL, the drain is connected to the global bit line GBL, and the gate is connected to the corresponding control line EN. In a basic array, there are n such transistors, respectively located in columns 1 to n, n basic bit lines LBL, n global bit lines GBL, and only one control line EN. Taking the first column of memory cells as an example, the basic bit lines LBL of the column ₀ Connecting global bit line GBL through a transistor ₀ The gate of the transistor is connected to a control line EN. The basic array shown in fig. 2 (a) can be equivalently used as the symbol diagram shown in fig. 2 (b), and fig. 2 (b) shows that one basic array has (m+n+2) outgoing lines in the circuit, including m word lines (WL ₀ 、WL ₁ 、……、WL _m-2 、WL _m-1 ) N Global Bit Lines (GBL) ₀ 、GBL ₁ 、……、GBL _n-2 、GBL _n-1 ) A global plate line GPL and a control line EN.

The basic array shown in fig. 2 is repeatedly arranged according to the method proposed by the present patent, and may constitute an overall array. Fig. 3 is a schematic equivalent circuit diagram of a ferroelectric random access memory array according to the present invention. The overall array shown in fig. 3 includes a B-row basic array and an a-column basic array. In the global array shown in fig. 3, n global bit lines in each column of the basic array are connected together. For example, GBL in the first column base array ₀ ConnectionTaken together to form GBL _0,0 GBL in the first column base array ₁ Are joined together to form GBL _1,0 GBL in the first column base array _n-2 Are joined together to form GBL _n-2,0 GBL in the first column base array _n-1 Are joined together to form GBL _n-1,0 In this manner, the basic arrays from the first column to the A-th column are all the same, and GBL in the A-th basic array ₀ Are joined together to form GBL _0,A-1 GBL in column A basic array _n-1 Are joined together to form GBL _n-1,A-1 . Thus, there are n x a global bit lines GBL in the global array shown in fig. 3. In the overall array shown in fig. 3, the m word lines in each row of the basic array are connected together. For example, WL in the first row basic array ₀ Are connected together to form WL _0,0 WL in first row basic array ₁ Are connected together to form WL _1,0 WL in first row basic array _m-2 Are connected together to form WL _m-2,0 WL in first row basic array _m-1 Are connected together to form WL _m-1,0 In this manner, the same is true for the basic array from the first row to the B-th row, WL in the B-th basic array ₀ Are connected together to form WL _0,B-1 WL in basic array of row B _m-1 Are connected together to form WL _m-1,B-1 . Thus, there are m×b word lines WL in the overall array shown in fig. 3. In the basic array shown in FIG. 3, the control lines EN of each row of the basic array are connected together to form the EN of the overall array, from the EN of the first row ₀ EN to line B _B-1 A total of B control lines EN. The global plate lines GPLs of each column of the basic array are connected together to form GPLs of the global array, from the GPLs of the first column ₀ GPL to column A _A-1 A total of a global board lines GPL. In the global array shown in FIG. 3, each global bit line GBL is connected to a corresponding sense amplifier circuit, each global plate line GPL is connected to a corresponding driver circuit, each word line is connected to a corresponding driver circuit, and each control line is connected to a corresponding driver circuit, which are not shown in the figures, and the sense amplifier circuits and the driver circuits are not shown in the figures, which are known to those skilled in the artA portion that can be completed.

An embodiment of n=m=a=b=2 is taken below to describe how the proposed memory array is written, read and rewritten with the control method proposed by the present invention. Fig. 4 shows an overall array circuit when n=m=a=b=2, i.e. the overall array of fig. 4 is composed of 2 rows and 2 columns of basic arrays, each consisting of 2 rows and 2 columns of memory cells. Word lines of the first row of memory cells are all connected with WL _0,0 Word lines of the second row of memory cells are all connected with WL _1,0 Word lines of the third row of memory cells are all connected with WL _0,1 Word lines of the fourth row of memory cells are all connected with WL _1,1 . The first column of memory cells are all connected to the global bit line GBL through a transistor _0,0 ，GBL _0,0 Is connected to a sense amplifier circuit SA _0,0 The second column of memory cells are all connected to global bit line GBL through a transistor _1,0 ，GBL _1,0 Is connected to a sense amplifier circuit SA _1,0 The third column of memory cells are all connected to global bit line GBL through a transistor _0,1 ，GBL _0,1 Is connected to a sense amplifier circuit SA _0,1 The fourth column of memory cells are all connected to the global bit line GBL through a transistor _1,1 ，GBL _1,1 Is connected to a sense amplifier circuit SA _1,1 . In each basic array, there are two rows of basic plate lines and two columns of basic bit lines, the basic plate lines are connected to the overall plate line through a transistor, the gates of the transistors are connected to the word lines of the same row, the basic bit lines are connected to the overall bit line through a transistor, and the gates of the transistors are connected to the control line. Since there are 2 rows and 2 columns of the basic array, there are two rows of control lines EN ₀ And EN ₁ Two-column general board line GPL ₀ And GPL ₁ . In FIG. 4, the basic plate lines and basic bit lines in different basic arrays are distinguished by different subscripts, and in the basic array in the upper left corner, there are two rows of basic plate lines LPL ₀₀ And LPL ₁₀ Each row of basic plate lines is connected with two memory cells, and has two columns of basic bit lines LBL ₀₀ And LBL ₁₀ Each column of basic bit lines is connected with two memory cells. In the basic array in the upper right corner, there are two rows of basic board lines LPL ₀₁ And LPL ₁₁ Each row of basic board linesTwo memory cells are connected, and there are two basic bit lines LBL ₀₁ And LBL ₁₁ Each column of basic bit lines is connected with two memory cells. In the basic array in the lower left corner, there are two rows of basic board lines LPL ₀₂ And LPL ₁₂ Each row of basic plate lines is connected with two memory cells, and has two columns of basic bit lines LBL ₀₂ And LBL ₁₂ Each column of basic bit lines is connected with two memory cells. In the basic array in the lower right corner, there are two rows of basic board lines LPL ₀₃ And LPL ₁₃ Each row of basic plate lines is connected with two memory cells, and has two columns of basic bit lines LBL ₀₃ And LBL ₁₃ Each column of basic bit lines is connected with two memory cells.

The following performs a write operation to the general array shown in fig. 4, specifically, performs a write operation to the first row of memory cells, and writes "0", "1", "0", and "1" to the four memory cells from left to right, respectively. First, GBL is set _0,0 、GBL _1,0 、GBL _0,1 And GBL _1,1 GPL0 and GPL1 were precharged to 0V, 2.5V, 0V and 2.5V, respectively. Then EN is carried out ₀ And WL (WL) _0,0 Placed at 2.5V, EN ₁ 、WL _1,0 、WL _0,1 And WL (WL) _1,1 Is placed at 0V. At this time, the transistors connecting the global bit line and the basic bit line are turned on, and the transistors connecting the global plate line and the basic plate line are turned on, and the transistors in the memory cells of the first row are also all turned on. Thus, LBL ₀₀ 、LBL ₁₀ 、LBL ₀₁ And LBL ₁₁ The voltages of 0V, 2.5V, 0V and 2.5V, LPL, respectively ₀₀ And LPL ₀₁ The voltages of (2) are all 0V and LBL ₀₂ 、LBL ₁₂ 、LBL ₀₃ 、LBL ₁₃ 、LPL ₁₀ 、LPL ₁₁ 、LPL ₀₂ 、LPL ₀₃ 、LPL ₁₂ And LPL ₁₃ The original voltage is kept unchanged. The voltages at two ends of the ferroelectric capacitors in the first row of memory cells are respectively 0V, 2.5V, 0V and 2.5V from left to right, the ferroelectric capacitors in the first and third memory cells do not have ferroelectric polarization inversion, the stored information is unchanged, the ferroelectric capacitors in the second and fourth memory cells have ferroelectric polarization inversion, and the stored information '1' is written. Splicing jointNext, GPL is set ₀ And GPL ₁ Is set at 2.5V, thus LPL ₀₀ And LPL ₀₁ The voltages of (2) are 2.5V. At this time, voltages at both ends of the ferroelectric capacitors in the first row of memory cells are-2.5V, 0V, -2.5V and 0V from left to right, respectively, ferroelectric polarization inversion occurs in the ferroelectric capacitors in the first and third memory cells, and the ferroelectric capacitors in the second and fourth memory cells are written with the memory information "0", and the ferroelectric polarization inversion does not occur in the ferroelectric capacitors in the second and fourth memory cells, so that the memory information is unchanged. Next, GBL _0,0 、GBL _1,0 、GBL _0,1 、GBL _1,1 、GPL ₀ And GPL ₁ The voltage of (2) is set at 0V, and then EN is applied ₀ And WL (WL) _0,0 The write operation is completed by placing at 0V.

The read operation is performed on the general array shown in fig. 4, specifically, the first row of memory cells, and since four memory cells from left to right have been written with "0", "1", "0", and "1", the corresponding read information should also be "0", "1", "0", and "1". First, GBL is set _0,0 、GBL _1,0 、GBL _0,1 And GBL _1,1 Put in a floating state, GPL0 and GPL1 are precharged to 0V. Then EN is carried out ₀ And WL (WL) _0,0 Placed at 2.5V, EN ₁ 、WL _1,0 、WL _0,1 And WL (WL) _1,1 Is placed at 0V. At this time, the transistors connecting the global bit line and the basic bit line are turned on, the transistors connecting the global plate line and the basic plate line are turned on, and the transistors in the memory cells of the first row are all turned on. Thus, LBL ₀₀ 、LBL ₁₀ 、LBL ₀₁ And LBL ₁₁ Also in a floating state, LPL ₀₀ And LPL ₀₁ The voltages of (2) are all 0V and LBL ₀₂ 、LBL ₁₂ 、LBL ₀₃ 、LBL ₁₃ 、LPL ₁₀ 、LPL ₁₁ 、LPL ₀₂ 、LPL ₀₃ 、LPL ₁₂ And LPL ₁₃ The original voltage is kept unchanged. Next, GPL is set ₀ And GPL ₁ Is set at 2.5V, thus LPL ₀₀ And LPL ₀₁ The voltages of (2) are 2.5V. At this time, the voltages across the ferroelectric capacitors in the first row of memory cells are 2.5V, the second and fourth memoriesFerroelectric capacitor of the memory cell is subjected to ferroelectric polarization inversion, ferroelectric capacitor of the first and third memory cells is not subjected to ferroelectric polarization inversion, GBL _1,0 And GBL _1,1 Becomes 0.9V, is higher than the reference voltage V _REF =0.5v, reference voltage V _REF =0.5v above GBL _0,0 And GBL _0,1 Is 0.1V. After being amplified by a sensitive amplifying circuit, GBL _1,0 And GBL _1,1 The voltage of (2) becomes 2.5V, GBL _0,0 And GBL _0,1 The voltage of (2) becomes 0V. Thereby completing the read-out operation.

The following performs a rewrite operation on the overall array shown in fig. 4, specifically, a rewrite operation on the first row of memory cells, and since four memory cells from left to right have been read out of "0", "1", "0" and "1", the corresponding rewrite information should also be "0", "1", "0" and "1". Specifically, the voltages of the various portions of the overall array shown in FIG. 4 continue the state at the end of the read operation described above, i.e., GBL _1,0 And GBL _1,1 Is 2.5V, GBL _0,0 And GBL _0,1 Is 0V, EN ₀ And WL (WL) _0,0 2.5V, EN ₁ 、WL _1,0 、WL _0,1 And WL (WL) _1,1 0V, GPL ₀ And GPL ₁ Is 2.5V. At this time, the voltages across the ferroelectric capacitors in the first row of memory cells are-2.5V, 0V, -2.5V, and 0V in this order from left to right, and the first and third memory cells complete the overwriting of "0". Next, GPL is set ₀ And GPL ₁ The ferroelectric capacitors placed at 0V, the voltages across the ferroelectric capacitors in the first row of memory cells are 0V, 2.5V, 0V and 2.5V in this order from left to right, and the second and fourth memory cells complete the overwriting of "1". Next, GBL _0,0 、GBL _1,0 、GBL _0,1 And GBL _1,1 The voltage of (2) is set at 0V, and then EN is applied ₀ And WL (WL) _0,0 And (5) placing at 0V to finish the rewriting operation.

While the invention has been described in terms of preferred embodiments, it is not intended to be limiting. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (3)

1. A ferroelectric random access memory array comprising a general array of basic arrays repeatedly arranged in a lateral direction and a longitudinal direction; in the global array, each global bit line in the same column basic array is connected together according to respective columns, each word line in the same row basic array is connected together according to respective rows, control lines of the same row basic array are connected together to form a row control line, and global plate lines of the same column basic array are connected together to form a global plate line of the column;

the basic array comprises memory cells, word lines, control lines, basic plate lines, overall plate lines, basic bit lines and overall bit lines, and the memory cells are repeatedly arranged into a matrix structure along the transverse direction and the longitudinal direction; the word lines of the memory cells in the same row are connected to the same word line, the plate lines of the memory cells in the same row are connected to the same basic plate line, the bit lines of the memory cells in the same column are connected to the same basic bit line, the word lines are parallel to the basic plate line, and the word lines are perpendicular to the basic bit line; each basic plate line is connected to the same overall plate line of the basic array through a transistor, the drain electrode of the transistor is connected with the basic plate line, the source electrode of the transistor is connected with the overall plate line, and the grid electrode of the transistor is connected with word lines of the same row; each basic bit line is connected to the corresponding overall bit line of each column through a transistor, the source electrode of the transistor is connected with the basic bit line, the drain electrode of the transistor is connected with the overall bit line, and the grid electrode of the transistor is connected with the same control line of the basic array; when the basic array is composed of m rows and n columns of memory cells, the basic array comprises m transistors for connecting basic plate lines and overall plate lines, n transistors for connecting basic bit lines and overall bit lines, m basic plate lines, one overall plate line, n basic bit lines, n overall bit lines, m word lines and one control line, and the outgoing lines of the basic array are provided with one overall plate line, n overall bit lines, m word lines and one control line, and the total outgoing lines are (m+n+2);

the memory cell comprises a transistor, a ferroelectric capacitor, a word line, a bit line and a plate line, wherein the gate electrode of the transistor is connected with the word line, the drain electrode of the transistor is connected with the bit line, the source electrode of the transistor is connected with the upper polar plate of the ferroelectric capacitor, and the lower polar plate of the ferroelectric capacitor is connected with the plate line.

2. The ferroelectric random access memory array of claim 1, wherein each global bit line is connected to a corresponding sense amplifier circuit, each global plate line is connected to a corresponding driver circuit, each word line is connected to a corresponding driver circuit, and each control line is connected to a corresponding driver circuit.

3. A method of controlling a ferroelectric random access memory array according to claim 1, comprising the steps of:

when writing data into the ferroelectric random access memory array, writing corresponding storage information into one row of storage units at a time, wherein the specific steps are as follows:

pre-charging the total bit line corresponding to the unit needing to be written with the storage information to a voltage value needing to be written, then placing the voltages of the control line and the word line at an effective voltage, turning on a transistor connecting the total bit line and the basic bit line, turning on a transistor connecting the total plate line and the basic plate line, and turning on all transistors in the selected memory units in the middle row, so that the voltages of the total bit line are all transmitted to the corresponding basic bit line, the voltages of the total plate line are all transmitted to the corresponding basic plate line, and at the moment, the voltages of the memory units needing to be written with the information '1' are high-potential, and the voltages of the memory units needing to be written with the information '0' are low-potential; firstly, setting the overall plate line voltage at a low potential to complete writing of information '1', and then setting the overall plate line voltage at a high potential to complete writing of information '0'; after the writing is finished, the voltages of the overall plate line and the overall bit line are restored to low potential, and the voltages of the control line and the word line are restored to invalid voltage;

when reading data in the ferroelectric random access memory array, reading information stored in one row of memory cells at a time, wherein the method comprises the following specific steps:

firstly, setting the general bit line corresponding to the unit to be read in a floating state, then setting the voltages of the control line and the word line in an effective voltage, at the moment, starting the transistors connecting the general bit line and the basic bit line, starting the transistors connecting the general plate line and the basic plate line, and completely starting the transistors in the memory units of the selected middle row, so that the voltages of the general bit line are completely transmitted to the corresponding basic bit line, and the voltages of the general plate line are completely transmitted to the corresponding basic plate line, and at the moment, the basic bit line is also in a floating state; then the overall plate line voltage is set to be high, dielectric charges are provided by the cells storing 0 in the selected row so that the corresponding overall bit line voltage is raised, ferroelectric polarization inversion can also occur to the cells storing 1 so that the overall bit line voltage corresponding to the cells storing 1 is higher than the overall bit line voltage corresponding to the cells storing 0; the total bit line voltage is compared with the reference voltage through the sensitive amplifying circuit, the total bit line voltage corresponding to the unit storing '1' becomes high potential, and the total bit line voltage corresponding to the unit storing '0' becomes low potential;

after the read operation is completed, when the read selected row information needs to be rewritten, the specific steps are as follows:

at the end of the reading operation, the total bit line voltage is compared with the reference voltage through the sense amplifying circuit, the total bit line voltage corresponding to the cell storing '1' becomes high potential, the total bit line voltage corresponding to the cell storing '0' becomes low potential, and the cell storing '0' automatically completes the rewriting because the total plate line voltage is high potential at the moment; then the overall plate line voltage is set at a low potential, and the cell storing '1' will also complete the overwriting; after the overwriting is completed, the voltages of the global bit line and the global plate line are restored to the low potential, and the voltages of the control line and the word line are restored to the invalid voltage.