JPH08124378A - Ferroelectric memory - Google Patents

Abstract

PURPOSE: To provide a ferroelectric memory miniaturized and improved in storage capacity by installing memory cells, a voltage impressing means and a means which detects the difference in polarized conditions of a ferroelectric film as the difference in threshold voltages of FET. CONSTITUTION: When voltage VCB of a high, positive value V1 is applied to a memory cell which has a ferroelectric body held at the nonpolarized state C or a negatively and remarkably polarized state B, the ferroelectric body becomes a positively saturated state D of polarization. When VCB is made zero this time, the ferroelectric body becomes a state A of large, positive polarization. Next, when a high, negative potential of -V1 is applied to a memory cell which has a ferroelectric body held at the nonpolarized state or a positively, remarkably polarized state A, the ferroelectric body becomes a state E in which its polarization is negatively saturated. When VCB is made zero this time, the ferroelectric body becomes a polarized state B. Thus, by realizing three differently polarize states A, B and C, the threshold value of the memory cell can be controlled to three different types of states, and hence three values of information are stored into the memory cell in accordance with these threshold values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory,
In particular, the present invention relates to a non-volatile ferroelectric memory capable of storing information of three values or more.

[0002]

2. Description of the Related Art Ferroelectric materials have a hysteresis characteristic in which the electric field and the magnitude of polarization are non-linear and the magnitude of polarization varies depending on the history of the applied electric field. A ferroelectric memory is a memory that stores information by utilizing this hysteresis characteristic, and at present, a memory having a memory cell in which a capacitor using a ferroelectric as a capacitive insulating film and a transistor are combined is mainly proposed. .

Regarding such a ferroelectric memory, it has been proposed to store information of three or more values in one memory cell from the viewpoint of expanding the memory capacity. For example,
JP-A-5-28773 and JP-A-5-28774.
Japanese Patent Laid-Open Publication No. 2004-242242 discloses a capacitor using a ferroelectric substance as a capacitance insulating film. By arranging a plurality of electrodes in parallel on both front and back surfaces of one ferroelectric substance and controlling the electric field between the electrodes,
A ferroelectric memory is disclosed in which one memory cell stores three or more values of information.

Further, Japanese Patent Laid-Open No. 5-89691 discloses that
A ferroelectric memory is disclosed in which one capacitor using a ferroelectric as a capacitive insulating film and four MOSFETs can change the polarization state of the capacitor to store three values.

[0005]

However, in a ferroelectric memory having a memory cell in which a capacitor using a ferroelectric as a capacitance insulating film and a transistor are combined as described above, particularly, information of three or more values is stored. If you try to
Since the number of elements per memory cell increases, there is a problem that it is not suitable for expanding the memory capacity in the end.

On the other hand, a nonvolatile ferroelectric memory in which a memory cell is composed of only one field effect transistor has been proposed by using a ferroelectric material as a part of a gate insulating film of the field effect transistor ( "Physics of
ferroelectric nonvolatile memory field effect trans
istor "SLMiller and PJMcWhorter, J.Appl.Phy
s.72 (12), 15 December 1992). However, this document describes a ferroelectric memory transistor (FEMFET).
However, there is no disclosure regarding the use of FEMFET for storing three-valued information or more.

Therefore, the present invention provides a ferroelectric memory in which a memory cell is composed only of a field effect transistor using a ferroelectric material as a gate insulating film and at the same time can store information of three values or more. The purpose is to do.

[0008]

In order to achieve the above object, a ferroelectric memory of the present invention comprises a memory cell comprising a field effect transistor having a gate insulating film containing a ferroelectric film, and the above field effect. A first voltage between the gate electrode of the transistor and the substrate portion, a second voltage having a polarity opposite to that of the first voltage, and the first voltage within a range in which the ferroelectric film is not in a saturated polarization state. Comprises voltage applying means for applying respective third voltages having different magnitudes, and detecting means for detecting a difference in polarization state of the ferroelectric film as a difference in threshold voltage of the field effect transistor. .

In one aspect of the present invention, the first voltage and the second voltage are voltages that bring the ferroelectric film into a saturated polarization state, respectively.

In one aspect of the present invention, the voltage applying means applies a fourth voltage having a polarity opposite to that of the third voltage between the gate electrode and the substrate portion.

In one aspect of the present invention, the third voltage is a voltage that makes the ferroelectric film substantially non-polarized after the voltage is removed.

In one aspect of the present invention, the voltage applying means has a fifth voltage having an intermediate magnitude between the first voltage and the third voltage and a polarity opposite to the fifth voltage. And a sixth voltage is applied between the gate electrode and the substrate portion.

[0013]

The polarization state of the ferroelectric film can be changed to at least three kinds because the gate electrode of the memory cell is provided with means for applying at least three kinds of voltages having different sizes. Therefore, at least ternary information can be stored.

Further, by applying a voltage which brings the ferroelectric film into a saturated polarization state or a voltage which brings the ferroelectric film into a non-polarized state after the voltage is removed, the difference in the polarization state of the ferroelectric film is caused. Becomes clear and its detection becomes easy.

Further, it is possible to change the polarization state of the ferroelectric film into four or more kinds by variously selecting the applied voltage, and in that case, more information can be stored.

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 shows a total of four memory cells M, two in each of the vertical and horizontal directions, of the memory cells constituting the memory cell array of the ferroelectric memory according to the embodiment of the present invention.
It is a partial plan view showing a state in which C ₁ to MC ₄ are connected. In FIG. 1, bit lines BL ₁ and BL ₂ are formed in the direction orthogonal to the word lines WL ₁ and WL ₂ , respectively. A source line SL is formed between the word lines WL ₁ and WL _{2 in} parallel with them. Further, below the bit lines BL ₁ and BL ₂ , well lines BUL ₁ and BUL ₂ are formed in parallel with them.

In the bit contacts BC ₁ and BC ₂ , the bit line BL ₁ and the drain 21 of the memory cell MC ₁ are connected.
And the drain 23 of the memory cell MC ₃ are connected to each other. In the bit contacts BC ₃ and BC ₄ ,
It is drain 24 Togaotto s connection of the bit line BL ₂ and the drain 22 and the memory cell MC ₄ of the memory cell MC _2. In the source contact SC ₁ , the source line SL
And a source 25 common to the memory cells MC ₁ and MC ₃ are connected. In the source contact SC ₂ , the source line SL and the source 26 common to the memory cells MC ₂ and MC ₄ are connected.

FIG. 2 is a sectional view taken along line II-II of FIG. In FIG. 2, well lines BUL ₁ and BUL ₂ which are well regions are formed on a silicon substrate 31. A word line WL ₁ that is a gate electrode is formed on the silicon substrate 31 via an insulating film (not shown), and the bit lines BL ₁ and BL ₂ are formed on the word line WL _1.
Are formed respectively. Word line WL ₁ and well line BU
A PZT film 32, which is a ferroelectric film, is formed as a gate insulating film between L ₁ and BUL ₂ .

FIG. 3 is a sectional view taken along line III-III in FIG. In FIG. 3, a silicon substrate 31 includes well lines BUL ₁ and BUL ₂ and a source 25 surrounded by these well lines.
26 are formed respectively. Further, on the silicon substrate 31, bit lines BL ₁ and B ₁ are formed via an insulating film (not shown).
L ₂ and source line SL are formed respectively. The source line SL is connected to the sources 25 and 26 via source contacts SC ₁ and SC ₂ , respectively.

FIG. 4 is a sectional view taken along line IV-IV in FIG. In FIG. 4, the well line BUL of the silicon substrate 31
Drains 21 and 23 and a source 25 are formed in the inside of ₁ , respectively. The PZ is formed on the silicon substrate 31 between the drain 21 and the source 25 and between the drain 23 and the source 25.
Word lines WL ₁ and WL ₂ are formed via the T film 32, respectively. Further, the bit lines BL ₁ and BL ₂ formed on the word line WL ₁ have bit contacts BC ₁ and BC _{2 respectively.}
Are connected to the drains 21 and 23, respectively.

FIG. 5 is an equivalent circuit diagram of the memory cell array shown in FIG. In FIG. 5, the word line WL ₁ is connected to the gate electrodes of the memory cells MC ₁ and MC ₂ , respectively, and the word line WL ₂ is connected to the gate electrodes of the memory cells MC ₃ and MC ₄ , respectively. The bit line BL ₁ is connected to the drains of the memory cells MC ₁ and MC ₃ , respectively, and the bit line WL ₂ is connected to the drains of the memory cells MC ₂ and MC ₄ , respectively. Also, the well line BUL ₁
Are connected to the substrate terminals of the memory cells MC ₁ and MC ₃ , respectively, and the well line BUL ₂ is connected to the memory cells MC ₂ and MC ₄
Are respectively connected to the board terminals. Furthermore, the source line S
L is respectively connected to the sources of the memory cells MC ₁ to MC _4.

FIG. 6 shows the relationship between the voltage V _GB (= the potential of the gate electrode−the potential of the well) applied to the gate electrode of each memory cell of this embodiment and the magnitude of the polarization of the ferroelectric substance (hysteresis). Is a graph showing characteristics).

First, when a positive high voltage of V _GB = V ₁ is applied to a memory cell having a ferroelectric substance in a non-polarized state "C" or a state in which a large negative polarization is given, a ferroelectric substance is applied. Becomes a state "D" in which the polarization is positively saturated. Then, if V _GB = 0 at this time, the ferroelectric substance is in a state "A" in which the ferroelectric substance is highly polarized.

Next, when a high negative voltage of V _GB = -V ₁ is applied to the memory cell having the ferroelectric substance in the unpolarized state "C" or the positively highly polarized state "A", the strong voltage is applied. The dielectric is in the state "E" where the polarization is negatively saturated. And
At this time, if V _GB = 0, the ferroelectric substance is in a state "B" in which it is highly negatively polarized.

Next, for a memory cell having a ferroelectric substance in the state "B" which is highly negatively polarized, V _GB = appropriately selected.
When a positive high voltage of V ₂ (0 <V ₂ <V ₁ ) is applied, the ferroelectric substance is weaker than the state “D” and is in the positive state “F”.
Becomes When V _GB = 0 at this time, the ferroelectric substance is in a non-polarized state (non-polarized state) “C” (or a state in the vicinity thereof).

Next, when a negative high voltage of V _GB = -V ₂ is applied to the memory cell having the ferroelectric substance in the state "A", which is largely polarized positively, the ferroelectric substance is brought to a state higher than that in the state "E". A weakly negatively polarized state "G" is obtained. And at this time V _GB
= 0, the ferroelectric substance is not polarized "C"
(Or a state in the vicinity thereof).

FIG. 7 shows the relationship between the drain current I of the memory cell and the gate voltage V _GB when the ferroelectric substance is in the states “A”, “C” and “B” corresponding to FIG. 6, respectively. It is a graph. In FIG. 7, the left curve corresponds to the state “A”, the center curve corresponds to the state “C”, and the right curve corresponds to the state “B”.

In the state "A", since the ferroelectric substance is highly polarized, the threshold voltage V of the memory cell is increased.
_tA is the threshold voltage V _tC in the non-polarized state “C”
Is smaller than. Further, in the state "B", the ferroelectric substance is highly negatively polarized, so that the threshold voltage V _tB of the memory cell is not polarized "C".
It is larger than the threshold voltage V _{tC at} .

As described above, by changing the ferroelectric substance into three polarization states "A", "C" and "B",
Since the threshold voltage of the memory cell can be controlled to three different types, ternary information can be stored in the memory cell according to the value of the threshold voltage.

For example, in the case of storing four values in one memory cell, V _GB = V ₃ (V ₂ <V ₃ which is appropriately selected for the memory cell having the ferroelectric substance in the state “B”). <V
By applying V _GB = 0 after applying the positive high voltage of ₁ ), the ferroelectric substance is brought into a state having a polarization of approximately half of the state “A”. Further, by applying a negative high voltage of V _GB = −V _{3 to} the memory cell having the ferroelectric substance in the state “A” and then setting V _GB = 0, the ferroelectric substance is abbreviated to the state “B”. The polarization is about half. As a result, each memory cell can have two states other than the states "A" and "B", and four-value storage becomes possible.

In this way, the gate voltage V of each memory cell is
_By appropriately adjusting _GB between the voltage V ₂ and the voltage V ₁ , the threshold voltage of each memory cell is changed between the state “A” and the state “C” and between the state “B” and the state “C”. It can be changed arbitrarily. Therefore, it is possible to store information of four or more values in each memory cell corresponding to them.

FIG. 8 shows a circuit block diagram of the ferroelectric memory of this embodiment.

In FIG. 8, the memory cell array MARY
Is a matrix of memory cell transistors using a ferroelectric film as a gate insulating film.
The address input terminal AD is a terminal for inputting a signal for determining a memory cell transistor selected at the time of rewriting or reading. The control input terminal CNT ₀ is a terminal for inputting a signal for selecting a mode such as rewriting and reading. The data input / output terminal DIO is a terminal for outputting the stored data at the time of reading and inputting the data to be written to the memory cell transistor at the time of rewriting.

The address buffer ADBF is a circuit which latches the signal from the address input terminal AD and outputs the output signal AX to the column decoder RDEC, the row decoder CDEC and the well line selection circuit BUDEC, respectively.

Column decoder RDEC, row decoder CDEC
The well line selection circuit BUDEC is a circuit for selecting a word line (column line) WL, a bit line (row line) BL, and a well line BUL of the memory cell array MARY during rewriting or reading.

The multiplexer MPX is a row decoder CD
The multiplexer selection signal PY from the EC is used as a control input, and at the time of reading, only the selected bit line is brought into conduction with the data line DB, and the non-selected bit line is brought out of conduction, and at the time of rewriting, all the bit lines are made into data lines. It is a circuit for disconnecting from DB.

The chip control circuit CCNT uses a signal from the control input terminal CNT ₀ to select a control signal P for selecting a mode such as a chip selection state, a read state or a rewrite state.
Of DQ, RD and CNT ₁ , the control signal PDQ is output to the address buffer ADBF, and the control signal RD is output to the row decoder CDEC, the sense amplifier circuit SAMP, the data output buffer DOBF, the source line voltage control circuit SLCNT and the well potential control circuit BUCNT. And the control signal CNT ₁ to the write state control circuit WCNT.

The write state control circuit WCNT uses the output CNT ₁ of the chip control circuit CCNT and the output DAT of the input data / output data comparison circuit DPRG as input signals, and applies them to the word line WL and the well line BUL during rewriting. among the signals PRG _0, PRG ₁ for controlling the voltage, the signal PRG ₀ column decoder RDEC, the well potential control circuit BUCNT, positive high-voltage generation / control circuit PVCNT
And output to the negative high voltage generation / control circuit NVCNT,
This is a circuit that outputs the signal PRG ₁ to the row decoder CDEC, the source line voltage control circuit SLCNT, and the well potential control circuit BUCNT, respectively.

The positive high voltage generation / control circuit PVCNT and the negative high voltage generation / control circuit NVCNT use the output PRG ₀ of the write state control circuit WCNT as an input signal, and the positive / negative high voltage applied to the word line WL and the well line BUL at the time of rewriting. This is a circuit for respectively generating signals V _P and V _N for generating / controlling a voltage. These signals V _P and V _N are supplied to the well potential control circuit BUCNT and the column decoder RDEC, respectively.

The well potential control circuit BUCNT has an output RD of the chip control circuit CCNT and a write state control circuit WC.
NT outputs PRG ₀ and PRG ₁ , positive high voltage generation / control circuit PVCNT output V _P and negative high voltage generation / control circuit N
A signal BX for controlling the voltage applied to the well line BUL according to the difference in the mode such as rewriting and reading and the difference in the data to be written by using the output V _N of VCNT as an input signal.
Is output to the well line selection circuit BUDEC.

The source line voltage control circuit SLCNT receives the output PRG ₁ of the write state control circuit WCNT and the output RD of the chip control circuit CCNT as input signals, and according to the difference in the mode such as rewriting and reading and the difference in the data to be written, This is a circuit that controls the voltage applied to the source line SL.

The data output buffer DOBF is a circuit which receives the output RD of the chip control circuit CCNT as a control input and latches the output DOUT of the sense amplifier circuit SAMP at the time of reading and outputs it to the data input / output terminal DIO.

The data input buffer DIBF is a circuit that latches an input from the data input / output terminal DIO when data is rewritten and outputs the output signal DIN to the input data / output data comparison circuit DPRG.

The sense amplifier circuit SAMP uses the output RD of the chip control circuit CCNT as a control input, the data line DB as a data input, and the read data as a data output buffer D.
The signals are output as output signals DOUT to the OBF and the input data / output data comparison circuit DPRG.

Input data / output data comparison circuit DPRG
Is the output DOUT of the sense amplifier circuit SAMP and the output DIN of the data input buffer DIBF as input signals,
It is a circuit that outputs a signal DAT for controlling the write state control circuit WCNT according to the result of comparing the respective signals.

Next, the rewriting and reading operations of the ferroelectric memory of this embodiment will be described with reference to FIGS. In the following description, three data “1”,
“0” and “−1” correspond to the three polarization states “A”, “C” and “B” described in FIG. 6, respectively.

[Table 1] shows rewriting and reading operations of the ferroelectric memory of this embodiment.

[0049]

[Table 1]

First, the rewriting operation will be described.
First, when the rewrite mode is selected by the chip control circuit CCNT in FIG. 8, for example, the signal PDQ becomes a high voltage and the address buffer ADBF is activated. Then, one word line and one well line are selected in the memory cell array MARY. In the rewrite mode, unselected word lines, all bit lines and source lines are
It is floating (or high impedance).

When data corresponding to "1" is input from the data input / output terminal DIO (step S1 in FIG. 9), the data is written into the write state control circuit through the data input buffer DIBF and the input data / output data comparison circuit DPRG. This write state control circuit WCN is sent to WCNT.
The control output PRG ₀ from T puts the positive high voltage generation / control circuit PVCNT and the negative high voltage generation / control circuit NVCNT into the “1” write state, respectively. And a positive high voltage V
_1/2 and negative high voltage -V _1/2 respectively occurred, respectively output to the column decoder RDEC and the well potential control circuit BUCNT. On the other hand, the control output PRG ₀ from the write state control circuit WCNT is also input to the column decoder RDEC and the well potential control circuit BUCNT, respectively, and is selected by the address input signal input from the address input terminal AD via the address buffer ADBF. positive high voltage V _1/2 to a word line, a negative high voltage -V in selected wells line
_1/2 are respectively applied. Also, the non-selected well line positive high voltage V _1/2 is applied.

For example, in FIG. 5, when the memory cell transistor MC ₁ is selected, the word line WL ₁ and the well line BUL _{1 are} respectively selected, and a positive voltage is applied between the gate electrode and the well of the memory cell transistor MC ₁ . High voltage V
₁ is applied, and the polarization state “C” or “B” changes to the polarization state “D” in FIG. 6, for example. Thereafter, the gate electrode of the memory cell transistor MC ₁ - by the 0V voltage is applied between the well, the polarization state "D" is changed to the state "A". That is, the "1" is written to the memory cell transistors MC ₁ selected (step S2 in FIG. 9).

At this time, the memory cell transistor M
In C ₂ , the voltage between the gate electrode and the well is 0 V, so the polarization state does not change and the data cannot be rewritten. In addition, memory cell transistors MC ₃ and MC ₄
Since the word line WL ₂ is floating, no positive or negative high voltage is applied between the gate electrode and the well, so that the polarization state does not change and the data cannot be rewritten. That is, “1” is written only in the selected memory cell transistor MC ₁ .

Next, "-1" is input from the data input terminal DIO.
When data corresponding to is input (step S in FIG. 9)
1), by the same operation as when the corresponding data is input to the "1", a negative high voltage -V _1/2 to the selected word line and unselected well line, a positive high voltage to a selected well line V ₁
/ 2 is applied respectively. Therefore, a negative high voltage -V is applied between the gate electrode and the well of the selected memory cell transistor.
₁ is applied, and in FIG. 6, for example, what was in the polarization state “A” or “C” is changed to the polarization state “E”.
After that, it changes to "B". That is, "-1" has been written in the selected memory cell transistor (step S3 in FIG. 9). Even when "-1" is written, the data of the non-selected memory cell transistor cannot be rewritten for the same reason as when writing "1".

Next, when data corresponding to "0" is input from the data input terminal DIO (step S in FIG. 9).
1) First, a positive high voltage V ₁ / is applied to the selected word line.
2, high voltage -V _1/2 negative in selected wells line, the V _1/2, respectively applied to the non-selected well line, forcibly rewritten to "1" to the memory cell transistor selected (Fig. 9 step S4). Then, a negative high voltage -V _2/2 to the selected word line, a positive high voltage V to a selected well line
Applying a voltage V ₂ between the well - _2/2, to the non-selected well line gives people husband -V _2/2, the gate electrode of the memory cell transistor selected. Then, by setting the voltage applied between the gate electrode and the well of the selected memory cell transistor to 0V, the selected memory cell transistor is rewritten to "0" (step S5 in FIG. 9). Incidentally, instead of the memory cell transistor "1" is selected from the rewritten to "-1", the selected word line to the positive high voltage V _2/2, selected negatively well-ray high voltage -V _2/2, V _2/2 to the non-selected well line
May be applied to rewrite the selected memory cell transistor to “0”.

Next, another method of writing "0" will be described. When data corresponding to "0" is input from the data input terminal DIO (step S1 in FIG. 9), first,
The pre-writing read mode is set, and one word line and one bit line are selected according to the address input signal.
At this time, for example, 5V is applied to the selected word line, 1V is applied to the selected bit line, and 0V is applied to the unselected word line, the well line, the source line, and the unselected bit line. As a result, "1", "0", or "-" depending on the difference in threshold voltage of the selected memory cell transistor.
Data corresponding to 1 ″ is output from the sense amplifier circuit SAMP and is input to the input data / output data comparison circuit DPRG.

Input data / output data comparison circuit DPRG
Is “1” → “0”, “−1” → in accordance with the read data from the selected memory cell in the pre-write read.
Rewriting "0" or "0" → "0" outputs different control signals to the write state control circuit WCNT. The write state control circuit WCNT uses the control signal from the input data / output data comparison circuit DPRG to output the column decoder RD.
EC, well potential control circuit BUCNT, positive high voltage generation /
Control circuit PVCNT and negative high voltage generation / control circuit NVC
The control signal PRG ₀ is output to NT and the row decoder CD is output.
The control signal PRG ₁ is output to the EC, the source line voltage control circuit SLCNT and the well potential control circuit BUCNT, respectively. Then, all the bit lines and the source lines are in a floating state, and a predetermined high voltage is applied to each of the selected word line and well line.

[0058] When rewriting the data of the memory cells to "1" → "0", for example, a selected word line and unselected well line -V _2/2, then the selection well line and V _2/2, unselected word lines, Floating source lines and all bit lines. As a result, only the data of the selected memory cell can be rewritten to "0".

On the other hand, the data in the memory cell is changed to "-1" →
"0" when the rewritten, for example V _2/2 the selected word line and unselected well line, -V _2/2 SELECT well line
And the non-selected word lines, source lines and all bit lines are made floating. As a result, only the data of the selected memory cell can be rewritten to "0".

Further, when the data in the memory cell is not rewritten as "0", for example, the selected word line and all the well lines are set to 0V, and the non-selected word lines, the source lines and all the bit lines are made floating.

When reading data from a memory cell,
The output of the sense amplifier circuit SAMP is output as read data to the data input / output terminal DIO through the data output buffer DOBF by the same operation as in the pre-write read mode when writing “0”.

FIG. 10 shows the sense amplifier circuit of FIG. 8 in more detail. RD is a signal that activates the sense amplifier circuit, and DOUT ₁ and DOUT ₂
Are data outputs, and DB is a memory read data input. IV ₀₁ , IV ₀₂ , IV ₀₄ , and IV ₀₅ are inverter circuits each composed of a MOS transistor, and AND ₀₃ is M
A 2-input AND circuit (A
ND circuit). Also, MP ₀₁ , MP ₀₂ , ..., MP ₀₆
Is a P-channel enhancement type MOS transistor,
_{MN 01, MN 02, ...,} MN 10 is N-channel enhancement type MOS transistor, RCEL _1, RCEL ₂ is a memory cell for reference.

In FIG. 10, the node N ₂₀ is a transistor MP.
The drain of _01, the drain of MN _01, the drain of MN ₀₂ and the gate of MN ₀₃ are respectively connected, and the node N ₂₁ is the drain and gate of the transistor MP ₀₂ , the drain of MN ₀₃ , the gate of MN ₀₅ and the circuit block DAMP. ₁
And DAMP ₂ are connected to the gates of the respective transistors MN ₀₅ , and the node N ₂₃ is connected to the drain of the transistor MP ₀₃ , the drain of MN ₀₅ and the input of the inverter circuit IV ₀₂ . The node N ₂₂ is connected to the drain and gate of the transistor MP ₀₅ , the drain of MN ₀₇ and the gate of MN ₀₆ , and the node N ₂₄ is connected to the drain of the transistor MP ₀₄ , the drain of MN ₀₆ , and M.
They are respectively connected to the gates and MP ₀₄ of P _03, the node N ₂₅ is the source of the transistor MN _05, is connected to the drain of the source and the MN ₀₄ in the MN _06, the node N ₂₆ is the drain of the transistor MP _06, the MN ₀₉ The drain, the drain of MN ₁₀ and the gate of MN ₀₇ are connected to the node N
₂₇ is connected to the source of the transistor MN ₀₇ , the drain of MN ₀₈ and the gate of MN ₀₉ , respectively.

DAMP ₁ is a transistor MP ₀₃ , MP
₀₄ , MP ₀₅ , MP ₀₆ , MN ₀₄ , MN ₀₅ , MN ₀₆ , M
N ₀₇ , MN ₀₈ , MN ₀₉ , MN ₁₀ , inverter circuit IV ₀₂
And a memory cell RCEL ₁ for reference, and DAMP ₂ is a circuit block having transistors and connections similar to those of DAMP ₁ .

In FIG. 10, the activation signal RD indicates the inverter circuit IV ₀₁ and the transistor MN of the circuit block DAMP ₁ .
_{04 and} the gate of the transistor MN ₀₄ (not shown) of the circuit block DAMP _{2 respectively} , and the output PDQB of the inverter circuit IV ₀₁ is the transistors MP ₀₁ and M.
Inputs are made to the respective gates of N ₀₁ , MP ₀₆ and MN ₁₀ and to the gates of the transistors MP ₀₆ and MN ₁₀ (neither shown) of the circuit block DAMP ₂ . The memory read data input DB is the gate of the transistor MN ₀₂ and MN _03.
Is input to each source. SO ₁ is the circuit block DA
The output of the inverter circuit IV ₀₂ of MP ₁ and the input of the inverter circuit IV ₀₄ , SO ₂ is the circuit block DAMP ₂
The output of the inverter circuit IV ₀₂ (not shown) and the input of the inverter circuit IV ₀₅ . Data output D
OUT ₂ is equal to the output SO _1B of the inverter circuit IV ₀₄ . SO _2B is the output of the inverter circuit IV ₀₅ and the input of the AND circuit AND ₀₃ . The other input of the AND circuit AND ₀₃ is the output SO _1B of the inverter circuit IV ₀₄ .
The data output DOUT ₁ is the output of the AND circuit AND ₀₃ . The signal line REF ₁ is the source of the transistor MN ₀₈ of the circuit block DAMP ₁ and the reference memory cell RC.
It is connected to the drain of EL ₁ . Although not shown, the same signal line is also provided for the reference memory cell RCEL ₂ of the circuit block DAMP ₂ . N ₃₀ is a ground node, and the inverter circuit IV _01-
IV ₀₅ and each ground terminal of the AND circuit AND ₀₃ (none of which are shown), transistors MN ₀₁ , MN ₀₂ , MN ₀₄ , M
The source terminals of N ₀₉ and MN _{10 and} the source terminals of the reference memory cells RCEL ₁ and RCEL ₂ are respectively connected. N ₃₁ is a power supply node, each power supply terminal of the inverter circuits IV _{01 to} IV ₀₅ and the AND circuit AND ₀₃ (none of which are shown), each source terminal of the transistors MP _{01 to} MP ₀₆ , and the gate terminal of the transistor MN ₀₈ . Connected to each.

In FIG. 10, the activation signal RD is "H".
When the potential is reached, the memory read data input DB becomes the same potential as the bit line of the selected memory cell. Since the output PDQB of the inverter circuit IV ₀₁ becomes the “L” potential, the transistor MP ₀₁ is turned on and the transistor MN ₀₁ is turned on.
₀₁ is turned off, and the potential of the node N ₂₀ rises from 0V. When the potential of the node N ₂₀ rises, the transistor MN ₀₃ is turned on and the memory read data input D
B has a potential obtained by subtracting the threshold voltage of the transistor MN ₀₃ from the potential of the node N ₂₀ . However, when the potential of the memory read data input DB is higher than the threshold voltage of the transistor MN _02, the transistor MN ₀₂ is turned on, to suppress the increase in potential of the memory read data input DB. Therefore, when the activation signal RD becomes "H", the memory read data input DB becomes an intermediate value between 0V and the power supply voltage, for example, 2V. At this time, if the memory cell to be read is in the ON state, a current flows from the memory read data input DB toward the source of the memory cell, and the potential of the memory read data input DB is slightly lowered to, for example, 1.8V. . Since the current supply at this time is performed via the transistor MP _02, by appropriately selecting the size of the transistor MP _02,
The potential of the node N ₂₁ is much lower than that of the memory read data input DB, and is, for example, 4.2V to 3.5V. Further, since the potential of the node N ₂₁ is proportional to the amount of current flowing through the memory cell, the transistors MP ₀₁ , M
P ₀₂ , MN ₀₂ and MN ₀₃ are memory read data input D
This means that the potential fluctuation of B is amplified. Transistors MP ₀₃ , MP ₀₄ , MN ₀₄ , MN ₀₅ and MN ₀₆ are differential amplifiers, and nodes N ₂₁ and N ₂₂ are differential inputs. The transistors MP ₀₅ , MP ₀₆ , MN ₀₇ , MN ₀₉ and MN ₁₀ are transistors MP ₀₁ , MP ₀₂ , MN ₀₁ , MN ₀₂ and MN.
It is a circuit similar to _03, and operates similarly to the memory read data input DB for the signal line REF ₁ . The transistor MN ₀₈ serves to transfer the potential of the signal line REF ₁ to the node N ₂₇ .

Now, the threshold voltage of the memory cell to be read is, for example, 3 V, and the reference cell RCE
The threshold voltages of L ₁ and RCEL ₂ are, for example, 7 V and 2 respectively.
When it is V, the potential of REF ₂ <the potential of DB <the potential of REF ₁ and the output SO ₁ is “L” potential and the output SO ₂ is “H”.
It becomes an electric potential. The threshold voltage of the reference memory cell is set in advance in test mode, etc.
It will not be described in detail in this embodiment. As a result, data output DOU
T ₂ becomes “H” potential, and data output DOUT ₁ becomes “L” potential.

FIG. 11 shows the threshold voltage of the memory cell,
FIG. 11 is a diagram showing a correspondence between the data outputs DOUT ₁ and DOUT ₂ of FIG. 10 and 2-bit data. In FIG. 11, the upper one corresponds to the higher threshold voltage, and the lower one corresponds to the lower threshold voltage.

For example, the polarization state is "-1", that is, FIG.
When the state is “B”, the output of the sense amplifier circuit is D
OUT ₁ = “0” and DOUT ₂ = “0”. Similarly, when the polarization state is “0”, that is, the state “C” in FIG. 6, the output of the sense amplifier circuit is DOUT ₁ = “0”,
DOUT ₂ = “1”. Further, the state of polarization "1", that is, when the state "A" in FIG. 6, the output of the sense amplifier circuit DOUT ₁ = "1", DOUT ₂ =
It is "1".

As described above, in the ferroelectric memory of this embodiment, the memory cell transistors using the ferroelectric film as the gate insulating film are rewritten into the word lines and well lines of the memory cell array arranged in an array. When a positive high voltage or a negative high voltage is applied at times, V ₁ , V ₂ , and -V are generated as the potential difference between the gate and the well of the memory cell transistor.
By setting _one and four values of -V _2, causing three polarization states in the gate insulating film of the memory cell transistor, during read threshold voltage of the memory cell transistors in the three polarization states It is possible to write and read three-valued information to one memory cell transistor by utilizing the change in

Although the present invention has been described above with reference to one embodiment, the above embodiment is not intended to limit the present invention. For example, in the above-described embodiment, the word line and the well line have the same absolute value of the applied voltage at the time of rewriting, but it is not always necessary. Further, the potentials of the word line and the bit line at the time of reading may be different from those in the above-mentioned embodiments.

Further, the magnitude relation between the positive / negative of the polarization direction of the ferroelectric film and the threshold voltage V _t of the memory cell transistor does not need to be the same as in the above-mentioned embodiment, but the magnitude relation is opposite. Good.

In the above-described embodiment, the potential of the well, which is the substrate portion of each memory cell transistor, is configured to be controllable, for example, V _1/2 for the gate electrode and −V _{1 for the} well.
The potential difference between the gate and the well was controlled to V ₁ by applying the voltage of / 2 respectively. However, when the potential of the well is fixed at 0 V, of course, the voltage of V ₁ is applied to the gate electrode. To do.

[0074]

According to the present invention, in a ferroelectric memory, it is possible to rewrite and read at least ternary information in one memory cell transistor with a relatively simple circuit configuration. Therefore, the device can be miniaturized and the storage capacity can be increased.

[Brief description of drawings]

FIG. 1 is a plan view of an essential part of a ferroelectric memory according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

3 is a sectional view taken along line III-III in FIG.

4 is a sectional view taken along line IV-IV in FIG.

FIG. 5 is an equivalent circuit diagram of FIG.

FIG. 6 is a graph showing a hysteresis characteristic of a ferroelectric memory cell.

FIG. 7 is a graph showing a threshold voltage characteristic of a ferroelectric memory cell.

FIG. 8 is a circuit block diagram of a ferroelectric memory according to an embodiment of the present invention.

FIG. 9 is a flowchart of a method of rewriting a ferroelectric memory according to an embodiment of the present invention.

FIG. 10 is a circuit diagram showing in detail the sense amplifier circuit of FIG.

FIG. 11 is a conceptual diagram showing the relationship between the threshold voltage of a memory cell and the output of a sense amplifier circuit.

[Explanation of symbols]

MC _{1 to} MC ₄ memory cell WL ₁ , WL ₂ word line BL ₁ , BL ₂ bit line SL source line BUL ₁ , BUL ₂ well line BC _{1 to} BC ₄ bit contact SC ₁ , SC ₂ source contact 21 to 24 drain 25 , 26 source 31 silicon substrate 32 PZT film MARY memory cell array AD address input terminal CNT ₀ control input terminal DIO data input / output terminal ADBF address buffer AX output signal RDEC column decoder CDEC row decoder BUDEC well line selection circuit MPX multiplexer PY multiplexer selection signal DB data line CCNT chip control circuit PDQ, RD and CNT ₁ control signal SAMP sense amplifier circuit DOBF data output buffer SLCNT source line voltage control circuit BUCNT well potential control circuit WCN Light state control circuit DPRG input data / output data comparator circuit DAT output PVCNT positive high voltage generator / control circuit NVCNT negative high voltage generator / control circuit V _P, V _N signal DIBF data input buffer DIN output signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/8247 29/788 29/792

Claims (5)

[Claims] 1. A memory cell comprising a field effect transistor having a gate insulating film including a ferroelectric film, a first voltage between the gate electrode of the field effect transistor and a substrate portion, and the first voltage. A second voltage having a polarity opposite to that of the first voltage and a voltage applying means for applying a third voltage having a magnitude different from that of the first voltage within a range in which the ferroelectric film is not in a saturated polarization state; A ferroelectric memory comprising: a detection unit that detects a difference in polarization state of a body film as a difference in threshold voltage of the field effect transistor. 2. The first voltage and the second voltage are:
2. The ferroelectric memory according to claim 1, wherein the voltage is a voltage that brings each of the ferroelectric films into a saturated polarization state. 3. The voltage applying means applies a fourth voltage having a polarity opposite to that of the third voltage between the gate electrode and the substrate portion. Ferroelectric memory. 4. The third voltage according to claim 1, wherein the third voltage is a voltage that makes the ferroelectric film substantially in a non-polarized state after the voltage is removed. Ferroelectric memory. 5. The fifth voltage applying means has a fifth voltage having an intermediate magnitude between the first voltage and the third voltage and a sixth voltage having a polarity opposite to that of the fifth voltage. The ferroelectric memory according to claim 1, wherein the ferroelectric memory is applied between the gate electrode and the substrate portion, respectively.