CN117650175A - Vertical GaN HEMT semiconductor device and manufacturing method thereof - Google Patents
Vertical GaN HEMT semiconductor device and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a vertical GaN HEMT semiconductor device and a manufacturing method thereof, wherein the device comprises a laminated structure and a surface drift layer which are epitaxially grown on a substrate, the laminated structure comprises an inner drift layer, a uniform current layer and an inner resistance layer arranged between the inner drift layer and the uniform current layer; a deep groove with a non-flat side wall is formed on the substrate, the drift layer and the laminated structure penetrate through the surface, and the inner blocking layer is provided with a protruding part protruding inwards from the side wall of the deep groove; the conductivity type of the protruding portion is modified; the surface blocking layer is continuously formed on the surface drift layer and on the non-flat side wall of the deep trench; the first gate structure is disposed in the deep trench. The invention has the effects of establishing a longitudinal channel in a GaN device and effectively cutting off the channel under the condition of device miniaturization. In a preferred example, a second gate structure is disposed on the surface blocking layer, between the first gate structure and the source structure.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a vertical GaN HEMT semiconductor device and a manufacturing method thereof, and the vertical GaN HEMT semiconductor device is particularly applied to the new energy industry.
Background
A GaN HEMT semiconductor device is a semiconductor device prepared with GaN (gallium nitride) as a substrate, and one specific application is a high-power semiconductor device. HEMTs are short for high electron mobility transistors (High Electron Mobility Transistors), which are wide bandgap power semiconductor devices that have higher electron mobility, saturated electron velocity, and breakdown field resistance than silicon-based and silicon-carbide-based devices in high frequency power applications. Early GaN HEMT semiconductor devices were of lateral channel structure, and the Current Blocking Layer (CBL) in the device did not need to be patterned, and the occupied chip area was large, which was not beneficial to the miniaturization of chip products. Vertical-like or vertical channel-like structures have been proposed, but Current Blocking Layers (CBL) require patterning for the passage of carrier flow, resulting in excessive manufacturing costs. The current known current barrier layer patterning technology with channel patterns has two preparation methods, one is an epitaxial patterning procedure in the epitaxial stage process, and the channel patterns of the current barrier layer are formed by patterning in the epitaxial process, so that the cost of raw materials is greatly increased and the materials have no universality; the other is a post patterning process after the epitaxy stage, which is to form a channel pattern of the current blocking layer by patterning ion implantation, and the post patterning process cannot prepare to control the concentration and position of the doping ions in the current blocking layer.
The invention patent publication number CN106449727a discloses an avalanche-proof quasi-vertical HEMT, the semiconductor device comprising: a semiconductor body with a first device region of a first conductivity type (corresponding to a channel pattern in a current blocking layer) and a drift current control region of a second conductivity type (corresponding to a patterned current blocking layer), the drift current control region being separated from a second lateral surface by the drift region. The second device region, which is located at an upper layer, includes a blocking layer (corresponding to a plane blocking layer) and a buffer layer (corresponding to a plane drift layer), which has a band gap different from that of the blocking layer, such that a two-dimensional charge carrier gas channel (lateral carrier gas channel) occurs along an interface between the buffer layer and the blocking layer. A substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. The gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region (corresponding to a patterned current blocking layer) is configured to block vertical current in the drift region via a space charge region. In the related art, the gate structure is a planar gate structure, and the drift region of the first conductivity type (corresponding to the channel pattern in the current blocking layer) between the drift current control regions of the adjacent second conductivity type is not provided with a vertical carrier gas channel, so that the structure can only form a quasi-vertical GaN HEMT device. The related prior art does not disclose a specific semiconductor manufacturing process, and a person skilled in the art can only infer from the pattern of the drift current control region of the second conductivity type in combination with the integral connection structure of the drift region of the first conductivity type and the drift layer, the patterning method of the drift current control region of the second conductivity type doped with P-type is patterned ion implantation, the photolithography process required by the patterning mask is unavoidable, and as proved by the nucleation layer on the underlying first device region, the epitaxial growth implementation sequence of the second device region is implemented after the patterning process of the drift current control region (corresponding to the patterned current blocking layer), so that the photolithography process is implemented in the multi-layer epitaxial growth, and it can be inferred based on the arrangement of the nucleation layer in the architecture that there is a secondary epitaxial growth after ion implantation, so that implementation is difficult and will also result in that the epitaxial wafer has no versatility.
The invention patent publication No. CN113611731A discloses a GaN-based enhanced vertical HEMT device and a preparation method thereof, wherein the structure of the GaN-based enhanced vertical HEMT device sequentially comprises a drain electrode, a substrate, a drift region, a vertical channel blocking layer, a channel layer, a barrier layer, an interlayer film, a trench gate and a source electrode from bottom to top. GaN channel layer (corresponding to surface drift layer) and AlGaN barrier layer (corresponding to surface barrier layer) on top of GaN channel layer and AlxGa below GaN channel layer 1-x The N vertical channel barrier forms a double heterojunction structure in the vertical channel direction through the GaN/AlGaN heterostructureAnd forming a barrier layer, so that the transport of carriers in the vertical direction is blocked under the off-state condition, and then the channel is turned off, and the enhancement characteristic is realized. The structure is used for effectively avoiding negative effects caused by the traditional Mg-doped P-GaN barrier layer. However, the devices of the related art have a risk of being impractical. This is because the carrier gas channel of the GaN device is formed on one side (corresponding to the lateral carrier gas channel) of the face drift layer (GaN) close to the face barrier layer (AlGaN), and the vertical channel barrier layer (corresponding to the internal barrier layer) and the trench gate dielectric are respectively formed on both sides and bottom portions of the embedded gate metal under the face drift layer, and under this barrier, the longitudinal carrier flow channel and the longitudinal carrier gas channel for conducting the source and the drain cannot be established on both sides of the gate metal, which belongs to the unfinished invention.
The invention patent publication No. CN105845724A discloses an accumulation type vertical HEMT device, in a forward conduction state, a high-concentration electron accumulation layer (equivalent to a longitudinal carrier gas channel) is formed at the side wall of an insulated gate structure, and the on-resistance of the device is reduced, so that the device has good forward current driving capability; in the reverse blocking state, the insulated gate structure (embedded gate) can effectively improve the electric field concentration effect at the interface of the device barrier layer (equivalent to the inner barrier layer) and the buffer layer, and simultaneously, a new electric field peak is introduced at the tail end of the insulated gate structure so as to ensure that the electric field distribution of the device is uniform. Based on this related art, it is known by those skilled in the art that the lateral carrier gas channel is formed on the side of the channel layer (corresponding to the planar drift layer) close to the barrier layer (corresponding to the planar barrier layer), and that the two sides of the insulated gate structure (embedded gate) cannot practically establish a vertical carrier gas channel that can be cut off, which does not significantly contribute to the size miniaturization of the chip structure. In addition, the built-in multi-layer up and down separated current blocking layer (corresponding to the inner blocking layer) is obviously a patterned structure to form longitudinal channels extending down on both sides of the gate, but there is no disclosure nor any technical suggestion to teach whether there are any longitudinal carrier gas channels that can be cut off. In addition, the related art only discloses a device architecture, and does not disclose a manufacturing method of the device architecture, and a person skilled in the art can only infer a possible manufacturing method from the related art, so that the current blocking layer patterning technology of the channel pattern is either an epitaxial patterning process during an epitaxial stage or a post patterning process after the epitaxial stage, which will generate any one of a first problem that the cost of the raw material is greatly increased and the material has no versatility and a second problem that the concentration and the position of the doped ions in the current blocking layer cannot be prepared to be controlled.
Disclosure of Invention
The main purpose of the present invention is to provide a vertical GaN HEMT semiconductor device, which is mainly advanced in that a vertical channel of the vertical GaN HEMT semiconductor device can be established without a patterning ion implantation process, and in particular, a vertical carrier gas channel can be provided, so that the development of miniaturization of the chip surface size can not cause improper shortening of the channel length, thereby avoiding the problems of increased cost, lack of material sharing, or unstable chip functions caused by post-patterning in a pre-patterning process due to the need of manufacturing a channel pattern of a patterned current blocking layer of the vertical GaN HEMT.
The second main object of the present invention is to provide a semiconductor chip apparatus, which includes a vertical GaN HEMT semiconductor device, and which is compatible with the trend of device miniaturization caused by GaN-based vertical channels and is convenient for manufacturing the vertical GaN HEMT semiconductor device, so that it is not necessary to pattern a current blocking layer to make a channel pattern.
The third main object of the present invention is to provide a method for manufacturing a vertical GaN HEMT semiconductor device, which is used to realize the material sharing of epitaxial patterns in the manufacture of the vertical GaN HEMT semiconductor device, and avoid the manufacture of channel patterns of patterned current blocking layers on GaN-based substrates, i.e. omit the patterning lithography process of forming the channel patterns.
The main purpose of the invention is realized by the following technical scheme:
a vertical GaN HEMT semiconductor device is provided, comprising:
a stacked structure epitaxially grown on a substrate and a surface drift layer on the stacked structure, wherein the stacked structure comprises an inner drift layer, a uniform current layer and an inner resistance layer arranged therebetween; a deep trench with a non-flat side wall is etched on the surface drift layer and the laminated structure, the deep trench penetrates through the surface drift layer and the laminated structure, and the inner barrier layer is provided with a protruding part protruding inwards on the side wall of the deep trench; the conductivity type of the protruding portion of the inner barrier layer is modified;
a surface blocking layer continuously formed on the surface drift layer and on the non-planar sidewalls of the deep trenches;
a first gate structure disposed in the deep trench;
a source electrode structure arranged on the surface drift layer and positioned at two sides of the first gate electrode structure;
and the drain electrode structure is arranged at the bottom of the device opposite to the epitaxial growth direction of the laminated structure.
By adopting the technical scheme, the inner blocking layer is provided with the protruding part protruding inwards from the side wall of the deep groove; the conductivity type of the protruding part of the inner barrier layer is modified, and a longitudinal passage can be established at two sides of the first grid structure; and combining the surface barrier layer to continuously extend into the non-flat side wall of the deep groove, establishing intermittent and truncatable longitudinal carrier gas channels positioned at the end sides of the inner drift layer in the longitudinal passages at the two sides of the first grid structure, and simultaneously reducing the length of the carrier gas channels without synchronously reducing the chip area size and manufacturing a channel pattern of the inner barrier layer.
The present invention in a preferred example may be further configured to: the inner drift layer and the surface drift layer are over etched to enable the non-flat side wall of the deep groove to have an S-shaped cross section.
By adopting the preferable technical characteristics, the non-flat side wall of the deep groove has an S-shaped cross section, so that the conductivity type of the protruding part of the inner barrier layer is easier to be modified.
The present invention in a preferred example may be further configured to: the device further includes a gate dielectric layer formed on an outer surface of the face barrier layer.
By adopting the preferable technical characteristics, the first gate structure and the surface barrier layer are isolated by the gate dielectric layer, so that silicon element of the first gate structure is prevented from diffusing into crystal lattices of the surface barrier layer.
The present invention in a preferred example may be further configured to: the inner blocking layer conducts the inner drift layer and the current equalizing layer only at the protruding portion.
By adopting the above preferable technical characteristics, only the longitudinal conduction position of the inner blocking layer is used as the protruding part, and the inner blocking layer can block the longitudinal movement of carriers beyond the two sides of the first gate structure in a large area, so that the longitudinal conduction passage from the surface drift layer to the substrate is controlled to be on the two sides of the first gate structure.
The present invention in a preferred example may be further configured to: the inner resistance layer is of a multi-layer structure and is also formed between the face drift layer and the current equalizing layer and between the inner drift layer and an epitaxial bottom layer below the inner drift layer.
By adopting the preferable technical characteristics, the inner blocking layer of the multilayer structure is utilized, except the protruding part, the inner blocking layer isolates abnormal conduction between the surface drift layer and the current equalizing layer, and the characteristic of vertical breakdown prevention is improved, so that the longitudinal current blocking effect is better exerted.
The present invention in a preferred example may be further configured to: the surface drift layer is provided with a lateral carrier gas channel which can be interrupted at one side close to the surface blocking layer, the inner drift layer is provided with a longitudinal carrier gas channel which can be interrupted at the side edge close to the side wall of the deep groove, the longitudinal carrier gas channel is positioned in the matrix circuit based on the connection of the uniform flow layer, and the lateral carrier gas channel is positioned at one side of the matrix circuit.
By adopting the preferable technical characteristics, the combination of the transverse carrier gas channel and the longitudinal carrier gas channel is utilized to reduce the occupied area of the total channel length on the surface of the device, thereby being beneficial to the miniaturization of the chip size; and based on the connection of the current equalizing layer to the longitudinal carrier gas channels, a matrix circuit is formed between the source electrode and the drain electrode in the on-state of the transistor, the longitudinal carrier gas channels are positioned in the matrix circuit, the transverse carrier gas channels are positioned on one side of the matrix circuit, the effect of uniform carrier distribution is better exerted, a plurality of longitudinal carrier gas channels have the mutual protection integrity, and the individual longitudinal carrier gas channels are not easy to burn.
The present invention in a preferred example may be further configured to: the device further includes a second gate structure disposed on the face barrier layer and between the first gate structure and the source structure; preferably, a shallow trench that does not penetrate through the surface drift layer is formed from the upper surface of the surface drift layer, so that the bottom surface of the second gate structure is non-planar and the lateral carrier gas channel is discontinuous.
By adopting the above preferable technical characteristics, the transverse carrier gas channel is multi-section and can be cut off in the closing stage of the transistor by utilizing the arrangement of the second grid structure; in a more preferable feature, the shallow trench is used to fix the second gate structure well in a non-planar manner, the lateral carrier gas channel is a cut-off section, and a plurality of sub-conducting sections and sub-cut-off sections between the sub-conducting sections can be thinned, so that the lateral carrier gas channel is discontinuous, and a better cut-off effect is achieved.
The main purpose of the invention is realized by the following technical scheme: a semiconductor chip device is provided that includes a vertical GaN HEMT semiconductor device with a combination of features as previously described.
The main purpose of the invention is realized by the following technical scheme:
a method for manufacturing a vertical GaN HEMT semiconductor device is provided, comprising:
step S1, providing a substrate, wherein a laminated structure and a surface drift layer on the laminated structure are epitaxially grown on the substrate, and the laminated structure comprises an inner drift layer, a uniform flow layer and an inner resistance layer arranged therebetween;
step S2, etching the surface drift layer and the laminated structure to form a deep trench with a non-flat side wall on the substrate, wherein the deep trench penetrates through the surface drift layer and the laminated structure, and the inner barrier layer is provided with a protruding part protruding inwards at the side wall of the deep trench;
s3, modifying the protruding part of the inner barrier layer;
s4, continuously forming a surface blocking layer on the surface drift layer and on the non-flat side wall of the deep trench;
step S5, setting a first grid structure in the deep trench;
step S6, arranging source electrode structures on the surface drift layer, wherein the source electrode structures are positioned on two sides of the first grid electrode structure;
step S7, setting a drain electrode structure as the bottom of the device in the direction opposite to the epitaxial growth direction of the laminated structure; specifically, a drain structure may be disposed on the back side of the substrate.
By adopting the technical scheme of the method, the GaN HEMT semiconductor device with the transverse carrier gas channel and the longitudinal carrier gas channel can be manufactured.
The present invention in a preferred example may be further configured to:
in step S1, the stacked structure and the surface drift layer are a non-pattern blank film layer epitaxially grown on the substrate in a full coverage manner;
step S2, etching the deep groove selectively to enable the inner drift layer and the surface drift layer to be excessively etched, so that the non-flat side wall of the deep groove has an S-shaped cross section;
step S3 comprises oblique ion implantation, wherein the implantation mask layer is used along with the etching mask layer used in step S2 so as to change the conductivity type of the protruding part of the inner blocking layer to be consistent with that of the current sharing layer;
preferably, after step S1 and before step S4, the method further comprises: step S31, forming shallow trenches in the surface drift layer, wherein the shallow trenches do not penetrate through the surface drift layer, so that the bottom surface of the second gate structure arranged in the step S5 is non-flat, and the transverse carrier gas channel is discontinuous;
after forming the surface blocking layer in step S4, the method further comprises: step S41, forming a gate dielectric layer on the outer surface of the surface barrier layer;
Step S5 further includes disposing a second gate structure on the surface blocking layer, where the second gate structure is located between the first gate structure and the source structure; in step S5, the first gate structure and the second gate structure are conductive polysilicon;
in step S6, the source electrode structure is conductive polysilicon; after step S6, the method further comprises: step S61, forming an interlayer film on the surface blocking layer, wherein the interlayer film substantially covers the first gate structure of the device region, and the interlayer film does not cover the upper end surface of the source structure; step S62, disposing a source metal on the interlayer film.
In summary, the present invention includes at least one of the following technical effects contributing to the prior art:
1. the difficulty that the patterning current blocking layer is required to be manufactured in the conventional vertical GaN HEMT semiconductor device is eliminated, and the technical defect that an epitaxial wafer cannot be shared or/and the process stability is poor due to the existence of the patterning current blocking layer is overcome;
2. the additional function of the grid electrode groove is added, so that the patterning procedure of the current blocking layer can be avoided;
3. under the same channel length specification, the occupation area on the surface of the chip can be reduced based on the longitudinal carrier gas channel;
4. And the impedance of the transistor can be adjusted in a partitioning manner based on the second grid structure, so that the GaN HEMT semiconductor device has better product stability.
Drawings
Fig. 1 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device according to some embodiments of the invention;
fig. 2 is a flow chart of a method for manufacturing a vertical GaN HEMT semiconductor device according to some preferred embodiments of the invention;
FIG. 3 is a schematic cross-sectional view of the assembly corresponding to the step S1 of FIG. 2 according to some preferred embodiments of the present invention;
FIG. 4 is a schematic cross-sectional view of the assembly corresponding to step S2 of FIG. 2 according to some preferred embodiments of the present invention;
FIG. 5 is a schematic cross-sectional view of the assembly corresponding to step S3 of FIG. 2 according to some preferred embodiments of the present invention;
FIG. 6 is a schematic cross-sectional view of the assembly corresponding to step S4 of FIG. 2 according to some preferred embodiments of the present invention;
FIG. 7 is a schematic cross-sectional view of the assembly corresponding to step S5 of FIG. 2 according to some preferred embodiments of the present invention;
FIG. 8 is a schematic cross-sectional view of the assembly corresponding to step S6 of FIG. 2 according to some preferred embodiments of the present invention;
FIG. 9 is a schematic cross-sectional view of the assembly corresponding to step S7 of FIG. 2 according to some preferred embodiments of the present invention;
fig. 10 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device according to some embodiments of the invention in a gate operation state;
Fig. 11 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device according to another preferred embodiment of the invention;
fig. 12 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device according to another preferred embodiment of the invention in a gate operation state;
fig. 13 is a schematic cross-sectional view illustrating shallow trenches formed in the fabrication of a vertical GaN HEMT semiconductor device according to other preferred embodiments of the invention.
Reference numerals: 10. a substrate; 101. a transfer support plate; 11. deep trenches; 20. a laminated structure; 21. an inner drift layer; 21a, longitudinal carrier gas channel; 22. a uniform flow layer; 23. an inner barrier layer; 23a, protruding parts; 24. an epitaxial bottom layer; 25. an isolation junction; 30. a surface drift layer; 30a, a lateral carrier gas channel; 31. a shallow trench; 40. a surface blocking layer; 50. a first gate structure; 51. a gate dielectric layer; 60. a source electrode structure; 61. a source metal; 70. a drain structure; 80. a second gate structure; 90. an interlayer film; 110. and a hard mask layer.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only examples for understanding a part of the inventive concept of the present invention, and are not representative of all embodiments, nor are they to be construed as the only embodiments. All other embodiments, based on the embodiments of the present invention, which are obtained by those of ordinary skill in the art under the understanding of the inventive concept of the present invention, are within the scope of the present invention.
It should be noted that, if a directional indication (such as up, down, left, right, front, and rear … …) is involved in the embodiment of the present invention, the directional indication is merely used to explain the relative positional relationship, movement condition, etc. between the components in a specific posture, and if the specific posture is changed, the directional indication is correspondingly changed. In order to facilitate understanding of the technical scheme of the present invention, the vertical GaN HEMT semiconductor device and the manufacturing method thereof of the present invention are described and explained in further detail below, but are not intended to limit the scope of protection of the present invention.
Fig. 1 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device according to some preferred embodiments of the invention. The drawings show only those parts that are common to many embodiments, and that differ or otherwise differ in what is depicted in the figures or otherwise presented in a written manner. Thus, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and determine whether individual features or any combination of several features described below can be characterized in the same embodiment or whether features mutually exclusive in technical essence can be characterized only in different variant embodiments. Embodiments in which the figures are too similar are not repeated.
Referring to fig. 1, some embodiments of the present invention disclose a vertical GaN HEMT semiconductor device, which includes a substrate 10 for providing a drain electrode and having a stacked structure 20 and a surface drift layer 30 provided thereon, a surface blocking layer 40 on the substrate 10 for isolating a gate electrode from a source electrode, a first gate structure 50 penetrating the surface drift layer 30 and embedded in the stacked structure 20, a source structure 60 provided on the surface drift layer 30, and a drain structure 70 provided on a back surface of the substrate 10. The substrate 10, the stacked structure 20, the surface drift layer 30 and the surface blocking layer 40 are all made of semiconductor single crystal materials, and the base material may be, but not limited to, gaN (gallium nitride), or a group iv semiconductor, a group iii-v semiconductor or a group ii-vi semiconductor with the same function, for example, siC is also another base material, and each layer may be doped with a chemical element as needed to adapt the electrical characteristics thereof. In the aforementioned semiconductor structure, carriers can conduct the source structure 60 and the drain structure 70. The surface barrier layer 40 may also be referred to as a surface barrier layer, a surface barrier layer. Based on the influence of the surface blocking layer 40 on the surface drift layer 30, a carrier flow path is relatively easy to form on the surface of the surface drift layer 30, for example, the surface drift layer 30 is made of intrinsic GaN and is electrically biased to N-type, the surface blocking layer 40 is made of AlGaN and is electrically P-type, and the surface of the surface drift layer 30 abutting against the surface blocking layer 40 is increased to N-type. The carrier flow path includes a transverse carrier gas channel 30a and a longitudinal carrier gas channel 21a as shown in fig. 1. Based on the electric field effect of the first gate structure 50, the transverse carrier gas channel 30a and the longitudinal carrier gas channel 21a can be turned off by the first gate structure 50, see fig. 1 and 10. In the example, the carriers are electrons, and when the first gate structure 50 is in a negative electric field, the surface drift layer 30 adjacent to the first gate structure 50 is turned to positive, and the N-type increasing characteristic of the surface drift layer 30 is eliminated by the gate electric field, so that the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a are in an off state (as compared with the variation between fig. 1 and fig. 10).
The stacked structure 20 and the surface drift layer 30 on the stacked structure 20 are sequentially epitaxially grown on the substrate 10, the substrate 10 is a semiconductor single crystal structure, and the stacked structure 20 and the surface drift layer 30 are also semiconductor single crystal structures based on a semiconductor epitaxial growth process. In this example, the substrate 10 is made of an n+ type GaN material, the surface drift layer 30 is made of a GaN material or an N-type semiconductor material, and the base material of the stacked structure 20 is GaN. The stacked structure 20 includes an inner drift layer 21, a current equalizing layer 22, and an inner blocking layer 23 interposed therebetween, wherein the number of layers of the inner blocking layer 23 is more than two, and the layers are mainly used for separating the surface drift layer 30 from the inner drift layer 21 and for separating the inner drift layer 21 from a conductive layer (such as a substrate 10 or an epitaxial bottom layer 24) at the bottom of the device; the material of the inner drift layer 21 is specifically GaN material or N-type semiconductor material, the material of the current equalizing layer 22 is specifically n+ type GaN material, and the material of the inner drift layer 23 is specifically P-type GaN material, specifically AlGaN. More specifically, the bottom layer of the stacked structure 20 is an epitaxial bottom layer 24, and as a bottom drift layer, the material of the epitaxial bottom layer 24 is specifically an N-type GaN material, the epitaxial bottom layer 24 has a lower doping concentration than the current equalizing layer 22, and the doping component may be silicon, germanium or other N-type materials.
Further, a deep trench 11 with a non-flat sidewall is etched on the substrate 10 to the surface drift layer 30 and the stacked structure 20, the deep trench 11 penetrates through the surface drift layer 30 and the stacked structure 20, and may specifically end up in the epitaxial underlayer 24, and the inner barrier layer 23 has a protruding portion 23a protruding inwards from the sidewall of the deep trench 11; the protruding portion 23a protrudes from both the same side edge of the inner drift layer 21 and the same side edge of the current equalizing layer 22, and the conductivity type of the protruding portion 23a of the inner resistance layer 23 is modified so that the conductivity type of the protruding portion 23a is the same as that of the inner drift layer 21 or the current equalizing layer 22. Based on the protruding portion 23a, the side wall of the deep trench 11 is a non-flat straight side wall, and the deep trench 11 is a multi-loop structure. Furthermore, in the semiconductor device operating region (i.e., the main region excluding the external contact bonding region), there is no need to provide a doping well other than the region of the deep trench 11. In an example, the epitaxial bottom layer 24 is formed with an isolation junction 25 below the deep trench 11, and a well region of the isolation junction 25 is defined by a notch shape of the deep trench 11, without an additional photolithography developing step. The conductivity type of the isolation junction 25 is opposite to that of the epitaxial bottom layer 24, for example, the isolation junction 25 is P-type, the doping component may be a group iii or group ii chemical element, the PN-type is unidirectional non-conductive, and the PNP-type or NPN-type is bidirectional non-conductive. The doping components described above, except for the spacer 25, may be formed in situ during epitaxial growth.
The surface blocking layer 40 is continuously formed on the surface drift layer 30 and on the non-planar sidewalls of the deep trenches 11. The surface blocking layer 40 may be specifically prepared by using a secondary epitaxy process after the deep trench 11 is etched, and in an example, the material of the surface blocking layer 40 is specifically P-type GaN material, specifically AlGaN. The surface blocking layer 40 has a band gap different from that of the surface drift layer 30, so that a lateral carrier gas channel 30a and a longitudinal carrier gas channel 21a are present near the interface of the surface drift layer 30 and the surface drift layer, and the longitudinal carrier gas channel 21a is also formed at the side edge of the inner drift layer 21. And the first gate structure 50 is disposed in the deep trench 11 for turning off the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a. The first gate structure 50 is typically made of heavily doped conductive polysilicon, but may be made of other conductive materials. In addition, before the first gate structure 50 is disposed, a gate dielectric layer 51 may be formed on the surface of the surface blocking layer 40, and the gate dielectric layer 51 is made of a dielectric insulating material of metal nitride or metal oxide, the gate dielectric layer 51 isolates the surface blocking layer 40 from the first gate structure 50, the thicknesses of the gate dielectric layer 51 and the surface blocking layer 40 are sufficiently thin, and the electric potential of the first gate structure 50 can affect the surface conductivity types of the surface drift layer 30 and the inner drift layer 21 so as to turn off the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a.
The source structure 60 is disposed on the surface drift layer 30 and located at both sides of the first gate structure 50. The source structure 60 is electrically connected to the surface drift layer 30, and the source structure 60 may be made of conductive polysilicon, copper, aluminum, titanium or other suitable alloy, and a barrier layer (not shown) may be formed at the contact interface between the source structure 60 and the surface drift layer 30 in order to prevent diffusion of the source structure 60 component into the surface drift layer.
The drain structure 70 is disposed at the bottom of the device opposite the epitaxial growth direction of the stacked structure 20. Specifically, the drain structure 70 is disposed on the back side of the substrate 10. In various examples, the substrate 10 may be peeled off or removed, the drain structure 70 may be directly disposed on the lower surface of the stacked structure 20, or the drain structure 70 may be disposed on the bottom surface of a transfer carrier plate 101 (as shown in fig. 11 and 12) that is attached after the semiconductor process, and the transfer carrier plate may be made of any conductive material, and should perform an interfacial buffering function and a longitudinal electrical conduction function for bonding the stacked structure 20 and the drain structure 70, but is not limited to the semiconductor material.
In the present embodiment of the basic structure, with the inner barrier layer 23 having the protruding portion 23a protruding inwardly from the sidewall of the deep trench 11, the conductivity type of the protruding portion 23a of the inner barrier layer 23 can be modified without an additional photolithography developing process, and a longitudinal via can be established at both sides of the first gate structure 50; in combination with the continuous extension of the surface blocking layer 40 into the non-planar side walls of the deep trench 11, intermittent and truncatable longitudinal carrier gas channels 21a are established in the longitudinal passages on both sides of the first gate structure 50 on the end sides of the inner drift layer 21, so that the length of the carrier gas channels is not reduced simultaneously while the chip area size is miniaturized, and the channel pattern of the inner blocking layer 23 is not required.
In a preferred example, regarding the sidewall shape of the deep trench 11, the inner drift layer 21 and the surface drift layer 30 can be excessively etched laterally in an isotropic selective etching manner, so that the non-flat sidewall of the deep trench 11 has an S-shaped wavy cross-sectional shape. With this S-shaped cross-sectional shape, the conductivity type of the convex portion 23a of the inner barrier layer 23 is made easier to be modified.
In a preferred example, regarding the internal structure of the stacked structure 20, the inner barrier layer 23 conducts the inner drift layer 21 and the current equalizing layer 22 only at the protruding portion 23 a. With the only conduction portion in the longitudinal direction of the inner barrier layer 23 being the protruding portion 23a, the inner barrier layer 23 can block the carrier from moving in the longitudinal direction beyond the two sides of the first gate structure 50 in a large area, which is beneficial to control the longitudinal conduction path from the surface drift layer 30 to the substrate 10 to the two sides of the first gate structure 50.
In a preferred example, regarding the specific structure of the inner barrier layer 23, the inner barrier layer 23 is a multi-layered structure, and is further formed between the face drift layer 30 and the current equalizing layer 22 and between the inner drift layer 21 and the epitaxial underlayer 24 located under the inner drift layer 21. With the inner barrier layer 23 of a multilayer structure, except for the convex portion 23a, the inner barrier layer 23 isolates abnormal conduction between the face drift layer 30 and the current equalizing layer 22, and improves the characteristic of preventing vertical breakdown to better exert a longitudinal current blocking effect.
In a preferred example, with respect to the specific structure of the first gate structure 50, the device further includes a gate dielectric layer 51 that may be formed on the outer surface of the face barrier layer 40. The first gate structure 50 is isolated from the surface blocking layer 40 by the gate dielectric layer 51, and diffusion of silicon element of the first gate structure 50 into the lattice of the surface blocking layer 40 is avoided. The first gate structure 50 may be prominently higher than the gate dielectric layer 51 to increase the off-length of the channel; in a different example, the first gate structure 50 may also be flush with the gate dielectric layer 51 to reduce the thickness of the interlayer film 90. In a further specific example, the interlayer film 90 is electrically insulating and covers the gate dielectric layer 51 or the surface blocking layer 40. The interlayer film 90 is in the same layer structure as the source structure 60 to protect the source structure 60. A layer of source metal 61 may be formed on the interlayer film 90 to connect the source structure 60.
As can be seen, the lateral carrier gas channel 30a is formed on the surface drift layer 30 near the surface blocking layer 40, and the vertical carrier gas channel 21a is formed on the inner drift layer 21 near the side edge of the side wall of the deep trench 11, which is an N-type channel in this example. Based on the connection of the current equalizing layer 22, the longitudinal carrier gas channel 21a is located in a matrix circuit, and the transverse carrier gas channel 30a is located at one side of the matrix circuit. The combination of the transverse carrier gas channel 30a and the longitudinal carrier gas channel 21a is utilized to reduce the occupied area of the total channel length on the surface of the device, thereby being beneficial to the miniaturization of the chip size; and based on the connection of the current equalizing layer 22 to the vertical carrier gas channels 21a, a matrix circuit is formed between the source structure 60 and the drain structure 70 in the on-state of the transistor, the vertical carrier gas channels 21a are located in the matrix circuit, the horizontal carrier gas channels 30a are located at one side of the matrix circuit, the effect of uniform carrier distribution is better exerted, a plurality of the vertical carrier gas channels 21a have mutual protection integrity, and the individual vertical carrier gas channels 21a are not easy to burn.
Referring to fig. 2 in conjunction with fig. 3 to 10, some embodiments of the present invention further disclose a vertical GaN HEMT semiconductor device, including steps S1 to S7 as follows.
Step S1 may be performed by referring to fig. 3, providing a substrate 10, and epitaxially growing a stacked structure 20 and a surface drift layer 30 on the stacked structure 20 on the substrate 10, where the stacked structure 20 includes an inner drift layer 21, a current equalizing layer 22, and an inner blocking layer 23 interposed therebetween. In step S1, the substrate 10 is in a wafer state. In this example, the epitaxial growth sequence of the stacked structure 20 is that of the epitaxial bottom layer 24, the internal barrier layer 23, the internal drift layer 21, the internal barrier layer 23, the current equalizing layer 22, the internal barrier layer 23, and the surface drift layer 30 is epitaxially grown on the uppermost internal barrier layer 23. When the inner barrier layer 23 is of the first conductivity type, the inner drift layer 21 and the current equalizing layer 22 have the same second conductivity type, the inner barrier layer 23 of the first conductivity type is disposed between two adjacent layers of the second conductivity type, and the number of layers of the inner drift layer 21 and the current equalizing layer 22 is not limited to one layer and may be multiple layers. In a preferred example, in step S1, the stacked structure 20 and the surface drift layer 30 are non-patterned blank film layers epitaxially grown on the substrate 10 in a full-coverage manner, and may be used as a common wafer.
Step S2 may be performed by referring to fig. 4, etching the face drift layer 30 and the stacked structure 20 based on the post-lithography pattern of the hard mask layer 110 to form a deep trench 11 with a non-planar sidewall on the substrate 10, wherein the deep trench 11 penetrates the face drift layer 30 and the stacked structure 20, and the inner barrier layer 23 has a protruding portion 23a protruding inward from the sidewall of the deep trench 11. The specific substep is to etch longitudinally to a preset depth of the deep trench 11 with anisotropy, and then to use isotropic over-selective etching, wherein the etching gas used has a slower etching efficiency for the inner barrier layer 23 than other layers, so that the non-flat sidewall of the deep trench 11 has an S-shaped cross-section. The convex portion 23a of the inner barrier layer 23 can be formed.
Step S3 may be performed by referring to fig. 5, modifying the convex portions 23a of the inner barrier layer 23. The modification method is ion implantation, and a material component with a second conductivity type is injected into the convex part 23a of the inner barrier layer 23 with a first conductivity type in an oblique angle implantation direction, and the convex part 23a is converted into the second conductivity type so as to be consistent with the conductivity type of the inner drift layer 21 and the current sharing layer 22. In a preferred example, a material component having the first conductivity type is injected into the epitaxial underlayer 24 having the second conductivity type corresponding to the bottom of the deep trench 11 by using an anisotropic longitudinal ion implantation method under the shielding of the hard mask layer 110, so as to form an isolation junction 25. The hard mask layer 110 can be used as a pattern for forming the deep trench 11, as a modified shielding for the protruding portion 23a, and as a pattern for forming the isolation junction 25, so that only one photolithographic development of the hard mask layer 110 is required.
Step S4 may be performed by referring to fig. 6, continuously forming a surface blocking layer 40 on the surface drift layer 30 and on the non-planar sidewalls of the deep trench 11. The specific operation is that the hard mask layer 110 is removed, the deep trench 11 is cleaned, and the surface blocking layer 40 is epitaxially grown on the outer surface of the surface drift layer 30, and also epitaxially grown on the non-flat sidewall of the deep trench 11. The aforementioned isolation junction 25 relatively increases the well thickness of the first conductivity type of the surface blocking layer 40 below the bottom of the deep trench 11. In a preferred example, after forming the surface blocking layer 40 in step S4, the method further includes: in step S41, a gate dielectric layer 51 is formed on the outer surface of the surface blocking layer 40. One method of forming the gate dielectric layer 51 is a thin film deposition technique such as CVD or ALD.
Step S5 may be performed with reference to fig. 7, where the first gate structure 50 is disposed in the deep trench 11. The first gate structure 50 is provided by polysilicon filling.
Step S6 may refer to fig. 8, where a source structure 60 is disposed on the surface drift layer 30, and the source structure 60 is located at two sides of the first gate structure 50. The source structure 60 may be bonded to the surface drift layer 30 or directly to the surface blocking layer 40. When the source structure 60 is bonded to the surface drift layer 30, a well layer (not shown) of the first conductivity type may be preferably provided at the lowermost layer of the integrated layer including the epitaxial bottom layer 24 and the substrate 10, to form a unidirectional conduction protection measure. When the source structure 60 is bonded to the surface blocking layer 40, a unidirectional conduction protection is provided between the surface blocking layer 40 and the surface drift layer 30 at the bottom of the source structure 60. In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type; in a variation, the first conductivity type is N-type and the second conductivity type is P-type.
In a preferred example, the source structure 60 is conductive polysilicon in step S6; after step S6, the method further comprises: step S61 of forming an interlayer film 90 on the surface blocking layer 40, wherein the interlayer film 90 substantially covers the first gate structure 50 in the device region, and the interlayer film 90 does not cover the upper end surface of the source structure 60; step S62, disposing a source metal 61 on the interlayer film 90.
Step S7 may be performed by referring to fig. 9, where the drain structure 70 is provided as the bottom of the device, opposite to the epitaxial growth direction of the stacked structure 20. In a specific example, the drain structure 70 is disposed on the back side of the substrate 10.
Therefore, a GaN HEMT semiconductor device having both the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a can be manufactured based on the above-described manufacturing method.
Referring to fig. 11 and 12, a vertical GaN HEMT semiconductor device according to other embodiments of the present invention includes the main basic components as described above, and fig. 11 shows the on-state of the transistor of the semiconductor device, and fig. 12 shows the off-state of the transistor of the semiconductor device. In the preferred example, the device further includes a second gate structure 80 disposed on the surface blocking layer 40 and between the first gate structure 50 and the source structure 60; in a preferred example, a shallow trench 31 that does not penetrate the surface drift layer 30 is formed from the upper surface of the surface drift layer 30, so that the bottom surface of the second gate structure 80 is non-planar and the lateral carrier gas channel 30a is discontinuous. With the arrangement of the second gate structure 80, the lateral carrier gas channel 30a is multi-segmented during the transistor turn-off phase; in a more preferred feature, the shallow trench 31 is utilized to fix the second gate structure 80 well in a non-planar manner, and the lateral carrier gas channel 30a is a breakable segment, and a plurality of sub-conductive segments and sub-breaking segments between the sub-conductive segments can be subdivided, so that the lateral carrier gas channel 30a is discontinuous, and a better breaking effect is achieved. The manufacturing method of the vertical GaN HEMT semiconductor device includes main steps S1 to S7 as described in fig. 2 in the first embodiment.
Fig. 13 illustrates a method for manufacturing the shallow trench 31. In a preferred example, after the step S1 of providing the substrate 10 and before the step S4 of forming the surface blocking layer 40, further includes: in step S31, a shallow trench 31 is formed in the surface drift layer 30, and the shallow trench 31 does not penetrate through the surface drift layer 30, so that the bottom surface of the second gate structure 80 set in step S5 is non-planar, and the lateral carrier gas channel 30a is discontinuous, i.e., is not a continuous segment. The main difference between the deep trench 11 and the shallow trench 31 is that the deep trench 11 penetrates the surface drift layer 30 and the rest of the stacked structure 20 except the epitaxial underlayer 24, and the depth of the shallow trench 31 is not more than one half of the thickness of the surface drift layer 30.
In a preferred example, a second gate structure 80 is further disposed on the surface blocking layer 40 in step S5, the second gate structure 80 being located between the first gate structure 50 and the source structure 60; in step S5, the first gate structure 50 and the second gate structure 80 are conductive polysilicon. After the source structure 60 is disposed in step S6, the semiconductor device itself has sufficient supporting strength based on the presence of the source metal 61, the substrate 10 may be removed or the substrate 10 may be replaced with the interposer carrier plate 101, and then the drain structure 70 may be disposed on the interposer carrier plate 101 in step S7 (as shown in fig. 11 and 12).
The embodiments of the present invention are all preferred embodiments for easy understanding or implementation of the technical solution of the present invention, and are not limited in scope by the present invention, and all equivalent changes according to the structure, shape and principle of the present invention should be covered in the scope of the claimed invention.
Claims (14)
1. A vertical GaN HEMT semiconductor device comprising:
a stacked structure epitaxially grown on a substrate and a surface drift layer on the stacked structure, wherein the stacked structure comprises an inner drift layer, a uniform current layer and an inner resistance layer arranged therebetween; a deep trench with a non-flat side wall is etched on the surface drift layer and the laminated structure, the deep trench penetrates through the surface drift layer and the laminated structure, and the inner barrier layer is provided with a protruding part protruding inwards on the side wall of the deep trench; the conductivity type of the protruding portion of the inner barrier layer is modified;
a surface blocking layer continuously formed on the surface drift layer and on the non-planar sidewalls of the deep trenches;
a first gate structure disposed in the deep trench;
a source electrode structure arranged on the surface drift layer and positioned at two sides of the first gate electrode structure;
And the drain electrode structure is arranged at the bottom of the device opposite to the epitaxial growth direction of the laminated structure.
2. The vertical GaN HEMT semiconductor device of claim 1, wherein said inner drift layer and said face drift layer are over etched such that non-planar sidewalls of said deep trench have an S-shaped cross-sectional shape.
3. The vertical GaN HEMT semiconductor device of claim 1, further comprising a gate dielectric layer formed on an outer surface of said face barrier layer.
4. The vertical GaN HEMT semiconductor device of claim 1, wherein said inner barrier layer turns on said inner drift layer and said current-sharing layer only at said raised portions.
5. The vertical GaN HEMT semiconductor device of claim 4, wherein said inner resistance layer is a multilayer structure further formed between said face drift layer and said current sharing layer and between said inner drift layer and an epitaxial underlayer below said inner drift layer.
6. The vertical GaN HEMT semiconductor device of any one of claims 1-5, wherein said face drift layer is formed with a interruptible lateral carrier gas channel on a side near said face barrier layer, said inner drift layer is formed with an interruptible longitudinal carrier gas channel on a side edge near said deep trench sidewall, said longitudinal carrier gas channel being located in a matrix circuit and said lateral carrier gas channel being located on a side of said matrix circuit based on the connection of said uniform current layers.
7. The vertical GaN HEMT semiconductor device of claim 6, further comprising a second gate structure disposed on said plane blocking layer and between said first gate structure and said source structure; a shallow trench is formed from the upper surface of the face drift layer that does not penetrate the face drift layer so that the bottom surface of the second gate structure is non-planar and the lateral carrier gas channel is discontinuous.
8. A semiconductor chip device comprising a vertical GaN HEMT semiconductor device according to any one of claims 1-7.
9. A method of manufacturing a vertical GaN HEMT semiconductor device, comprising:
s1, providing a substrate, wherein a laminated structure and a surface drift layer on the laminated structure are epitaxially grown on the substrate, and the laminated structure comprises an inner drift layer, a uniform flow layer and an inner resistance layer arranged therebetween;
s2, etching the surface drift layer and the laminated structure to form a deep trench with a non-flat side wall on the substrate, wherein the deep trench penetrates through the surface drift layer and the laminated structure, and the inner barrier layer is provided with a protruding part protruding inwards at the side wall of the deep trench;
S3, modifying the protruding part of the inner barrier layer;
s4, continuously forming a surface blocking layer on the surface drift layer and on the non-flat side wall of the deep trench;
s5, setting a first grid structure in the deep trench;
s6, arranging a source electrode structure on the surface drift layer, wherein the source electrode structure is positioned on two sides of the first grid electrode structure;
and S7, setting a drain electrode structure as the bottom of the device in the direction opposite to the epitaxial growth direction of the laminated structure.
10. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 9, wherein:
in step S1, the stacked structure and the surface drift layer are a non-pattern blank film layer epitaxially grown on the substrate in a full coverage manner;
step S2, etching the deep groove selectively to enable the inner drift layer and the surface drift layer to be excessively etched, so that the non-flat side wall of the deep groove has an S-shaped cross section;
step S3 includes bevel ion implantation, and the implantation mask layer used in step S2 is followed by etching the mask layer to change the conductivity type of the protruding portion of the inner barrier layer to be consistent with the current equalizing layer.
11. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 9, wherein: after forming the surface blocking layer in step S4, the method further comprises: s41, forming a gate dielectric layer on the outer surface of the surface barrier layer.
12. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 9, wherein: step S5 further includes disposing a second gate structure on the surface blocking layer, where the second gate structure is located between the first gate structure and the source structure; in step S5, the first gate structure and the second gate structure are conductive polysilicon.
13. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 12, wherein: the method further comprises the following steps after the step S1 and before the step S4: s31, forming shallow trenches in the surface drift layer, wherein the shallow trenches do not penetrate through the surface drift layer, so that the bottom surface of the second gate structure arranged in the step S5 is non-flat, and the transverse carrier gas channel is discontinuous.
14. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 9, wherein: in step S6, the source electrode structure is conductive polysilicon; after step S6, the method further comprises: s61, forming an interlayer film on the surface blocking layer, wherein the interlayer film substantially covers the first gate structure of the device region, and the interlayer film does not cover the upper end surface of the source structure; s62, disposing source metal on the interlayer film.
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