CN117648272A - Memory device, operation method of memory device and memory system - Google Patents

Abstract

Memory devices, methods of operating memory devices, and memory systems are disclosed. The memory device includes: a data sampler configured to sample a data signal based on a write data strobe signal; a measurement circuit configured to measure a temperature-based delay variation and a voltage-based delay variation of a transfer path of the write data strobe signal; a storage circuit configured to store a first coefficient code that adjusts a reference-based delay variation on a transmission path; a temperature sensor configured to sense a temperature of the conveyance path; a monitoring circuit configured to generate a second coefficient code by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other; a reference voltage generator configured to generate a reference voltage; a voltage regulator configured to generate a regulated voltage; and a write data strobe signal transfer circuit configured to transfer the write data strobe signal to the data sampler.

Description

Memory device, operation method of memory device and memory system

The present application claims the priority rights of korean patent application No. 10-2022-012339 filed at the korean intellectual property office on month 5 of 2022 and korean patent application No. 10-2023-0071135 filed at the korean intellectual property office on month 7 of 2023, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates generally to semiconductor devices, and more particularly, to memory devices that adjust delays on data clock paths, methods of operating memory devices, and memory systems including memory devices.

Background

Electronic devices such as, but not limited to, smart phones, graphics accelerators, and Artificial Intelligence (AI) accelerators may process data through the use of memory devices such as, but not limited to, dynamic Random Access Memory (DRAM). The electronic device may control the internal and/or external memory devices through the memory controller. The memory controller may send various signals to the memory device in order to control the memory device.

The memory devices and memory controllers may use data signals to send and/or receive data. The memory device may sample the data signal using a data clock signal (and/or a write data strobe signal) provided by the memory controller. For example, the memory device may sample the data signal based on the edge timing of the data clock signal. That is, the memory device may transfer the data clock signal to a circuit for sampling the data signal in order to sample the data signal based on the data clock signal. As another example, the memory controller may perform training on the data clock signal to compensate for delays on a path (which may be referred to as a data clock path) used to transmit the data clock signal.

The delay on the data clock path may vary depending on the temperature change of the memory device. When the sampling timing varies according to a delay change on the data clock path, a setup/hold (S/H) margin may be reduced. Thus, the memory controller may perform retraining to compensate for delay changes due to temperature changes. Thus, the memory controller may adjust the delay on the data clock path. However, when retraining is performed, resources for training may increase.

Disclosure of Invention

Aspects of the present disclosure provide a memory device, a method of operating a memory device, and a memory system including a memory device that can adjust a delay on a data clock path according to real-time temperature changes without retraining by a memory controller.

According to an aspect of the present disclosure, a memory device is provided. The memory device includes: a data sampler configured to: the data signal from the memory controller is sampled based on the write data strobe signal from the memory controller. The memory device further includes: measurement circuitry configured to: the temperature-based delay variation is measured based on a temperature of a transfer path of the write data strobe signal, and the voltage-based delay variation is measured based on a voltage on the transfer path of the write data strobe signal. The memory device further includes: a storage circuit configured to: a first coefficient code is stored, the first coefficient code adjusting a reference-based delay variation on a transfer path of a write data strobe signal based on a temperature change. The memory device further includes: a temperature sensor configured to: the temperature of a transfer path of the write data strobe signal is sensed. The memory device further includes: monitoring circuitry configured to: the second coefficient code is generated by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other. The memory device further includes: a reference voltage generator configured to: a reference voltage is generated from the supply voltage based on the second coefficient code. The memory device further includes: a voltage regulator configured to: a regulated voltage is generated based on the reference voltage. The memory device further includes: a write data strobe signal transfer circuit configured to: the write data strobe signal is transferred to the data sampler by using the regulated voltage.

According to an aspect of the present disclosure, a method of operating a memory device is provided. The operation method comprises the following steps: the data signal from the memory controller is sampled based on the write data strobe signal from the memory controller. The operation method further comprises the following steps: the temperature-based delay variation is measured based on a temperature of a transfer path of the write data strobe signal, and the voltage-based delay variation is measured based on a voltage on the transfer path of the write data strobe signal. The operation method further comprises the following steps: a reference-based delay variation is generated based on the first coefficient code and the temperature change of the memory device. The operation method further comprises the following steps: a second coefficient code is generated, the second coefficient code being determined by comparing the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other. The operation method further comprises the following steps: the data signal is sampled by adjusting a delay on a transfer path of the write data strobe signal based on the temperature change of the memory device and the second coefficient code.

According to one aspect of the present disclosure, a memory system is provided. The memory system includes a memory device and a memory controller. The memory device is configured to: the method includes monitoring a temperature-based delay variation based on temperature, monitoring a voltage-based delay variation based on voltage, and monitoring a reference-based delay variation with respect to a write data strobe signal used to sample a data signal. The memory controller is configured to: a first series code for adjusting for reference-based delay variation is determined. The memory device is further configured to: comparing the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other; adjusting a delay on a transfer path of the write data strobe signal based on a temperature change of the memory device; and sampling the data signal.

Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, and/or may be learned by practice of the presented embodiments.

Drawings

The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating a memory system according to an embodiment;

FIG. 2 is a block diagram illustrating a memory system according to an embodiment;

FIG. 3 is a block diagram illustrating a memory device for delay adjustment on the write data strobe signal WDQS path, in accordance with an embodiment;

FIG. 4 is a flow diagram illustrating a latency adjustment operation of a memory system according to an embodiment;

FIG. 5 is a graph illustrating an example of a delay change on a write data strobe signal WDQS path according to a temperature characteristic of a device of a memory device, in accordance with an embodiment;

FIG. 6 is a graph illustrating an example of a delay change on a write data strobe signal WDQS path according to a power supply voltage characteristic of a device of a memory device, in accordance with an embodiment;

FIG. 7 is a table of the operation of the monitoring circuit of FIG. 3, according to an embodiment;

FIG. 8 is a graph showing the results of temperature compensation according to an embodiment;

FIG. 9 is a block diagram illustrating a stacked memory device according to an embodiment;

fig. 10 is a diagram illustrating a semiconductor package according to an embodiment; and is also provided with

Fig. 11 is a diagram showing an example of implementation of a semiconductor package according to an embodiment.

Detailed Description

The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the disclosure defined by the claims and their equivalents. Various specific details are included to aid understanding, but these are considered exemplary only. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

With respect to the description of the drawings, like reference numerals may be used to refer to like or related elements. It is to be understood that the singular form of a noun corresponding to an item may include one or more of the things unless the context clearly indicates otherwise. As used herein, phrases such as "a or B", "at least one of a and B", "at least one of a or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B or C" may each include possible combinations of items listed together in a respective one of the phrases. As used herein, terms such as "1 st" and "2 nd" or "first" and "second" may be used to simply distinguish corresponding components from additional components and not to otherwise limit the components (e.g., importance or order). It will be understood that if an element (e.g., a first element) is referred to as being "coupled" to, "coupled to," or "connected" with another element (e.g., a second element) with or without the term "operably" or "communicatively," it can be directly (e.g., wired), wirelessly, or via a third element.

It will be understood that when an element or layer is referred to as being "on," "over," "on," "under," "connected to" or "bonded to" another element or layer, it can be directly on, over, under, connected to or bonded to the other element or layer or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly above," "directly on," "directly under," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

The terms "upper," "middle," "lower," and the like may be replaced with terms such as "first," "second," "third," and the like, to describe the relative positions of elements. The terms "first," second, "and" third "may be used to describe various elements, but the elements are not limited by the terms, and the" first element "may be referred to as the" second element. Alternatively or additionally, the terms "first," "second," "third," and the like may be used to distinguish components from one another and do not limit the present disclosure. For example, the terms "first," "second," "third," and the like may not necessarily refer to any form of order or numerical meaning.

Reference throughout this disclosure to "one embodiment," "an example embodiment," or similar language may indicate that a particular feature, structure, or characteristic described in connection with the embodiment indicated is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment," "in an example embodiment," and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment.

It should be understood that the specific order or hierarchy of blocks in the processes/flowcharts disclosed is an illustration of exemplary approaches. Based on design preferences, it is understood that the specific order or hierarchy of blocks in the processes/flow charts may be rearranged. Furthermore, some blocks may be combined or omitted. The appended claims present elements of the various blocks in a sample order and are not meant to be limited to the specific order or hierarchy presented.

As shown in the figures, embodiments may be described and illustrated herein as blocks that perform one or more of the functions described. These blocks (which may be referred to herein as units or modules, etc., or by designations such as devices, logic, circuits, counters, comparators, generators, converters, etc.) may be physically implemented by analog and/or digital circuits, including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc., and may also be implemented or driven by software and/or firmware (configured to perform the functions or operations described herein).

Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a memory system according to an embodiment.

Referring to fig. 1, a memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may control the overall operation of the memory device 200. For example, the memory controller 100 may control the memory device 200 to output the DATA from the memory device 200. Alternatively or additionally, the memory controller 100 may control the memory device 200 to store the DATA in the memory device 200.

The memory controller 100 may send and/or receive various signals to and/or from the memory device 200. For example, the memory controller 100 may send command/address signals CA, clock signals CK, write data strobe signals WDQS, and/or data signals DQ to the memory device 200. Alternatively or additionally, the memory controller 100 may receive the data signal DQ from the memory device 200. The command/address signal CA may include a command CMD and/or an address ADD. The DATA signal DQ may include DATA.

In one embodiment, the memory controller 100 may be implemented in a host and may access the memory device 200 upon request of a processor included in the host. For example, the memory controller 100 may access the memory device 200 in a Direct Memory Access (DMA) method. As another example, the memory controller 100 may be implemented as part of a system on a chip (SoC), but the disclosure is not limited thereto.

The memory device 200 may operate as at least one of a buffer memory, a working memory, and a main memory for a host including the memory controller 100. That is, the memory device 200 may operate under the control of the memory controller 100. For example, the memory device 200 may output the stored DATA under the control of the memory controller 100. As another example, the memory device 200 may store DATA provided by the memory controller 100.

The memory device 200 may receive various signals from the memory controller 100 and/or may send various signals to the memory controller 100. For example, memory device 200 may receive command/address signal CA, clock signal CK, write data strobe signal WDQS, and data signal DQ from memory controller 100. Alternatively or additionally, the memory device 200 may send the data signal DQ to the memory controller 100.

The memory controller 100 may include a Phase Locked Loop (PLL) 110, a first transmitter 130, a second transmitter 140, a third transmitter 160, and a fourth transmitter 170. The PLL 110 may generate an internal clock signal ICS. For example, the internal clock signal ICS may have a specific frequency (e.g., a repetition period) and may be switched between a high level and a low level.

The first transmitter 130 may transmit the command/address signal CA to the memory device 200 based on the internal clock signal ICS. For example, the first transmitter 130 may transmit the command CMD and/or the address ADD to the memory device 200 through the command/address signal CA at the timing of the rising edge and/or the falling edge of the internal clock signal ICS. The command/address signal CA may be sent to the memory device 200 through the command/address pin ca_p'.

The second transmitter 140 may transmit the internal clock signal ICS as the clock signal CK to the memory device 200. For example, the internal clock signal ICS and the clock signal CK may have substantially similar and/or identical frequencies, and/or substantially similar and/or identical phases. As another example, the second transmitter 140 may divide the internal clock signal ICS and transmit the divided internal clock signal dcss as the clock signal CK to the memory device 200. In this example, the divided internal clock signal dcs and the clock signal CK may have different frequencies (e.g., multiple) and/or different phases. The clock signal CK may be sent to the memory device 200 through the clock pin ck_p'.

The third transmitter 160 may transmit the internal clock signal ICS as a write data strobe signal WDQS to the memory device 200. For example, the internal clock signal ICS and the write data strobe signal WDQS may have substantially similar and/or identical frequencies, and/or substantially similar and/or identical phases. As another example, the third transmitter 160 may divide the internal clock signal ICS and transmit the divided internal clock signal dcss to the memory device 200 as the write data strobe signal WDQS. In this example, the divided internal clock signal dcs and the write data strobe signal WDQS may have different frequencies (e.g., frequency multiplication) and/or different phases. The write data strobe signal WDQS may be transmitted to the memory device 200 through the write data strobe pin W_P'.

The fourth transmitter 170 may send the data signal DQ to the memory device 200 based on the internal clock signal ICS. For example, the fourth transmitter 170 may transmit the DATA to the memory device 200 through the DATA signal DQ at the timing of the rising edge and/or the falling edge of the internal clock signal ICS. The data signal DQ may be sent to the memory device 200 through the data pin d_p'.

As shown in FIG. 1, the clock signal CK and the write data strobe signal WDQS may be generated by a PLL 110. Accordingly, the operating current of the memory controller 100 may be reduced. However, the present disclosure is not limited thereto, and each of the clock signal CK and the write data strobe signal WDQS may be generated by a separate PLL.

Memory device 200 may include a command/address (CA) sampler 210, a Clock (CK) receiver 220, a write data strobe signal (WDQS) transfer circuit 230, and a data sampler 240.

The Clock (CK) receiver 220 may receive a clock signal CK from the memory controller 100 through a clock pin ck_p. The clock signal CK received by the Clock (CK) receiver 220 may be sent to the command/address (CA) sampler 210.

Command/address (CA) sampler 210 may receive command/address signals CA from memory controller 100 via command/address pins ca_p. The command/address (CA) sampler 210 may sample the command/address signal CA based on the clock signal CK. For example, the command/address (CA) sampler 210 may sample the command/address signal CA at the timing of the rising and/or falling edges of the clock signal CK. Thus, the memory device 200 may obtain a command and/or address CMD/ADD.

The write data strobe signal WDQS transmitting circuit 230 may receive the write data strobe signal WDQS from the memory controller 100 via the write data strobe pin W_P. WDQS transfer circuit 230 may transfer write data strobe signal WDQS to data sampler 240. In one embodiment, the WDQS transmission circuit 230 may include a WDQS receiver and a WDQS tree circuit. For example, the WDQS receiver may receive a write data strobe signal WDQS provided by a write data strobe pin W_P. The WDQS tree circuit may include a plurality of repeaters for transmitting the write data strobe signal WDQS output from the WDQS receiver to the data sampler 240. For example, each of the plurality of repeaters may be implemented as at least one buffer or inverter.

The data sampler 240 may receive a data signal DQ from the memory controller 100 via the data pin d_p. The data sampler 240 may sample the data signal DQ based on the write data strobe signal WDQS. For example, the data sampler 240 may sample the data signal DQ at the timing of the rising and/or falling edges of the write data strobe signal WDQS. Thus, the memory device 200 may obtain the DATA.

In one embodiment, memory device 200 may sample data signal DQ based on a write data strobe signal WDQS that may be different than clock signal CK. That is, the write data strobe signal WDQS may be a clock signal (e.g., a data clock signal) for data communication.

In one embodiment, the path through which the write data strobe signal WDQS passes from the write data strobe pin W_P to the data sampler 240 (hereinafter WDQS path WDQS_P) may be mismatched with the path through which the data signal DQ passes from the data pin D_P to the data sampler 240 (hereinafter DQ path DQ_P). For example, the circuitry on the WDQS paths WDQS_P and DQ paths DQ_P may be asymmetrically arranged. As another example, the number of transistors included in the WDQS path wdqs_p may be different from the number of transistors included in the DQ path dq_p. Accordingly, even though training may have been performed on the write data strobe signal WDQS during the initialization process of the memory device 200, the delay change on the WDQS path WDQS_P and/or the delay change on the DQ path DQ_P according to temperature changes may be different from each other. Thus, the arrival timing (e.g., sampling timing) of the write data strobe signal WDQS transmitted to the data sampler 240 may vary. For example, the delay change on the WDQS path WDQS_P as a function of temperature change may vary depending on the characteristics of the devices on the WDQS path WDQS_P. Accordingly, a setup/hold (S/H) margin of the data sampler 240 may be reduced.

According to some embodiments, delay changes on the WDQS path WDQS_P according to temperature changes may be compensated for without retraining the write data strobe signal WDQS. For example, the memory device 200 may adjust the delay on the WDQS path WDQS_P based on real-time sensed temperature changes taking into account the characteristics of the circuitry on the WDQS path WDQS_P. Thus, the delay on the WDQS path WDQS_P based on training performed in the initialization process of the memory device 200 may be maintained. Thus, the S/H margin of the data sampler 240 may be improved and data errors may be reduced when compared to an associated memory device, regardless of temperature changes.

FIG. 2 is a block diagram illustrating a memory system according to an embodiment.

Referring to fig. 2, the memory system 20 may include a memory controller 300 and a memory device 400. The memory controller 300 of fig. 2 may include and/or may be similar in many respects to the memory controller 100 described above with reference to fig. 1, and may include additional features not mentioned above. Furthermore, the memory device 400 of FIG. 2 may include and/or may be similar in many respects to the memory device 200 described above with reference to FIG. 1, and may include additional features not mentioned above. Accordingly, the repetitive description of the memory controller 300 and the memory device 400 described above with reference to fig. 1 may be omitted for brevity.

The memory controller 300 may include a code determination circuit 310. The code determination circuit 310 may control the initialization operation and/or the test operation of the memory device 400. The code determination circuit 310 may determine a code in an initialization operation and/or a test operation of the memory device 400 and set the determined code in the memory device 400. As used herein, a deterministic code may refer to a deterministic number. For example, coefficient codes may include Negative Temperature Coefficient (NTC) and Positive Temperature Coefficient (PTC). As the temperature value increases, the resistance value of the NTC may decrease. Alternatively or additionally, the resistance value of the PTC may increase as the temperature value increases. The coefficient code may adjust for Low Drop Out (LDO) reference voltage variations based on temperature variations. For example, the coefficient code may correspond to a delay adjustment amount for adjusting the delay on the WDQS path WDQS_P. In one embodiment, the coefficient code may be referred to as a delay code. The delay on the WDQS path WDQS_P may be maintained constant regardless of temperature changes as the delay on the WDQS path WDQS_P is adjusted according to the coefficient code. In one embodiment, the code determination circuit 310 may be implemented as a processor, such as, but not limited to, a Central Processing Unit (CPU), of the memory controller 300. However, the present disclosure is not limited thereto, and the code determination circuit 310 may be implemented in various forms without departing from the scope of the present disclosure. For example, the code determination circuit 310 may be implemented as an integrated circuit, software, and/or a combination of circuitry and software.

In one embodiment, the code determination circuit 310 may determine the coefficient code based on a previously determined temperature. Alternatively or additionally, the code determination circuit 310 may communicate the determined coefficient code to the memory device 400. For example, the code determination circuit 310 may determine the coefficient code based on information about the temperature of the write data strobe signal WDQS.

The memory device 400 may include a write data strobe signal (WDQS) transfer circuit 410, a data sampler 420, and a storage circuit 450.WDQS transfer circuit 410 may transfer a write data strobe signal WDQS provided by memory controller 300 to data sampler 420. The data sampler 420 may sample the data signal DQ provided by the memory controller 300 based on the write data strobe signal WDQS.

The memory circuit 450 may store coefficient codes provided by the memory controller 300. In one embodiment, the storage circuit 450 may be implemented as a register and/or a fuse (also referred to as a fuse). For example, the memory circuit 450 may be and/or may include a mode register when the first code and the second code are set during an initialization process of the memory device 400. As another example, when the coefficient code is set during a test process of the memory device 400, the memory circuit 450 may be and/or may include a test mode register and/or a fuse.

FIG. 3 is a block diagram illustrating a memory device for delay adjustment on a WDQS path WDQS_P, in accordance with an embodiment.

The memory device 500 of fig. 3 may include and/or may be similar in many respects to at least one of the memory device 200 described above with reference to fig. 1 and the memory device 400 described above with reference to fig. 2, and may include additional features not mentioned above. Accordingly, for brevity, the repeated description of the memory device 500 described above with reference to fig. 1 and 2 may be omitted.

Referring to FIG. 3, memory device 500 may include a storage circuit 510, a temperature sensor 520, a monitoring circuit 530, a reference voltage generator 540, a voltage regulator 550, a write data strobe signal (WDQS) transfer circuit 560, and a data sampler 570. The memory circuit 510 may include and/or may be similar in many respects to the memory circuit 450 of fig. 2, and may include additional features not mentioned above. The WDQS transmit circuit 560 may include and/or may be similar in many respects to at least one of the WDQS transmit circuit 230 described above with reference to FIG. 1 and the WDQS transmit circuit 410 described above with reference to FIG. 2, and may include additional features not mentioned above. The data sampler 570 may include and/or may be similar in many respects to the data sampler 240 described above with reference to fig. 1 and the data sampler 420 described above with reference to fig. 2, and may include additional features not mentioned above. Accordingly, for brevity, the repeated descriptions of the memory circuit 510, the WDQS transmission circuit 560, and the data sampler 570 described above with reference to FIGS. 1 and 2 may be omitted.

The memory circuit 510 may store the coefficient code CCODE. As described with reference to fig. 1 and 2, the coefficient code CCODE may be determined by the memory controllers 100 and 300 during an initialization process and/or a test process. For example, in one example, the memory circuit 510 may be implemented as at least one of a mode register, a test mode register, and a fuse. In another example, the memory circuit 510 may be and/or may include a mode register, and the mode register may store coefficient codes provided by the memory controllers 100 and 300 and/or determined coefficient codes output by the monitor circuit 530 based on mode register set commands from the memory controllers 100 and 300.

Measurement circuit 515 may measure the temperature and voltage on WDQS path WDQS_P. For example, measurement circuit 515 may measure delay variation TD (e.g.,where Δdelay represents delay time variation). Alternatively or additionally, measurement circuit 515 may measure the delay variation VD (e.g., +.>Where Δvoltage represents a voltage change). The measurement circuit 515 may communicate the delay variation TD and the delay variation VD to the monitoring circuit 530.

The temperature sensor 520 may sense the temperature of the memory device 500. The temperature sensor 520 may provide a temperature code TCODE based on the sensed current temperature to the monitoring circuit 530.

The monitoring circuit 530 may monitor the delay variation TVD. The delay variation TVD (for example,) May refer to an LDO reference voltage change Δv_ldo_ref according to a temperature change Δtemp. That is, the delay variation TVD may be obtained by dividing the LDO reference voltage variation Δv_ldo_ref by the temperature variation Δtemp. The determined coefficient code CCODE may correspond to a delay adjustment amount used to adjust the delay on the WDQS path wdqs_p. For example, the monitoring circuit 530 may calculate the temperature change based on a previously determined reference temperature and the temperature code TCODE. Alternatively or additionally, the monitoring circuit 530 may generate the determined coefficient code CCODE for adjusting the delay by comparing the sensed temperature, delay variation TD, delay variation VD, and delay variation TVD corresponding to the temperature code TCODE with each other. For example, the monitoring circuit 530 may compare the delay variation TD and the delay variation VD with the delay variation TVD. In one example of this, in one implementation,when the ratio obtained by dividing the delay variation TD by the delay variation VD matches the delay variation TVD, the monitoring circuit 530 may generate a determined coefficient code CCODE for adjusting the delay. For example, when the ratio obtained by dividing the delay variation TD by the delay variation VD is equal to the value obtained by multiplying the delay variation TVD by-1, the monitoring circuit 530 may output the determined coefficient code CCODE for adjusting the delay. That is, the absolute value of the ratio of the delay variation TD and the delay variation VD may be substantially similar and/or identical to the absolute value of the delay variation TVD, but the sign (e.g., positive, negative) of the ratio of the delay variation TD and the delay variation VD and the sign of the delay variation TVD may be different. In one example, the monitoring circuit 530 may adjust the delay variation TVD based on the determined coefficient code CCODE used to adjust the delay. For example, the delay on the write data strobe signal WDQS path may be maintained constant regardless of temperature changes as the delay on the WDQS path WDQS_P is adjusted according to the determined coefficient code CCODE.

The reference voltage generator 540 may generate the reference voltage VREF from the power supply voltage VDDQ based on the determined coefficient code CCODE. The reference voltage generator 540 may generate a reference voltage VREF having a level corresponding to the determined coefficient code CCODE.

Voltage regulator 550 may generate regulated voltage VLDO based on reference voltage VREF. For example, voltage regulator 550 may generate regulated voltage VLDO having a level lower than the level of reference voltage VREF. The regulated voltage VLDO output from voltage regulator 550 may be provided to WDQS transmission circuit 560.

WDQS transfer circuit 560 may transfer write data strobe signal WDQS to data sampler 570.WDQS transfer circuit 560 may transfer write data strobe signal WDQS to data sampler 570 using supply voltage VDDQ and regulated voltage VLDO. For example, some of the repeaters (or inverters) of the WDQS transmit circuit 560 may operate using the supply voltage VDDQ. Alternatively or additionally, the remaining repeaters (or inverters) of the WDQS transmit circuit 560 may operate using the regulated voltage VLDO. In such an example, the delay of the write data strobe signal WDQS transmitted by the repeater operating with the regulated voltage VLDO may be controlled in accordance with the level of the regulated voltage VLDO.

The data sampler 570 may sample the data signal DQ based on the write data strobe signal WDQS. When the delay on the WDQS path WDQS_P is adjusted based on the adjustment voltage VLDO, the S/H margin of the data sampler 570 may be increased regardless of temperature. Accordingly, the error rate of the data output from the data sampler 570 may be reduced.

In one embodiment, memory device 500 may control the level of regulated voltage VLDO applied to WDQS transmission circuit 560 by voltage regulator 550 based on previously stored coefficient code CCODE, delay variation TD, delay variation VD, delay variation TVD, and temperature code TCODE. Thus, memory device 500 may adjust the delay on WDQS path WDQS_P based on the temperature sensed in real-time without retraining by a memory controller (e.g., memory controller 100 of FIG. 1, memory controller 300 of FIG. 2).

FIG. 4 is a flow diagram illustrating a latency adjustment operation according to a memory system according to an embodiment.

That is, the operation of the memory system to adjust the delay on the WDQS path WDQS_P based on temperature changes is described with reference to FIG. 4.

Referring to fig. 3 and 4, in operation S110, the memory device 500 may measure a delay variation TD according to a temperature on a WDQS path wdqs_p. For example, memory device 500 may use measurement circuit 515 to measure delay variation TD from the temperature on WDQS path WDQS_P.

In operation S120, the memory device 500 may measure the delay variation VD according to a voltage on the WDQS path wdqs_p. For example, memory device 500 may use measurement circuit 515 to measure the delay variation VD from the voltage on the WDQS path wdqs_p.

With continued reference to fig. 2 through 4, in operation S130, the memory controller 300 may enable the coefficient code CCODE. For example, the memory controller 300 may enable the coefficient code CCODE using the code determination circuit 310. In one embodiment, the code determination circuit 310 may enable the coefficient code CCODE according to an enable command. Code determination circuit 310 may communicate coefficient code CCODE to memory device 400 when coefficient code CCODE is enabled.

In operation S140, the memory device 500 may generate the delay variation TVD based on the coefficient code CCODE. For example, the memory device 500 may monitor the delay variation TVD based on the coefficient code CCODE using the monitoring circuit 530. In one example, memory device 500 may generate an LDO reference voltage change based on a coefficient code CCODE from a change in temperature.

In operation S150, the memory device 500 may determine whether a ratio obtained by dividing the delay variation TD by the delay variation VD is equal to a value obtained by multiplying the delay variation TVD by-1.

When the ratio obtained by dividing the delay variation TD by the delay variation VD is not equal to the value obtained by multiplying the delay variation TVD by-1 (no in operation S150), the memory device 500 and/or the memory controller 300 may change the coefficient code CCODE in operation S160. For example, the memory controller 300 may use the code determination circuit 310 to change the coefficient code CCODE.

Alternatively or additionally, when the ratio obtained by dividing the delay variation TD by the delay variation VD is equal to the value obtained by multiplying the delay variation TVD by-1 (yes in operation S150), the memory device 500 may determine the coefficient code CCODE in operation S170. For example, the monitor circuit 530 of the memory device 500 may output the determined coefficient code CCODE. The determined coefficient code CCODE may correspond to a delay adjustment amount used to adjust the delay on the WDQS path wdqs_p.

In operation S180, the memory device 500 may sample the data signal DQ based on the write data strobe signal WDQS according to the real-time temperature. In one embodiment, the write data strobe signal WDQS may be transmitted to the data sampler 240 using WDQS transmission circuit 230. In such embodiments, the timing of the arrival of the write data strobe signal WDQS at the data sampler 240 may be maintained constant regardless of temperature changes of the memory device 200. That is, the value of the voltage on the WDQS path WDQS_P may be adjusted according to the temperature change on the WDQS path WDQS_P using the value of the delay variation TVD determined in operation S170. When the temperature t1 on the WDQS path wdqs_p monitored at the first time and the temperature t2 on the WDQS path wdqs_p monitored at the second time after the first time are different from each other, the voltage on the WDQS path wdqs_p may be increased by "a value obtained by multiplying the difference between the temperature t2 and the temperature t1 by the delay variation TVD". That is, the voltage v2 on the second-time WDQS path wdqs_p may be determined to be equal to a result obtained by adding "a value obtained by multiplying the difference between the temperature t2 and the temperature t1 by the delay variation TVD" to the voltage v1 on the first-time WDQS path wdqs_p (for example, v2=v1+tvd× (t 2-t 1)). The data sampler 240 may sample the data signal DQ based on the write data strobe signal WDQS.

According to the memory system 10 of the present disclosure, the memory device 200 may compensate for delay variations on the WDQS path WDQS_P according to real-time temperature changes based on the coefficient code CCODE determined during an initialization process or a test process. That is, the delay on the WDQS path WDQS_P may be maintained constant without retraining by the memory controller 100. Accordingly, retraining may not need to be performed to compensate for delay changes on the WDQS path WDQS_P due to temperature changes.

FIG. 5 is a graph illustrating an example of a delay change on WDQS path WDQS_P according to a temperature characteristic of a device of a memory device, according to an embodiment.

Referring to FIG. 5, the horizontal axis represents temperature values and the vertical axis may represent delay on the WDQS path WDQS_P in picoseconds (ps). Referring to FIGS. 2 and 5, the delay variation on WDQS path WDQS_P as a function of temperature may vary depending on the device characteristics of WDQS transmit circuit 410. As used herein, the delay variation on the WDQS path wdqs_p according to a temperature change may refer to the delay variation TD described with reference to fig. 3 and 4. Device characteristics may be distinguished by the process corner (process corner) of the device (e.g., transistor) on the WDQS path WDQS_P. For example, device characteristics may be divided into slow process corners, typical process corners, and fast process corners.

When the devices of the WDQS transmission circuit 410 have the first device characteristic 592 (e.g., when the devices of the WDQS transmission circuit 410 correspond to a slow process corner), the delay on the WDQS path WDQS_P may be reduced as the temperature of the memory system 20 increases.

When the devices of the WDQS transmission circuit 410 have the second device characteristic 594 (e.g., when the devices of the WDQS transmission circuit 410 correspond to typical process corners), the delay on the WDQS path WDQS_P may be reduced as the temperature of the memory system 20 increases. As shown in fig. 5, the delay reduction corresponding to the second device characteristic 594 may be less than the delay reduction corresponding to the first device characteristic 592.

When the devices of the WDQS transmission circuit 410 have the third device characteristic 596 (e.g., when the devices of the WDQS transmission circuit 410 correspond to a fast process corner), the delay on the WDQS path WDQS_P may be increased as the temperature of the memory system 20 increases.

As shown in fig. 5, the delay on the WDQS path wdqs_p may vary linearly (and/or substantially linearly) with temperature, depending on the device characteristics of the WDQS pass circuit 410. Thus, the coefficient code reflecting the device characteristics may be calculated based on the delay value on the WDQS path WDQS_P corresponding to the current temperature. For example, the coefficient code may be calculated as a slope that varies according to a delay of temperature. That is, when the memory device 400 compensates for the delay change by using the coefficient code calculated based on the delay value of the temperature, temperature compensation reflecting the device characteristics may be performed.

FIG. 6 is a graph illustrating an example of a delay change on WDQS path WDQS_P according to a power supply voltage characteristic of a device of a memory device, according to an embodiment.

In FIG. 6, the horizontal axis may represent supply voltage and the vertical axis may represent delay on WDQS path WDQS_P.

Referring to FIGS. 2 and 6, the delay variation on WDQS path WDQS_P as a function of supply voltage changes may vary depending on the device characteristics of WDQS transmit circuit 410. As used herein, the delay variation on the WDQS path wdqs_p according to the change in the power supply voltage may refer to the delay variation VD described with reference to fig. 3 and 4. Thus, as the supply voltage increases, the delay variation may increase.

As shown in fig. 6, the delay on the WDQS path wdqs_p according to the device characteristics of the WDQS pass circuit 410 may vary linearly (and/or substantially linearly) according to the supply voltage variation. Thus, the coefficient code reflecting the device characteristics may be calculated based on the delay value on the WDQS path WDQS_P corresponding to the power supply voltage. For example, the coefficient code may be calculated as an inclination that changes according to a delay of the voltage. That is, when the memory device 400 compensates for the delay change by using the coefficient code calculated based on the delay value of the voltage, temperature compensation reflecting the device characteristics may be performed.

Fig. 7 is a table of the operation of the monitoring circuit 530 of fig. 3 according to an embodiment.

Referring to fig. 3 and 7, the monitoring circuit 530 may compare the current temperature with a reference temperature to calculate a temperature code TCODE, which is a temperature change. For example, the reference temperature may be stored in the monitoring circuit 530 in advance.

The monitoring circuit 530 may monitor the temperature code TCODE and the coefficient code CCODE.

In one example, the monitor circuit 530 may generate the coefficient code CCODE based on a change in the write data strobe signal WDQS (e.g., a reference-based delay change TVD on the transmission path of the write data strobe signal WDQS) and a temperature change corresponding to the temperature code TCODE, and generate the coefficient code CCODE based on a coefficient code enable command from the memory controller. For example, as shown in fig. 3 and 7, the monitoring circuit 530 may output a first coefficient code CCODE1 corresponding to the first temperature code TCODE1, may output a second coefficient code CCODE2 corresponding to the second temperature code TCODE2, and may output an nth coefficient code CCODE (where n is an integer greater than 2) corresponding to the nth temperature code TCODE.

That is, the coefficient code CCODE may reflect the device characteristics of the WDQS transmission circuit.

Fig. 8 is a graph illustrating a result according to temperature compensation according to an embodiment.

The first through third device characteristics 592, 594, 596 of fig. 8 may be similar in many respects to the first through third device characteristics 592, 594, 596 described with reference to fig. 5. Accordingly, for brevity, the repeated descriptions of the first through third device characteristics 592, 594, 596 of fig. 8 described above with reference to fig. 5 may be omitted.

Referring to fig. 5 and 8, the delay reduction of the first result 593 may be less than the delay reduction of the first device characteristic 592.

In one embodiment, the delay reduction of the second result 595 may be less than the delay reduction of the second device characteristic 594.

In alternative or additional embodiments, the amount of delay reduction of third result 597 may be less than the amount of delay reduction of third device characteristic 596.

According to some embodiments, the delay on the data clock path may be adjusted in consideration of the characteristics of the circuits on the data clock path according to the temperature change sensed in real time. That is, delay changes on the data clock path according to temperature changes may be compensated for without retraining the data clock signal. Accordingly, an S/H margin for sampling the data signal can be improved regardless of temperature change, and data errors can be reduced.

Fig. 9 is a diagram illustrating a stacked memory device according to an embodiment.

Referring to fig. 9, a stacked memory device 700 may include and/or may be similar in many respects to at least one of memory device 200, memory device 400, and memory device 500 described with reference to fig. 1-8, and may include additional features not mentioned above. Accordingly, for brevity, the repeated description of the stacked memory device 700 described above with reference to fig. 1-8 may be omitted.

Stacked memory device 700 may include a buffer die 710 and a plurality of core dies 720-750. For example, buffer die 710 may also be referred to as an interface die, a base die, a logic die, a master die, and the like. Alternatively or additionally, each of core dies 720 through 750 can be referred to as a memory die, a slave die, or the like. The stacked memory device 700 shown in fig. 9 includes four core dies 720-750. However, the present disclosure is not limited in this respect. That is, the number of core dies may be varied in various ways. For example, stacked memory device 700 may include 8, 12, and/or 16 core dies.

The buffer die 710 and the core dies 720-750 may be stacked and electrically connected to each other via through silicon vias (TSVs, also referred to as through silicon vias). Thus, stacked memory device 700 may have a three-dimensional (3D) memory structure in which multiple dies 710-750 are stacked. For example, stacked memory device 700 may be implemented based on High Bandwidth Memory (HBM) and/or Hybrid Memory Cube (HMC) standards.

The stacked memory device 700 may support multiple channels (and/or libraries) that are functionally independent. For example, as shown in fig. 9, stacked memory device 700 may support 16 channels CH 0-CH 15. When each of the channels CH0 through CH15 supports 64 data transfer paths (e.g., when there are respective 64 data signal DQ pins corresponding to the channels CH0 through CH15, respectively), the stacked memory device 700 including 16 channels CH0 through CH15 may support 1024 data transfer paths. However, the present disclosure is not limited thereto, and the stacked memory device 700 may support 1024 or more data transfer paths, and may support various numbers of channels (e.g., eight (8) channels). For example, when stacked memory device 700 supports eight (8) lanes and each lane supports 128 data transfer paths, stacked memory device 700 may support 1024 data transfer paths.

Each of the core dies 720-750 can support at least one channel. For example, as shown in fig. 9, core dies 720-750 may support four (4) channels CH 0-CH 3, CH 4-CH 7, CH 8-CH 11, and CH 12-CH 15, respectively. In such examples, core dies 720 through 750 may support different channels. However, the present disclosure is not limited thereto, and at least two of the core dies 720 through 750 may support the same channel. For example, when stacked memory device 700 includes eight (8) core dies, one of the four (4) core dies making up one stack and one of the other four (4) core dies making up the other stack among the eight (8) core dies may support the same channel. In such examples, core dies supporting the same lane may be distinguished by a Stack ID (SID).

Each of the channels CH0 to CH15 may constitute an independent command and data interface. For example, each of channels CH0 through CH15 may be independently clocked based on independent timing requirements and may not be synchronized with each other.

Each of the channels CH0 to CH15 may include a plurality of memory banks 701 (or banks 701). Each memory bank 701 may include memory cells, sense amplifiers, etc. connected to word lines and bit lines. For example, each of channels CH0 through CH15 may include memory bank 701 (e.g., 32 memory banks). However, the present disclosure is not limited thereto, and each of the channels CH0 to CH15 may include eight (8) or more memory banks 701. The memory banks 701 included in one channel are shown in fig. 9 as being included in one core die, however, the memory banks 701 included in one channel may be distributed over a plurality of core dies. For example, when two core dies among the core dies support the first channel CH0, the memory banks 701 of the first channel CH0 may be distributed between the two core dies.

In one embodiment, one channel may be divided into two pseudo channels that operate independently. For example, a dummy channel may share a command and/or clock input (e.g., clock signal CK and/or clock enable signal CKE) of the channel, but may decode and execute the command independently. For example, when one channel supports 64 data transfer paths, each dummy channel may support 32 data transfer paths. As another example, when one channel includes 32 memory banks 701, each dummy channel may include 16 memory banks 701.

Each of the core dies 720 through 750 and the buffer die 710 may include a TSV area 702. TSVs configured to penetrate through core dies 720-750 may be disposed in TSV region 702. Buffer die 710 may send and/or receive various signals to and/or from core dies 720-750 through TSVs. Each of the core dies 720-750 can send signals to and/or receive signals from the buffer die 710 and other core dies through TSVs. That is, signals may be independently transmitted and/or received through the corresponding TSVs for each channel. For example, when an external host device (e.g., the memory controller 100 of fig. 1) transmits a data signal through the first channel CH0 to store data in the memory cells of the first channel CH0, the buffer die 710 may transmit the data signal to the first core die 720 through TSVs corresponding to the first channel CH 0. Thus, data may be stored in the memory cells of the first channel CH 0.

In one embodiment, the supply voltage VDDQL may be used for signaling through TSVs. Supply voltage VDDQL may be lower than supply voltage VDDQ for the overall operation of buffer die 710. For example, supply voltage VDDQ may have a voltage level of about 1.1 volts (V). As another example, the power supply voltage VDDQL may have a voltage level of about 0.4V.

The buffer die 710 may include a physical layer PHY 711. The physical layer PHY 711 may include interface circuitry for communicating with an external host device. In one embodiment, physical layer PHY 711 may include interface circuitry corresponding to each of channels CH0 through CH 15. For example, interface circuitry corresponding to one channel may include elements 210 through 240 of memory device 200 of FIG. 1. Signals received from the host device through the physical layer PHY 711 may be transferred to the core dies 720-750 through TSVs.

In one embodiment, buffer die 710 may include a channel controller corresponding to each of channels CH0 through CH 15. The channel controller may manage memory reference operations for the corresponding channel and may determine timing requirements for the corresponding channel.

In one embodiment, buffer die 710 may include multiple pins for receiving signals from an external host device. As described with reference to fig. 1, the buffer die 710 may receive a clock signal CK, a command/address signal CA, a write data strobe signal WDQS, and a data signal DQ, and transmit the data signal DQ through a plurality of pins.

In one embodiment, stacked memory device 700 may also include Error Correction Code (ECC) circuitry for detecting and correcting errors in the data. For example, in a write operation, the ECC circuit may generate parity bits for data transferred from the host device. In a read operation, the ECC circuit may detect and correct errors in data transferred from one of the core dies 720 to 750 by using the parity bits and send the error corrected data to the host device.

In one embodiment, as described with reference to FIGS. 1-8, the stacked memory device 700 may store coefficient codes for compensating for delay changes on the WDQS path WDQS_P as a function of temperature changes. For example, the coefficient code may be determined during an initialization process or a test process of the stacked memory device 700. The stacked memory device 700 may adjust the delay on the WDQS path WDQS_P according to real-time temperature based on stored coefficient codes or determined coefficient codes. Thus, even if the temperature of the stacked memory device 700 changes, the stacked memory device 700 may maintain the delay on the WDQS path WDQS_P constant without retraining by the host device. Thus, the S/H margin for sampling the data signal DQ may be improved when compared to an associated memory device, regardless of temperature changes.

Fig. 10 is a diagram illustrating a semiconductor package according to an embodiment.

Referring to fig. 10, a semiconductor package 1000 may include a stacked memory device 1100, a system on a chip (SoC) 1200, an intermediate layer (interposer) 1300, and a package substrate 1400. Stacked memory device 1100 may include buffer die 1110 and core dies 1120-1150. The stacked memory device 1100 may include and/or may be similar in many respects to the stacked memory device 700 described with reference to fig. 9, and may include additional features not mentioned above. Accordingly, for brevity, the repeated description of stacked memory device 700 described above with reference to fig. 9 may be omitted.

Each of the core dies 1120-1150 may include a memory unit for storing data. The buffer die 1110 may include a physical layer PHY 1111 and a direct access area DAB 1112. The physical layer PHY 1111 may be electrically connected to the physical layer PHY 1210 of the SoC 1200 through the intermediate layer 1300. Stacked memory device 1100 may receive signals from SoC 1200 and/or send signals to SoC 1200 through physical layer PHY 1111. The physical layer PHY 1111 may include and/or may be similar in many respects to elements of the buffer die 710 described with reference to fig. 9, and may include additional features not mentioned above. Accordingly, the repeated description of the physical layer PHY 1111 described above with reference to fig. 9 may be omitted for brevity.

The direct access area DAB 1112 may provide an access path through which the stacked memory device 1100 may be tested without passing through the SoC 1200. The direct access area DAB 1112 may include conductive means (e.g., ports or pins) for directly communicating with external test devices. Test signals received through the direct access area DAB 1112 may be transmitted to the core dies 1120-1150 through the TSV 1101. To test the core dies 1120-1150, data read from the core dies 1120-1150 may be transmitted to the test device through the TSVs and the direct access area DAB 1112. Thus, direct access testing of core dies 1120-1150 may be performed.

The buffer die 1110 and the core dies 1120-1150 may be electrically connected to each other through TSVs 1101 and bumps (bumps) 1102. The buffer die 1110 may receive signals provided to each channel from the SoC 1200 through the bumps 1102 assigned for each channel. Alternatively or additionally, the buffer die 1110 may send signals to the SoC 1200 through the bumps 1102. For example, bump 1102 may be a microbump.

The SoC 1200 can execute applications supported by the semiconductor package 1000 by using the stacked memory device 1100. For example, soC 1200 may include, but is not limited to, at least one of a CPU, an Application Processor (AP), a Graphics Processor (GPU), a Neural Processor (NPU), a Tensor Processor (TPU), a Vision Processor (VPU), an Image Signal Processor (ISP), and a Digital Signal Processor (DSP) to perform specialized operations.

SoC 1200 can control the overall operation of stacked memory device 1100. The SoC 1200 may include and/or may be similar in many respects to at least one of the memory controller 100 described above with reference to fig. 1 and the memory controller 300 described above with reference to fig. 2. The system-on-chip 1200 may include a physical layer PHY 1210. Physical layer PHY 1210 may include interface circuitry to send signals to physical layer PHY 1111 of stacked memory device 1100 and/or to receive signals from physical layer PHY 1111 of stacked memory device 1100. For example, physical layer PHY 1210 may include and/or may be similar in many respects to elements of at least one of memory controller 100 of fig. 1 and memory controller 300 of fig. 2. The SoC 1200 can provide various signals to the physical layer PHY 1111 through the physical layer PHY 1210. Signals provided to the physical layer PHY 1111 may be transferred to the core dies 1120-1150 through the TSV 1101 and the interface circuitry of the physical layer PHY 1111.

The middle layer 1300 may connect the stacked memory device 1100 to the SoC 1200. Middle layer 1300 may be connected between physical layer PHY 1111 of stacked memory device 1100 and physical layer PHY 1210 of SoC 1200. For example, the intermediate layer 1300 provides a physical path formed using a conductive material. Accordingly, the stacked memory device 1100 and the SoC 1200 may be stacked on the middle layer 1300 to send and/or receive signals to each other.

Bumps 1103 may be attached to the upper portion of package substrate 1400. Alternatively or additionally, solder balls 1104 may be attached to lower portions of the package substrate 1400. For example, bump 1103 may be a flip chip bump. The intermediate layer 1300 may be stacked on the package substrate 1400 through the bump 1103. The semiconductor package 1000 may transmit and/or receive signals to and/or from other external packages and/or semiconductor devices through the solder balls 1104. For example, the package substrate 1400 may be a Printed Circuit Board (PCB).

In one embodiment, the physical layer PHY 1111 of the buffer die 1110 may receive the write data strobe signal WDQS and/or the data signal DQ from the SoC 1200 through the bump 1102. As described with reference to fig. 1-9, the physical layer PHY 1111 may sample the data signal DQ based on the write data strobe signal WDQS having a coefficient code that may be an adjusted delay.

Fig. 11 is a diagram showing an example of implementation of a semiconductor package according to an embodiment.

Referring to fig. 11, a semiconductor package 2000 may include a plurality of stacked memory devices 2100 and socs 2200. Each of the stacked memory devices 2100 may include and/or may be similar in many respects to the stacked memory device 1100 of fig. 10, and may include additional features not mentioned above. The SoC2200 may include and/or may be similar in many respects to the SoC 1200 of fig. 10, and may include additional features not mentioned above. The stacked memory device 2100 and the SoC2200 may be stacked on the intermediate layer 2300, and the intermediate layer 2300 may be stacked on the package substrate 2400. The semiconductor package 2000 may transmit and/or receive signals to and/or from other external packages and/or semiconductor devices through the solder balls 2001 attached to the lower portion of the package substrate 2400.

For example, each of the stacked memory devices 2100 may be implemented based on the HBM standard. However, the present disclosure is not limited thereto, and each of the stacked memory devices 2100 may be implemented based on a Graphics Double Data Rate (GDDR) standard, an HMC standard, and/or a Wide (Wide) I/O standard.

The SoC 2200 may include at least one processor (such as, but not limited to, CPU, AP, GPU or NPU). Alternatively or additionally, soC 2200 may include a plurality of memory controllers for controlling a plurality of stacked memory devices 2100. That is, the SoC 2200 may send signals to and/or receive signals from the corresponding stacked memory device 2100 through the plurality of memory controllers.

While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims (20)

1. A memory device, comprising:

a data sampler configured to: sampling a data signal from the memory controller based on a write data strobe signal from the memory controller;

measurement circuitry configured to: measuring a temperature-based delay variation based on a temperature of a transfer path of the write data strobe signal, and measuring a voltage-based delay variation based on a voltage on the transfer path of the write data strobe signal;

a storage circuit configured to: storing a first coefficient code that adjusts a reference-based delay variation on a transfer path of the write data strobe signal based on a temperature change;

A temperature sensor configured to: sensing a temperature of a transfer path of the write data strobe signal;

monitoring circuitry configured to: generating a second coefficient code by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other;

a reference voltage generator configured to: generating a reference voltage from the supply voltage based on the second coefficient code;

a voltage regulator configured to: generating a regulated voltage based on the reference voltage; and

a write data strobe signal transfer circuit configured to: the write data strobe signal is transferred to the data sampler by using the regulated voltage.

2. The memory device of claim 1, further comprising:

a first pin configured to receive a data signal from a memory controller; and

a second pin configured to receive a write data strobe signal from the memory controller,

wherein a data signal path corresponding to a first path of the data signal from the first pin to the data sampler is different from a transfer path corresponding to a second path of the write data strobe signal from the second pin to the data sampler.

3. The memory device of claim 1, wherein the write data strobe signal transfer circuit is further configured to:

The write data strobe signal is transferred to the data sampler based on a delay corresponding to the second coefficient code.

4. The memory device of claim 1, wherein the write data strobe signal transfer circuit is configured to:

the write data strobe signal is transferred to the data sampler by using the regulated voltage.

5. The memory device of claim 1, wherein the monitor circuit is further configured to:

the second coefficient code is generated based on matching a ratio obtained by dividing the temperature-based delay variation by the voltage-based delay variation with the reference-based delay variation.

6. The memory device of claim 1, wherein the reference-based delay variation is a low voltage drop reference voltage variation of the memory device based on a temperature variation.

7. The memory device of claim 6, wherein the monitor circuit is further configured to:

the reference-based delay variation is adjusted based on the second coefficient code.

8. The memory device of claim 1, wherein the monitor circuit is further configured to:

a second coefficient code is generated based on a change in the write data strobe signal and a change in temperature of the memory device.

9. The memory device of claim 8, wherein the monitor circuit is further configured to:

a second series code is generated based on a coefficient code enable command from the memory controller.

10. The memory device of any one of claims 1 to 9, wherein the memory device further comprises:

a mode register configured to: the second coefficient code is stored based on a mode register set command from the memory controller.

11. A method of operation of a memory device, comprising:

sampling a data signal from the memory controller based on a write data strobe signal from the memory controller;

measuring a temperature-based delay variation based on a temperature of a transfer path of the write data strobe signal;

measuring a voltage-based delay variation based on a voltage on a transfer path of the write data strobe signal;

generating a reference-based delay variation based on the first coefficient code and the temperature change of the memory device;

generating a second coefficient code, the second coefficient code being determined by comparing the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other; and

The data signal is sampled by adjusting a delay on a transfer path of the write data strobe signal based on the temperature change of the memory device and the second coefficient code.

12. The method of operation of claim 11, wherein the step of sampling the data signal comprises:

sensing a temperature of the memory device;

generating a reference voltage from the supply voltage based on the second coefficient code; and

a regulated voltage is generated based on the reference voltage.

13. The method of operation of claim 11, wherein generating the second coefficient code comprises:

the second coefficient code is generated based on matching a ratio obtained by dividing the temperature-based delay variation by the voltage-based delay variation with the reference-based delay variation.

14. The method of operation of claim 13, further comprising:

when a ratio obtained by dividing the temperature-based delay variation by the voltage-based delay variation does not match the reference-based delay variation, the reference-based delay variation is controlled by adjusting the first coefficient code.

15. The method of operation of any of claims 11 to 14, wherein generating a reference-based delay variation comprises:

In response to a coefficient code enable command from the memory controller.

16. The method of operation of claim 15, wherein:

the reference-based delay variation is a low voltage drop reference voltage variation of the memory device based on temperature variation, and

the operation method further comprises the following steps: the reference-based delay variation is adjusted based on the second coefficient code.

17. A memory system, comprising:

a memory device configured to: monitoring a temperature-based delay variation based on temperature, monitoring a voltage-based delay variation based on voltage, and monitoring a reference-based delay variation with respect to a write data strobe signal used to sample a data signal; and

a memory controller configured to: a first coefficient code for adjusting the reference-based delay variation is determined,

wherein the memory device is further configured to:

comparing the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other;

adjusting a delay on a transfer path of the write data strobe signal based on a temperature change of the memory device; and

the data signal is sampled.

18. The memory system of claim 17, the memory device comprising:

A data sampler configured to: sampling the data signal based on the write data strobe signal;

measurement circuitry configured to: measuring a temperature-based delay variation based on a temperature of a transfer path of the write data strobe signal, and measuring a voltage-based delay variation based on a voltage on the transfer path of the write data strobe signal;

a storage circuit configured to: storing a first coefficient code for adjusting a reference-based delay variation on a transmission path of the write data strobe signal based on a temperature change;

a temperature sensor configured to: sensing a temperature of a transfer path of the write data strobe signal;

monitoring circuitry configured to: generating a second coefficient code by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other;

a reference voltage generator configured to: generating a reference voltage from the supply voltage based on the second coefficient code;

a voltage regulator configured to: generating a regulated voltage based on the reference voltage; and

a write data strobe signal transfer circuit configured to: the write data strobe signal is transferred to the data sampler by using the regulated voltage.

19. The memory system of claim 18, wherein the monitor circuit is further configured to:

the second coefficient code is generated based on matching a ratio obtained by dividing the temperature-based delay variation by the voltage-based delay variation with the reference-based delay variation.

20. The memory system of claim 18, wherein the memory device further comprises:

a mode register configured to: the second coefficient code is stored based on a mode register set command from the memory controller.