CN114530172A

CN114530172A - Semiconductor memory device and memory system including the same

Info

Publication number: CN114530172A
Application number: CN202111397188.4A
Authority: CN
Inventors: 徐廷硕; 金光贤; 金治国; 柳承佑; 黄斗熙
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2020-11-23
Filing date: 2021-11-23
Publication date: 2022-05-24
Also published as: KR20220070643A; US20220165321A1; US11495280B2

Abstract

Provided are a semiconductor memory device and a memory system including the same. A semiconductor memory device includes: an external resistor disposed on the board; and a plurality of memory dies mounted on the board and designated as a master die and a slave die. The memory chips are commonly connected to an external resistor. The main chip performs a first impedance calibration operation during an initialization sequence of the semiconductor memory device, and stores first calibration data, a first voltage, and a first temperature in a first register set therein. After the first impedance calibration operation is completed, during an initialization sequence, each of the plurality of slave wafers performs a second impedance calibration operation, and second calibration data associated with the second impedance calibration operation and deviation data corresponding to a difference between the first calibration data and the second calibration data are stored in a second register set therein.

Description

Semiconductor memory device and memory system including the same

Cross Reference to Related Applications

This application claims priority from korean patent application No.10-2020-0157389, filed by the korean intellectual property office on 11/23/2020, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Example embodiments described herein relate to a memory device, and more particularly, to a semiconductor memory device including multiple chips and a memory system including the semiconductor memory device.

Background

As the operating speed of the semiconductor memory device increases, the swing width of signals of an interface between the semiconductor memory device and the memory controller generally decreases. However, as the swing width decreases, signals transmitted between the semiconductor memory device and the memory controller may be more susceptible to distortion due to impedance mismatch caused by process, voltage, and temperature (PVT) variations. An impedance calibration operation for adjusting an output impedance and/or a termination impedance of a semiconductor memory device may be used for a transmitting stage and/or a receiving stage of the semiconductor memory device. The impedance calibration operation may be referred to as an input/output (I/O) offset cancellation operation or a ZQ calibration operation.

Disclosure of Invention

According to some example embodiments, a semiconductor memory device includes an external resistor disposed on a board and a plurality of memory dies mounted on the board. The memory dies are commonly connected to an external resistor, one of the memory dies is designated as a master die, and the remaining memory dies other than the master die are designated as a plurality of slave dies. The main chip performing a first impedance calibration operation in response to a first impedance calibration command during an initialization sequence of the semiconductor memory device to determine a resistance of the first output driver and a first reference output high level (VOH) voltage of the first output driver; and a first set of registers therein stores first calibration data, a first voltage, and a first temperature associated with a first impedance calibration operation. After the first impedance calibration operation is completed, during an initialization sequence, each of the plurality of slave dies performs a second impedance calibration operation in response to the first impedance calibration command to determine a resistance of the second output driver and a second reference VOH voltage of the second output driver; and a second set of registers therein storing second calibration data associated with the second impedance calibration operation and deviation data corresponding to a difference between the first calibration data and the second calibration data.

According to some example embodiments, a memory system includes: a semiconductor memory device including a plurality of memory dies; and a memory controller that controls the semiconductor memory device. The semiconductor memory device includes an external resistor disposed on a board and a plurality of memory chips mounted on the board. The memory dies are commonly connected to an external resistor, one of the memory dies is designated as a master die, and the remaining memory dies other than the master die are designated as a plurality of slave dies. During an initialization sequence of the semiconductor memory device, the main chip performs a first impedance calibration operation in response to an impedance calibration command to determine a resistance of the first output driver and a first reference output high level (VOH) voltage of the first output driver; and a first set of registers therein stores first calibration data, a first voltage, and a first temperature associated with a first impedance calibration operation. After the first impedance calibration operation is completed, during an initialization sequence, each of the slave wafers performs a second impedance calibration operation in response to the impedance calibration command to determine a resistance of the second output driver and a second reference VOH voltage of the second output driver; and a second set of registers therein storing second calibration data associated with the second impedance calibration operation and deviation data corresponding to a difference between the first calibration data and the second calibration data.

According to some example embodiments, a semiconductor memory device includes: an external resistor disposed on the board and a plurality of memory dies mounted on the board. The memory dies are commonly connected to an external resistor, one of the memory dies is designated as a master die, and the remaining memory dies other than the master die are designated as a plurality of slave dies. The main chip performing a first impedance calibration operation in response to an impedance calibration command during an initialization sequence of the semiconductor memory device to determine a resistance of the first output driver and a first reference output high level (VOH) voltage of the first output driver; and storing, in a first set of registers therein, first calibration data, a first voltage, and a first temperature associated with a first impedance calibration operation. After the first impedance calibration operation is completed, during an initialization sequence, each of the slave wafers performs a second impedance calibration operation in response to the impedance calibration command to determine a resistance of the second output driver and a second reference VOH voltage of the second output driver; and storing, in a second register set therein, second calibration data associated with the second impedance calibration operation and deviation data corresponding to a difference between the first calibration data and the second calibration data, and updating, during an idle period of the semiconductor memory device, the second calibration data stored in the second register set by a difference indicated by the deviation data in response to a calibration trigger signal irregularly supplied from the main wafer based on a detection signal associated with an operating voltage and an operating temperature of the semiconductor memory device.

Thus, during the initialization sequence, the second calibration data and deviation data corresponding to the difference between the first calibration data and the second calibration data are stored in each of the second set of registers from each of the wafers. The second calibration data is updated from each of the wafers based on the deviation data without performing an additional impedance calibration operation. Accordingly, each of the slave wafers may reduce the interval corresponding to the background impedance calibration interval during the idle period.

Drawings

The above and other features of the present disclosure will be more clearly understood by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

FIG. 1 is a block diagram illustrating a memory system according to an example embodiment.

Fig. 2 is a block diagram illustrating an example of a host die in the semiconductor memory device in fig. 1 according to an example embodiment.

FIG. 3 illustrates a first array of memory banks in the main die of FIG. 2, according to an example embodiment.

FIG. 4 illustrates data I/O circuitry in the host die of FIG. 2 according to an example embodiment.

Fig. 5 illustrates a circuit diagram of an output driver in the data I/O circuit of fig. 4 according to an example embodiment.

Fig. 6 illustrates a diagram for explaining an operation of the data output circuit in fig. 5 according to an example embodiment.

Fig. 7 shows a block diagram of an impedance calibration circuit in the main wafer of fig. 2 according to an example embodiment.

Fig. 8 shows a block diagram of a calibration circuit in the impedance calibration circuit of fig. 7 according to an example embodiment.

Fig. 9 shows a block diagram of an impedance calibration circuit in the slave wafer of fig. 2 according to an example embodiment.

Fig. 10 shows an example of a first set of registers in the impedance calibration circuit in the host wafer in fig. 7.

Fig. 11 shows an example of a second set of registers in the impedance calibration circuit in the slave wafer of fig. 9.

Fig. 12 shows an example of a second set of registers in the impedance calibration circuit in the slave wafer of fig. 9.

Fig. 13 and 14 illustrate impedance calibration operations performed during an initialization sequence in the semiconductor memory device in fig. 1 according to example embodiments.

Fig. 15 illustrates a background impedance calibration operation performed during an idle period in the semiconductor memory device in fig. 1 according to an example embodiment.

Fig. 16A and 16B are flowcharts illustrating a method of operating a semiconductor memory device including a multi-chip according to example embodiments.

Fig. 17 is a flowchart illustrating a method of operating a semiconductor memory device including a multi-chip according to an example embodiment.

Fig. 18 is a schematic diagram of a multi-chip package including a semiconductor memory device according to an example embodiment.

Fig. 19 is a block diagram illustrating a semiconductor memory device according to an example embodiment.

Fig. 20 is a configuration diagram illustrating a semiconductor package including a stacked memory device according to an example embodiment.

Detailed Description

Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. In the present application, like reference numerals may refer to like elements.

Referring to fig. 1, a memory system 20 may include a memory controller 30 and a semiconductor memory device 100. The semiconductor memory device 100 includes a plurality of memory dies 200a to 200k, where k is an integer greater than two. In example embodiments, each of the memory dies 200a to 200k may be referred to as a memory chip. One of the memory dies 200 a-200 k (e.g., memory die 200a) may be designated as a master die, while the remaining memory dies of the memory dies 200 a-200 k (e.g., memory dies 200 b-200 k) other than memory die 200a may be designated as a plurality of slave dies.

The memory controller 30 may control the overall operation of the memory system 20. The memory controller 30 may control overall data exchange between an external host and the plurality of memory dies 200a to 200 k. For example, the memory controller 30 may write data into the plurality of memory dies 200a to 200k or read data from the plurality of memory dies 200a to 200k in response to a request of a host. In addition, the memory controller 30 may issue an operation command to the plurality of memory dies 200a to 200k to control the plurality of memory dies 200a to 200 k.

The memory controller 30 transmits control signals such as a clock signal CLK, a command CMD, an address ADDR, and a data signal DQ to the memory chips 200a to 200 k. The memory controller 30 also receives data signals DQ from the memory chips 200a to 200 k. Although not shown, the memory controller 30 may transmit data strobe signals and data signals DQ to the memory dies 200a to 200k, and may receive data strobe signals and data signals DQ from the memory dies 200a to 200 k. The memory controller 30 may send a write command, a read command, and an impedance calibration command to each of the memory dies 200a to 200 k. Each of the memory dies 200a to 200k may perform a write operation in response to a write command, a read operation in response to a read command, and an impedance calibration operation in response to an impedance calibration command.

In an example embodiment, each of the plurality of memory dies 200 a-200 k may be a Dynamic Random Access Memory (DRAM), such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), and so forth.

The memory chips 200a to 200k may be commonly connected to an external resistor RZQ provided (formed) in the board 110. The external resistor RZQ may be connected to the power supply voltage VDDQ. In an example embodiment, the external resistor RZQ may be connected to a ground voltage.

The semiconductor memory device 100 may also include a Power Management Integrated Circuit (PMIC)130 and a voltage/temperature (VT) sensor 140.

The PMIC 130 may generate an operating voltage VDD based on an input voltage (not shown) from the memory controller 30 and may provide the operating voltage VDD to the memory dies 200a to 200 k. The voltage/temperature sensor 140 may sense the level of the operating voltage VDD and the operating temperature of the semiconductor memory apparatus 100 and provide the main wafer 200a with a detection signal DS that is activated when the level of the operating voltage VDD and the operating temperature change beyond a reference range. In the idle mode of the semiconductor memory apparatus 100, when the level of the operating voltage VDD and the change of the operating temperature exceed the reference range within a certain time interval, the voltage/temperature sensor 140 may not activate the detection signal DS to prevent the impedance calibration operation from being frequently performed near the reference range.

The memory controller 30 may include a Central Processing Unit (CPU)40 to control the operation of the memory controller 30.

During an initialization sequence in which power is supplied to the semiconductor memory device 100, each of the plurality of memory dies 200a to 200k may perform an impedance calibration operation in response to a first impedance calibration command from the memory controller 30.

During an initialization sequence, the main die 200a may perform a first impedance calibration operation in response to a first impedance calibration command to determine a resistance of the first output driver and a first reference output high level (VOH) voltage of the first output driver, and may store first calibration data, a first voltage, and a first temperature associated with the first impedance calibration operation in a first set of registers therein.

During the initialization sequence, after the first impedance calibration operation is completed, each of the slave wafers 200b to 200k may perform a second impedance calibration operation in response to the first impedance calibration command to determine a resistance of the second output driver and a second reference VOH voltage of the second output driver, and may store second calibration data associated with the second impedance calibration operation and deviation data corresponding to a difference between the first calibration data and the second calibration data in a second register set therein.

In addition, during the idle period of the semiconductor memory apparatus 100, the master die 200 may compare the first voltage and the first temperature with the second voltage and the second temperature of the semiconductor memory apparatus 100 on an irregular basis based on the detection signal DS associated with the operating voltage and the operating temperature of the semiconductor memory apparatus 100, the master die 200 may perform the background impedance calibration operation when a first difference between the second voltage and the first voltage and a second difference between the second temperature and the first temperature exceed a reference range, may store third calibration data, the second voltage, and the second temperature associated with the background impedance calibration operation in the first register set, and may provide the calibration trigger signal associated with the background impedance calibration operation to the slave dies 200b to 200 k. The calibration trigger signal may indicate that a background impedance calibration operation is performed.

In addition, during an idle period, after the background impedance calibration operation is completed, each of the slave wafers 200b to 200k may update the second calibration data stored in the second register set by a difference indicated by the deviation data in response to the calibration trigger signal.

Referring to FIG. 2, the main die 200a may include control logic circuitry 210, address register 220, bank control logic 230, row address multiplexer (RA MUX)240, refresh counter 245, Column Address (CA) latch 250, row decoder 260, column decoder 270, sense amplifier unit 285, I/O gating circuitry 290, memory cell array 300, data I/O circuitry 320, Error Correction Code (ECC) engine 390, and impedance (ZQ) calibration circuitry 400.

The memory cell array 300 may include first to eighth memory bank arrays 310a to 310h, the row decoder 260 may include first to eighth row decoders 260a to 260h coupled to the first to eighth memory bank arrays 310a to 310h, respectively, the column decoder 270 may include first to eighth column decoders 270a to 270h coupled to the first to eighth memory bank arrays 310a to 310h, respectively, and the sense amplifier unit 285 may include first to eighth sense amplifiers 285a to 285h coupled to the first to eighth memory bank arrays 310a to 310h, respectively.

The first to eighth memory bank arrays 310a to 310h, the first to eighth row decoders 260a to 260h, the first to eighth column decoders 270a to 270h, and the first to eighth sense amplifiers 285a to 285h may form first to eighth memory banks. Each of the first through eighth bank arrays 310a through 310h may include a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BL.

The address register 220 may receive an address ADDR including a BANK address BANK _ ADDR, a ROW address ROW _ ADDR, and a column address COL _ ADDR from the memory controller 30. The address register 220 may provide a received BANK address BANK ADDR to the BANK control logic 230, a received ROW address ROW ADDR to the ROW address multiplexer 240, and a received column address COL _ ADDR to the column address latch 250.

The BANK control logic 230 may generate a BANK control signal in response to the BANK address BANK ADDR. One of the first to eighth row decoders 260a to 260h corresponding to the BANK address BANK _ ADDR may be activated in response to a BANK control signal, and one of the first to eighth column decoders 270a to 270h corresponding to the BANK address BANK _ ADDR may be activated in response to a BANK control signal.

The ROW address multiplexer 240 may receive a ROW address ROW _ ADDR from the address register 220 and may receive a refresh ROW address REF _ ADDR from the refresh counter 245. The ROW address multiplexer 240 may selectively output a ROW address ROW _ ADDR or a refresh ROW address REF _ ADDR as the ROW address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth row decoders 260a to 260 h.

The refresh counter 245 may sequentially increase or decrease the refresh row address REF _ ADDR under the control of the control logic circuit 210.

The activated one of the first to eighth row decoders 260a to 260h (activated by the bank control logic 230) may decode the row address RA output from the row address multiplexer 240 and activate a word line corresponding to the row address RA. For example, the activated row decoder may apply a word line driving voltage to a word line corresponding to a row address.

The column address latch 250 may receive a column address COL _ ADDR from the address register 220 and temporarily store the received column address COL _ ADDR. In some example embodiments, the column address latch 250 may generate a column address added from the received column address COL _ ADDR in the burst mode. The column address latch 250 may apply the temporarily stored or generated column address to the first to eighth column decoders 270a to 270 h.

An activated one of the first through eighth column decoders 270a through 270h may activate sense amplifiers corresponding to the BANK address BANK _ ADDR and the column address COL _ ADDR through the I/O gating circuit 290.

The I/O gating circuit 290 may include a circuit for gating input/output data, and may further include input data mask logic, read data latches for storing data output from the first through eighth bank arrays 310a through 310h, and write drivers for writing data to the first through eighth bank arrays 310a through 310 h.

The codeword CW read from one of the first through eighth bank arrays 310a through 310h may be sensed through a sense amplifier coupled to the one bank array from which data is to be read, and may be stored in a read data latch. The codeword CW stored in the read data latch may be provided to the memory controller 30 via the data I/O circuit 320 after ECC decoding is performed on the codeword CW by the ECC engine 390.

The data signal DQ to be written into one of the first through eighth bank arrays 310a through 310h may be provided from the memory controller 30 to the data I/O circuit 320. The data I/O circuit 320 may provide data DTA to the ECC engine 390 based on the data signal DQ. The ECC engine 390 may perform ECC encoding on the data DTA to generate parity bits, the ECC engine 390 may provide the data DTA and the parity bits to the I/O gating circuit 290, and the I/O gating circuit 290 may write the data DTA and the parity bits in a sub-page in one bank array through a write driver.

The data I/O circuit 320 may receive a clock signal CLK and a data signal DQ in a write operation. In a write operation, the data I/O circuit 320 may drive bits of the data DTA based on the pull-up control code PUCD and the pull-down control code PDCD from the impedance calibration circuit 400 to generate the data signal DQ having the target VOH level and supply the data signal DQ to the memory controller 30 through the data I/O pad 301.

The ECC engine 390 may perform ECC encoding on the data DTA based on the second control signal CTL2 from the control logic circuit 210.

The impedance calibration circuit 400 may be connected to an external resistor RZQ, which may be connected to the power supply voltage VDDQ, through an impedance (ZQ) pad 401 a. In an example embodiment, the external resistor RZQ may be connected to a ground voltage. In addition, the impedance calibration circuit 400 may be connected to the slave wafers 200b to 200k through the connection pad 402 a.

Control logic 210 may control the operation of master die 200 a. For example, the control logic 210 may generate control signals for the main wafer 200a to perform a write operation, a read operation, or an impedance calibration operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 30, and may include a mode register 212 that sets an operation mode of the main die 200 a.

The command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, and the like. The control logic circuit 210 may generate a first control signal CTL1 to control the I/O gating circuit 290, may generate a second control signal CTL2 to control the ECC engine 390, and may generate a mode register set signal MRS to control the impedance calibration circuit 400. The mode register set signal MRS may include an impedance calibration command ZQ _ CAL.

The configuration of each of the slave wafers 200b to 200k may be substantially the same as or similar to the configuration of the master wafer 200a of fig. 2.

Referring to fig. 3, the first bank array 310a may include a plurality of word lines WL1, WL2, WL2m-1, and WL2m (e.g., WL1 to WL2m) (where m is a natural number greater than 2), a plurality of bit lines BL1, BL2, BL2n-1, and BL2n (e.g., BL1 to BL2n) (where n is a natural number greater than 2), and a plurality of memory cells MC disposed near intersections between the word lines WL1 to WL2m and the bit lines BL1 to BL2 n. In an example embodiment, each of the plurality of memory cells MC may include a Dynamic Random Access Memory (DRAM) cell structure. The plurality of word lines WL1 to WL2m connecting the plurality of memory cells MC may be referred to as a row of the first memory bank array 310a, and the plurality of bit lines BL1 to BL2n connecting the plurality of memory cells MC may be referred to as a column of the first memory bank array 310 a.

Referring to fig. 4, the data I/O circuit 320 may include a data input circuit 330 and a data output circuit 340. The data output circuit 340 may include a pre-driver 350 and an output driver 360.

The data input circuit 330 may receive a data signal DQ from the memory controller 30, may convert the data signal DQ into data DTA, and may provide the data DTA to the ECC engine 390. The data output circuit 340 may convert the data DTA from the ECC engine 390 into a data signal DQ, and may provide the data signal DQ to the memory controller 30.

The pre-driver 350 may receive the data DTA, may generate a pull-up driving signal PUDS and a pull-down driving signal PDDS based on the pull-up control code PUCD and the pull-down control code PDCD, and may provide the pull-up driving signal PUDS and the pull-down driving signal PDDS to the output driver 360.

For example, when the data DTA is at a high level, the pre-driver 350 may buffer the pull-up control code PUCD and generate a pull-up driving signal PUDS that is substantially the same as the pull-up control code PUCD, and may generate a pull-down driving signal PDDS for turning off all transistors included in a pull-down driver (such as the pull-down driver 363 shown in fig. 5) of the output driver 360. Conversely, when the data DTA is at a low level, the pre-driver 350 may buffer the pull-down control code PDCD and generate a pull-down driving signal PDDS that is substantially the same as the pull-down control code PDCD and generate a pull-up driving signal PUDS for turning off all transistors included in a pull-up driver (such as the pull-up driver 361 shown in fig. 5) of the output driver 360. When the output driver 360 outputs the data signal DQ, the pre-driver 350 may determine the current generated by the pull-up driver 361 and the resistance of the pull-down driver 363 (shown in fig. 5).

Referring to fig. 5, the output driver 360 may include a pull-up driver 361 and a pull-down driver 363.

The pull-up driver 361 may include first through r (r is a natural number greater than 1) th pull-up transistors NU1 through NUr connected between a power supply voltage VDDQ and an output node ON 1. Each of the first pull-up transistor NU1 through the r pull-up transistor NUr may be an n-channel metal oxide semiconductor (NMOS) transistor.

The pull-down driver 363 may include first to nth pull-down transistors ND1 to NDr connected between an output node ON1 and a ground voltage VSS. Each of the first to nth pull-down transistors ND1 to NDr may be an NMOS transistor.

When the data DTA is at a high level, the pull-up driver 361 may receive the pull-up driving signals PUDS (e.g., PUDS [1] to PUDS [ r ]) corresponding to the pull-up control codes PUCD from the pre-driver 350 and generate currents determined by the pull-up control codes PUCD. The pull-down transistors ND1 through NDr included in the pull-down driver 363 may be all turned off according to the pull-down driving signal PDDS (e.g., PDDS [1] through PDDS [ r ]).

When the data DTA is at a high level, a current generated by the pull-up driver 361 may be transferred to an on-die termination (ODT) resistor RODT _ MC in the memory controller 30 via a data I/O (or DQ) pad 301. The data signal DQ received by the ODT resistor RODT _ MC is determined by the current generated by the pull-up driver 361 and the ODT resistor RODT _ MC, and has a target VOH voltage adjusted according to the pull-up control code PUCD generated by the impedance calibration circuit 400.

When the data DTA is at a low level, the pull-up transistors NU1 through Nur included in the pull-up driver 361 may be all turned off according to the pull-up driving signal PUDS. The pull-down driver 363 may receive the pull-down driving signal PDDS corresponding to the pull-down control code PDCD from the pre-driver 330, and may have a resistance determined by the pull-down control code PDCD.

When the data DTA is at a low level, the pull-up driver 361 generates no current, and thus, the data signal DQ received by the ODT resistor RODT _ MC has an output low-level Voltage (VOL) voltage substantially the same as the ground voltage VSS.

According to example embodiments, the total resistance (e.g., termination Resistance (RTT)) of the pull-up driver 361 or the pull-down driver 363 may be changed in response to a specific pull-up driving signal PUDS or pull-down driving signal PDDS. By changing the number of memory modules inserted into the memory slot, a single load or a double load can be realized, and an RTT suitable for the condition can be selected.

Referring to fig. 6, the data signal DQ may have a high level or a low level according to the data DTA. The data signal DQ is an Alternating Current (AC) signal that swings between VOH and VOL.

The memory controller 30 may receive the data signal DQ from each of the memory dies 200a to 200k, determine the VOH voltage and the VOL voltage, and determine the reference voltage VREF according to the VOH voltage and the VOL voltage. The memory controller 30 may compare the data signal DQ with the reference voltage VREF and determine a received data value (e.g., 0 or 1).

Various process-voltage-temperature (PVT) conditions may be applied to each of the memory wafers 200 a-200 k. PVT conditions may include non-uniform doping in the wafer process, voltage drops as current passes through different elements when power is supplied, and temperature along the path of the signal. The AC on-resistances (hereinafter, referred to as "Ron AC") of the output sides of the memory chips 200a to 200k may vary with the PVT conditions, and the VOH voltage of the data signal DQ may vary with the Ron AC.

Various operating frequencies may be applied to each of the memory dies 200a to 200 k. When the operating frequency is changed, the VOH voltage of the data signal DQ may be changed. Accordingly, the signal integrity of each of the memory dies 200a to 200k can be improved by generating the pull-up control code PUCD and the pull-down control code PDCD according to the PVT conditions (e.g., operating parameters) and the operating frequency so that the data signal DQ has the optimum VOH voltage.

The impedance calibration circuit 400 may generate a pull-up control code PUCD and a pull-down control code PDCD for a target VOH voltage, and store the pull-up control code PUCD and the pull-down control code PDCD in a first register set therein in response to the mode register set signal MRS during an impedance calibration interval.

During the normal operation period, the impedance calibration circuit 400 may provide the pull-up control code PUCD and the pull-down control code PDCD for the target VOH voltage to the data output circuit 340, and the data output circuit 340 may transmit the data signal DQ to the memory controller 30 based on the pull-up control code PUCD and the pull-down control code PDCD. The mode register set signal MRS may include information on the impedance of the ODT resistor RODT _ MC of the memory controller 30 and may include information indicating whether to increase or decrease the VOH voltage of the data signal DQ. The mode register set signal MRS may include an impedance calibration command ZQ _ CAL.

Referring to fig. 7, the impedance calibration circuit 400 may include a calibration (ZQ) controller 405, a calibration circuit 420, a Target Voltage Generator (TVG)410, and a first set of registers (register set) 480.

The calibration controller 405 may receive the impedance calibration command ZQ _ CAL from a Command Decoder (CD) (i.e., corresponding command decoder) 211 in the main die 200 a.

The calibration circuit 420 may be connected to the external resistor RZQ through the impedance pad 401a, may perform an impedance calibration operation in response to a calibration enable signal ZQEN1 from the calibration controller 405 to provide the first pull-up control code PUCD1 and the first pull-down control code PDCD1 to the output driver 360, may store the first pull-up control code PUCD1 and the first pull-down control code PDCD1 as first calibration data in the first register set 480, and may provide the first comparison signal CS11 and the second comparison signal CS12 indicating that the impedance calibration operation has been completed to the calibration controller 405. The calibration circuit 420 may perform impedance calibration operations for various operating voltages and operating temperatures.

The target voltage generator 410 may generate a target VOH voltage (hereinafter, also referred to as "VTG 1") in response to the calibration enable signal ZQEN1, and may provide the target VOH voltage VTG1 to the calibration circuit 420.

The first register set 480 may be connected to the slave wafers 200b to 200k through the first connection pad 402a, may store the first pull-up control code PUCD1 and the first pull-down control code PDCD1, and may store the voltage data VD and the temperature data TD associated with the impedance calibration operation.

Calibration controller 405 may include a timer 407, a Comparator (COMP)409, and logic 408. The calibration controller 405 may receive a voltage signal VS representing an operating voltage in the impedance calibration operation and a temperature signal TS representing an operating temperature in the impedance calibration operation, and may store the voltage signal VS and the temperature signal TS as voltage data VD and temperature data TD, respectively, in the first register set 480.

The timer 407 may activate the calibration enable signal ZQEN1 during an impedance calibration period determined according to the specification of the semiconductor memory device 100 in response to the impedance calibration command ZQ _ CAL. In addition, timer 407 may generate a periodically activated interval signal ITS during an idle period and may provide interval signal ITS to logic 408.

During idle periods, when the calibration controller 405 receives the voltage signal VS and the temperature signal TS, the comparator 409 may compare the voltage signal VS (second voltage) and the temperature signal TS (second temperature) with the voltage data VD and the temperature data TD previously stored in the first register set 480, may activate the calibration enable signal ZQEN1 when a first difference between the voltage signal VS and the voltage data VD and a second difference between the temperature signal TS and the temperature data TD exceed a reference range, and may provide the comparison signal CPS indicating the first difference and the second difference to the logic 408. During idle periods, the calibration circuit 420 may perform a background impedance calibration operation in response to the activated calibration enable signal ZQEN1, and may store third calibration data, a second voltage, and a second temperature associated with the background impedance calibration operation in the first set of registers 480.

Logic 408 may receive interval signal ITS and comparison signal CPS and may provide calibration trigger signal ZQTRG to slave dies 200b through 200k through signal pad 403a when comparison signal CPS indicates that the first difference and the second difference are outside of the reference range.

Referring to fig. 8, the calibration circuit 420 includes a pull-up (PU) driver 421, a first code generator 430, a first code storage circuit (code storage circuit) 440, a pull-down (PD) driver 451, a replica pull-down (PD) driver 453, a second code generator 460, and a second code storage circuit (code storage circuit) 470.

The pull-up driver 421 is connected between the power supply voltage VDDQ and the first node N11, and may have a similar configuration as the pull-up driver 361 in fig. 5. The replica pull-down driver 453 is connected between the first node N11 and the ground voltage VSS, and may have a configuration similar to the pull-down driver 363 in fig. 5. The pull-down driver 451 is connected between a second node N12 and a ground voltage VSS, and the second node N12 is connected with the impedance pad 401 coupled to the external resistor RZQ. The pull-down driver 451 may have a configuration similar to the pull-down driver 363 in fig. 5.

The first code generator 430 may generate a first pull-up control code PUCD1 obtained according to a result of comparing the first target VOH voltage VTG1 with the first voltage (or pull-up voltage) VPU of the first node N11. The first code generator 430 includes a first comparator 431 and a first counter (counter) 433.

The first comparator 431 may compare the first target VOH voltage VTG1 with the first voltage VPU to output a first comparison signal CS11 in response to the calibration enable signal ZQEN1 being enabled, and may provide the first comparison signal CS11 to the first counter 433 and the first code storage circuit 440. The first counter 433 may perform a counting operation in response to the first comparison signal CS11 to generate the first pull-up control code PUCD1, and may perform a counting operation to increase or decrease the first pull-up control code PUCD1 before a logic level transition of the first comparison signal CS 11. The first counter 433 may provide the first pull-up control code PUCD1 to the pull-up driver 421 and the first code storage circuit 440.

The pull-up driver 421 may adjust/calibrate the pull-up impedance in response to the first pull-up control code PUCD 1. The first pull-up control code PUCD1 may be calibrated/changed before the first target VOH voltage VTG1 becomes substantially the same as the pull-up voltage VPU.

When the logic level of the first comparison signal CS11 transitions, the first code storage circuit 440 may store the first pull-up control code PUCD 1. In other words, when the first target VOH voltage VTG1 becomes the pull-up voltage VPU, the first code storage circuit 440 may store the first pull-up control code PUCD 1.

The second code generator 460 may generate a first pull-down control code PDCD1 obtained from a result of comparing the second voltage (or pull-down voltage) VPD of the second node N12 with the reference voltage VREF. The second code generator 460 includes a second comparator 461 and a second counter (counter) 463. The second comparator 461 may compare the reference voltage VREF with the second voltage VPD to output a second comparison signal CS12 in response to the calibration enable signal ZQEN1 being enabled, and may provide the second comparison signal CS12 to the second counter 463 and the second code storage circuit 470.

The second counter 463 may perform a counting operation in response to the second comparison signal CS12 to generate the first pull-down control code PDCD1, and may perform a counting operation to increase or decrease the first pull-down control code PDCD1 before a logic level transition of the second comparison signal CS 12. The second counter 463 may provide the first pull-down control code PDCD1 to the pull-down driver 451, the replica pull-down driver 453, and the second code storage circuit 470.

The pull-down driver 451 may adjust/calibrate the pull-down impedance in response to the first pull-down control code PDCD 1. The replica pull-down driver 453 may adjust/calibrate the pull-down impedance in response to the first pull-down control code PDCD 1. The first pull-down control code PDCD1 may be calibrated/changed before the pull-down voltage VPD becomes substantially the same as the reference voltage VREF. When the logic level of the second comparison signal CS12 transitions, the second code storage circuit 470 may store the first pull-down control code PDCD 1. In other words, when the pull-down voltage VPD becomes the reference voltage VREF, the second code storage circuit 470 may store the first pull-down control code PDCD 1.

The calibration circuit 420 provides the first and second comparison signals CS11 and CS12 to the calibration controller 405.

Referring to fig. 9, the slave wafer 200b may include a Command Decoder (CD)211b and an impedance calibration circuit 400 b. The impedance calibration circuit 400b may include a calibration (ZQ) controller 405b, a calibration circuit 420b, a Target Voltage Generator (TVG)410b, a second set of registers (register set) 480b, a buffer 490b, and a calculator (CALC)495 b.

The calibration controller 405b may receive the impedance calibration command ZQ _ CAL from the command decoder (i.e., corresponding command decoder) 211b in the slave die 200 b. The calibration controller 405b may include a timer 407b, and the timer 407b may activate the calibration enable signal ZQEN2 at a timing according to a delay predetermined from an impedance calibration order of the wafer 200b, and may maintain the activated state of the calibration enable signal ZQEN2 during an impedance calibration period. In addition, during the idle period, the calibration controller 405b may receive the calibration trigger signal ZQTRG from the master wafer 200a through the signal pad 403b, may activate the calibration enable signal ZQEN2 at a timing delayed predetermined according to the impedance calibration order of the slave wafer 200b, and may maintain the state of activation of the calibration enable signal ZQEN2 during the impedance calibration period.

The calibration circuit 420b may be connected to the external resistor RZQ through the impedance pad 401b, may perform an impedance calibration operation in response to a calibration enable signal ZQEN2 from the calibration controller 405b to provide the second pull-up control code PUCD2 and the second pull-down control code PDCD2 to the output driver, may store the second pull-up control code PUCD2 and the second pull-down control code PDCD2 as second calibration data in the second register set 480b, and may provide the first comparison signal CS21 and the second comparison signal CS22 indicating that the impedance calibration operation is completed to the calibration controller 405 b. The target voltage generator 410b may generate a target VOH voltage VTG2 in response to the calibration enable signal ZQEN2, and may provide the target VOH voltage VTG2 to the calibration circuit 420 b.

The buffer 490b may receive the first calibration data (i.e., the first pull-up control code PUCD1 and the first pull-down control code PDCD1) from the first register set 480 through the connection pad 402b and may store the first calibration data. During idle periods, the calculator 495b may compare the second pull-up control code PUCD2 and the second pull-down control code PDCD2 with the first calibration data stored in the buffer 490b, may generate deviation data OFS corresponding to the difference between the second pull-up control code PUCD2 and the first pull-up control code PUCD1, and the second pull-down control code PDCD2 and the first pull-down control code PDCD1, and may store the deviation data OFS in the second set of registers 480b in which the second calibration data is stored.

When the calibration controller 405b activates the calibration enable signal ZQEN2 again in response to the calibration trigger signal ZQTRG, the calibration circuit 420b may update the second pull-up control code PUCD2 and the second pull-down control code PDCD2 by the difference indicated by the offset data OFS without performing the impedance calibration operation. Accordingly, during the idle period, the impedance calibration circuit 400b may reduce the impedance calibration interval.

Referring to FIG. 10, each of a plurality of indices Idx11 through Idx1s (where s is an integer greater than 2) may store a corresponding one of first pull-up control codes PUCD11[1: r ] through PUCD 1[1: r ] and a corresponding one of first pull-down control codes PDCD11[1: r ] through PDCD1s [1: r ] for a corresponding one of a plurality of sets of voltage and temperature variables (VVAR1[1: x ], TVAR1[1: y ]) through (VVARs [1: x ], TVARs [1: y ]). Here, each of x and y is an integer greater than 2. During an initialization sequence, a corresponding one of first pull-up control codes PUCD11[1: r ] through PUCD1s [1: r ] and a corresponding one of first pull-down control codes PDCD11[1: r ] through PDCD1s [1: r ] may be stored at various operating voltages. During idle periods, as voltage and temperature change, additional pull-up control codes, pull-down control codes, and voltage-temperature sets may also be stored in the first set of registers 480.

The first register set 480 may include a plurality of

columns

481, 482, 483, and 484. The first pull-up control code PUCD1 may be stored in column 481, the first pull-down control code PDCD1 may be stored in column 482, the voltage variable VVAR may be stored in column 483, and the temperature variable TVAR may be stored in column 484. A representative value covering the specified range may be stored as each of the voltage variable VVAR and the temperature variable TVAR. The average value associated with the specified range may be stored as a representative value. When the representative value is stored as each of the voltage variable VVAR and the temperature variable TVAR, the voltage and the temperature within the specified range are regarded as the same voltage and the same temperature, respectively. Since the logic 408 in fig. 7 activates the calibration trigger signal ZQTRG based on the interval signal ITS and the comparison signal CPS, the representative value can prevent the impedance calibration operation from being frequently performed. That is, when the change in voltage and temperature is out of the reference range, the background impedance calibration operation may be performed occasionally. In addition, since the background impedance calibration operation is performed when the voltage and temperature outside the reference range are detected, the background impedance calibration operation is performed when the operating temperature of the semiconductor memory apparatus 100 greatly changes.

Referring to FIG. 11, the second set of registers 480b may include second pull-up control codes PUCD21[1: r ] through PUCD2s [1: r ], second pull-down control codes PDCD21[1: r ] through PDCD2s [1: r ], and deviation data OFS21[1: z ] through OFS2s [1: z ] (z is an integer greater than 2) obtained in an impedance calibration operation during an initialization sequence. During idle periods, when the second pull-up control codes PUCD21[1: r ] to PUCD2s [1: r ] and the second pull-down control codes PDCD21[1: r ] to PDCD2s [1: r ] are to be updated in an impedance calibration operation, the second pull-up control codes PUCD21[1: r ] to PUCD2s [1: r ] and the second pull-down control codes PDCD21[1: r ] to PDCD2s [1: r ] may be updated by a difference indicated by a corresponding one of the deviation data OFS21[1: z ] to OFS2s [1: z ].

The second register set 480b may include a plurality of

columns

481b, 482b, and 485 b. The second pull-up control code PUCD2 may be stored in column 481b, the second pull-down control code PDCD2 may be stored in column 482b, and the offset data OFS may be stored in column 485 b.

Referring to FIG. 12, the second set of registers 480c may include second pull-up control codes PUCD31[1: r ] through PUCD3s [1: r ], second pull-down control codes PDCD31[1: r ] through PDCD3s [1: r ], and deviation data OFS31[1: z ] through OFS3s [1: z ] obtained in an impedance calibration operation during an initialization sequence. During idle periods, when the second pull-up control codes PUCD31[1: r ] to PUCD3s [1: r ] and the second pull-down control codes PDCD31[1: r ] to PDCD3s [1: r ] are to be updated in the impedance calibration operation, the second pull-up control codes PUCD31[1: r ] to PUCD3s [1: r ] and the second pull-down control codes PDCD31[1: r ] to PDCD3s [1: r ] may be updated by a difference indicated by a corresponding one of the deviation data OFS31[1: z ] to OFS3s [1: z ].

The second register set 480c may include a plurality of

columns

481c, 482c, and 485 c. The second pull-up control code PUCD3 may be stored in column 481c, the second pull-down control code PDCD3 may be stored in column 482c, and the offset data OFS may be stored in column 485 c.

Fig. 13 and 14 illustrate that an impedance calibration operation is performed during an initialization sequence in the semiconductor memory device of fig. 1 according to example embodiments.

In fig. 13, the semiconductor memory device 100 in fig. 1 includes a master wafer 200a and slave wafers 200b to 200 h. Here, h is an integer greater than 2.

Referring to fig. 13, each of the master wafer 200a and the slave wafers 200b to 200h includes an impedance pad ZQ connected to an external resistor RZQ, the master wafer 200a includes a first register set 480 connected to a first connection pad 402a, and each of the slave wafers 200b to 200h includes a corresponding one of the second register sets 480b to 480h and a corresponding one of the buffers 490b to 490 h. Each of the buffers 490b to 490h may be connected to the first register set 480 in the main wafer 200a through a corresponding one of the second connection pads 402b to 402 h.

Referring to fig. 14, during the initialization sequence, each of the master wafer 200a (DIE1) and the slave wafers 200b to 200h (DIE2 to DIE8) receives the impedance calibration command ZQ _ CAL from the memory controller 30, and each of the master wafer 200a and the slave wafers 200b to 200h performs the impedance calibration operation (CAL _ OP) in order. The master wafer 200a stores first calibration data, operating voltage, and operating temperature in the first register set 480, and each of the slave wafers 200b to 200h stores second calibration data and deviation data in a corresponding one of the second register sets 480b to 480 h.

Referring to fig. 15, when the changes of the voltage and temperature are out of the reference range, the master wafer 200a internally activates the calibration enable signal ZQEN1, performs a background impedance calibration operation (CAL _ OP), stores third calibration data in the first register set 480, and provides a calibration trigger signal ZQTRG to each of the slave wafers 200b to 200 h.

Each of the slave wafers 200b to 200h updates the pre-stored second calibration data LAT based on the deviation data stored in the corresponding one of the second register sets 480b to 480h in response to the calibration trigger signal ZQTRG. Since each of the slave wafers 200b to 200h adjusts the second calibration data by the difference indicated by the deviation data and stores the adjusted second calibration data instead of performing the impedance calibration operation, the interval corresponding to the background impedance calibration interval may be reduced by each of the slave wafers 200b to 200h during the idle period.

As described with reference to fig. 1 and 13, the master wafer 200a and the slave wafers 200b to 200h are disposed (formed) in the same board 110, and receive the operating voltage VDD from the PMIC 130. The process difference of each of the master wafer 200a and the slave wafers 200b to 200h may be different parameters when the master wafer 200a and the slave wafers 200b to 200h are manufactured, but may be a constant parameter when the master wafer 200a and the slave wafers 200b to 200h are operated. Considering the voltage and the temperature, since the master wafer 200a and the slave wafers 200b to 200h are adjacent in the package, and the thermal conductivity of the package is generally high, the temperature change of each of the master wafer 200a and the slave wafers 200b to 200h is similar with respect to each other. In addition, since each of the master and

slave wafers

200a and 200b to 200h receives the operating voltage VDD from the PMIC 130 through a similar path, the voltage change of each of the master and

slave wafers

200a and 200b to 200h is similar with respect to each other.

Accordingly, the master wafer 200a stores first calibration data obtained in the impedance calibration operation during the initialization sequence in the first register set, and each of the slave wafers 200b to 200h stores second calibration data obtained in the impedance calibration operation during the initialization sequence and deviation data corresponding to the first calibration data and the second calibration data in each of the second register sets. During the idle period, when the voltage and the temperature are changed, the second calibration data is updated from each of the wafers 200b to 200h based on the deviation data without performing the additional impedance calibration operation. Accordingly, during the idle period, the interval corresponding to the background impedance calibration interval may be reduced from each of the wafers 200b to 200 h.

Referring to fig. 1 to 16B, there is provided a method of operating a semiconductor memory device 100 including a master wafer 200a and a plurality of slave wafers 200B to 200k commonly connected to an external resistor RZQ provided in a board 110. According to the method, power is applied to the semiconductor memory apparatus 100 (power-on) (operation S210) and an initialization sequence is performed. During the initialization sequence, impedance calibration commands are applied from the memory controller 30 to the master wafer 200a and the slave wafers 200b to 200 k.

The main wafer 200a performs a first impedance calibration operation (operation S220), and the main wafer 200a stores first calibration data, voltage, and temperature associated with the first impedance calibration operation in the first register set 480 (operation S230).

The second impedance calibration operation is performed from each of the wafers 200b to 200k (operation S240), and the second calibration data obtained through the second impedance calibration operation and deviation data corresponding to a difference between the first calibration data and the second calibration data are stored in the second register set 480b from each of the wafers 200b to 200k (operation S250).

The semiconductor memory apparatus 100 enters an idle mode (operation S260) and performs a write operation and/or a read operation. When the operating voltage and the operating temperature of the semiconductor memory device 100 change, the main wafer 200a determines whether the impedance calibration operation is triggered (operation S270). When the impedance calibration operation is not triggered (no in operation S270), the semiconductor memory apparatus 100 enters the idle mode.

When the impedance calibration operation is triggered (yes in operation S270), the voltage/temperature sensor determines whether the voltage change VVAR and the temperature change TVAR are within the reference range (operation S280).

When it is determined that the voltage change VVAR and the temperature change TVAR are within the reference ranges (yes in operation S280), the semiconductor memory device 100 enters the idle mode. When it is determined that the voltage change VVAR and the temperature change TVAR are out of the reference ranges (no in operation S280), the calibration controller 405 in the master wafer 200a determines whether the voltage change VVAR and the temperature change TVAR are new entries based on whether the voltage change VVAR and the temperature change TVAR match the entries stored in the first register set 480 by searching the first register set 480 in operation S310 (operation S320). The calibration controller 405 may first search for temperature and then may search for voltage when a temperature match is found.

When it is determined that the voltage change VVAR and the temperature change TVAR are new entries not matching the entries stored in the first register set 480 (yes in operation S320), the main wafer 200a performs a background calibration operation at a new voltage and a new temperature (operation S330), and stores third calibration data in the first register set 480 (operation S340). The calibration controller 405 supplies a calibration trigger signal ZQTRG to each of the slave wafers 200b to 200 k. Each of the slave wafers 200b to 200k updates the second calibration data by the difference indicated by the deviation data in response to the calibration trigger signal ZQTRG and stores the updated second calibration data in the second register set 480b (operation S350). The semiconductor memory device 100 enters an idle mode (operation S260).

When it is determined that the voltage change VVAR and the temperature change TVAR are not new entries (no in operation S320), each of the slave wafers 200b to 200k updates the second calibration data by the difference indicated by the deviation data in response to the calibration trigger signal ZQTRG and stores the updated second calibration data in the second register set 480b (operation S350).

Referring to fig. 1 to 17, in a method of operating a semiconductor memory apparatus 100 including a multi-chip, a main chip 200 performs a first impedance calibration operation to store first calibration data, an associated voltage, and an associated temperature in a first register set 480 of the main chip 200 during an initialization sequence (operation S410).

During the initialization sequence, a second impedance calibration operation is performed from each of the wafers 200b to 200k to store second calibration data and deviation data corresponding to a difference between the first calibration data and the second calibration data in the second register set 480b (operation S420).

When the operating voltage and the operating temperature change are out of the reference ranges during the idle period of the semiconductor memory device 100, the master wafer 200a performs a background impedance calibration operation to store third calibration data in the first register set 480 (operation S430) and provide a calibration trigger signal ZQTRG to each of the slave wafers 200b to 200 k.

The slave wafers 200b to 200k each update the second calibration data by a difference indicated by the deviation data stored in the second register set 480b in response to the calibration trigger signal ZQTRG (operation S440). Updated second calibration data is stored in the second register set 480b from each of the wafers 200b to 200 k.

Referring to fig. 18, the multi-chip package 500 may include a plurality of memory dies 530, 540, and 550 stacked on a package substrate 510 in order. Memory die 530 may be a master die and memory dies 540 and 550 may be slave dies. The master wafer 530 may have substantially the same configuration as the master wafer 200a of fig. 2, and each of the

slave wafers

540 and 550 may have substantially similar configuration as the master wafer 200a of fig. 2.

Through Silicon Vias (TSVs) (not shown), bond wires (not shown), bumps (not shown), or solder balls 520 may be used to electrically connect the memory dies 530, 540, and 550 to each other.

Each of memory die 530, 540, and 550 may employ an impedance calibration circuit. Master wafer 530 may employ impedance calibration circuit 400 in fig. 7, and each of

slave wafers

540 and 550 may employ impedance calibration circuit 400b in fig. 9.

The master wafer 530 may be connected to the slave wafer 540 through wiring 561 and may be connected to the slave wafer 550 through wiring 562. The first set of registers of the master die 530 may be connected to buffers in the slave die 540 via wiring 561 and the first set of registers of the master die 530 may be connected to buffers in the slave die 550 via wiring 562.

Referring to fig. 19, a semiconductor memory device 700 may include at least one buffer wafer 710 and a plurality of memory wafers 720-1 to 720-p (p is a natural number equal to or greater than three) providing soft error analysis and correction functions in a stacked chip structure.

A plurality of memory dies 720-1 to 720-p may be stacked on the buffer die 710 and may pass data through a plurality of Through Silicon Via (TSV) lines.

Each of memory die 720-1 through 720-p can include a cell core 721 for storing data and a first type of ECC engine 723 for generating transmission parity bits (e.g., transmission parity data) based on transmission data to be sent to at least one buffer die 710. The first type of ECC engine 723 may be referred to as a 'cell core ECC engine'. The cell core 721 may include a plurality of memory cells having a DRAM cell structure.

The buffer wafer 710 may include a second type of ECC engine 712, which may correct a transmission error using transmission parity bits when the transmission error is detected from transmission data received through the TSV lines, and generate data after correcting the error. The second type of ECC engine 712 may be referred to as a 'punch-through ECC engine'.

The buffer die 710 may also include impedance calibration circuitry (ZQCC)714 and data I/O circuitry 716. The impedance calibration circuit 714 may be connected with an external resistor RZQ connected to the power supply voltage VDDQ.

The impedance calibration circuit 714 may employ the impedance calibration circuit 400 of fig. 7. The impedance calibration circuit 714 may provide the pull-up control code PUCD and the pull-down control code PDCD to the data I/O circuit 716. The data I/O circuit 716 may drive the data DTA provided from the second type of ECC engine 712 based on the pull-up control code PUCD and the pull-down control code PDCD to transmit the data signal DQ having the target VOH voltage to an external memory controller (e.g., the memory controller 30).

In the semiconductor memory device 700 of fig. 19, only the buffer chip 710 is connected to an external memory controller. During an initialization sequence, the impedance calibration circuit 714 performs a first impedance calibration operation for the memory die 720-1 to determine the resistance of the output driver and the VOH voltage of the first output driver, stores first calibration data, a voltage, and a temperature associated with the first impedance calibration operation in a set of registers of the memory die 720-1, performs a second impedance calibration operation for each of the memory dies 720-2 through 720-p, and stores second calibration data associated with the second impedance calibration operation and deviation data corresponding to a difference between the first impedance calibration and the second impedance calibration in the set of registers.

In addition, when the impedance calibration operation is triggered during the idle mode, the impedance calibration circuit 714 updates the second calibration data by the difference indicated by the deviation data for each of the memory dies 720-2 to 720-p, and stores the updated second calibration data in the register set. Accordingly, the impedance calibration circuit 714 may reduce the interval corresponding to the impedance calibration interval during the idle mode.

For example, the semiconductor memory device 700 may be a stacked chip type memory device or a stacked memory device that transfers data and control signals through TSV lines. The TSV lines may also be referred to as 'through electrodes'.

The first type of ECC engine 723 may perform error correction on data output from the memory die 720-p before the transfer data is sent.

The transmission error occurring at the transmission data may be due to, for example, noise occurring at the TSV line. Since a data failure due to noise occurring at the TSV line and a data failure due to erroneous operation of the memory wafer can be distinguished, they can be regarded as soft data failures (or soft errors). Soft data failures may be generated due to transmission failures on the transmission path and may be detected and corrected by ECC operations.

The data TSV group 732 formed at one memory wafer 720-p may include TSV lines L1 through Lp, and the parity TSV group 734 may include TSV lines L10 through Lq.

The TSV lines L1 to Lp of the data TSV group 732 and the parity TSV lines L10 to Lq of the parity TSV group 734 may be connected to the microbumps MCB correspondingly formed in the memory wafers 720-1 to 720-p.

The semiconductor memory device 700 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a host through the data bus B10. The buffer die 710 may be connected to a memory controller via a data bus B10.

The first type of ECC engine 723, indicated as a unit core ECC engine, may output transmission parity bits and transmission data through the parity TSV wire group 734 and the data TSV wire group 732, respectively. The output transfer data may be data after error correction by the first type of ECC engine 723.

The second type of ECC engine 712, indicated as a punch-through ECC engine, may determine whether a transmission error occurred at transmission data received over the data TSV wire set 732 based on transmission parity bits received over the parity TSV wire set 734. When a transmission error is detected, the second type of ECC engine 712 may correct the transmission error for the transmission data using the transmission parity bits. When the transfer error is uncorrectable, the second type of ECC engine 712 may output information indicating that an uncorrectable data error occurs. When an error is detected from read data in a High Bandwidth Memory (HBM) or a stacked memory structure, the error may be an error occurring due to noise when data is transmitted through the TSV.

According to example embodiments, as shown in fig. 19, a first type of ECC engine 723, indicated as a cell core ECC engine, may be included in the memory die, and a second type of ECC engine 712, indicated as a punch-through ECC engine, may be included in the buffer die. Thus, soft data failures can be detected and corrected. The soft data failure may include a transmission error generated due to noise when data is transmitted through the TSV line.

Referring to fig. 20, a semiconductor package 900 may include one or more stacked memory devices 910 and a Graphics Processing Unit (GPU) 920.

The stacked memory device 910 and GPU920 may be mounted on the middleware 930, and the middleware on which the stacked memory device 910 and GPU920 are mounted may be mounted on a package substrate 940 mounted on solder balls 950. The GPU920 may correspond to a semiconductor device that performs a memory control function. For example, GPU920 may be implemented as an application processor.

The stacked memory device 910 may be implemented in various forms, and the stacked memory device 910 may be a memory device in the form of a High Bandwidth Memory (HBM) in which a plurality of layers are stacked. Accordingly, the stacked memory device 910 may include a buffer die and a plurality of memory dies, and the buffer die may include an impedance calibration circuit.

A plurality of stacked memory devices 910 may be mounted on the middleware 930. The GPU920 may communicate with a plurality of stacked memory devices 910. For example, each of stacked memory device 910 and GPU920 may include a physical region through which communication may be performed between stacked memory device 910 and GPU 920. When the stacked memory device 910 includes a direct access region, test signals may be provided into the stacked memory device 910 through conductive devices (e.g., solder balls 950) mounted under the package substrate 940 and the direct access region.

The embodiments may be applied to a system using a semiconductor memory device including a plurality of chips. For example, the embodiments may be applied to systems such as a smart phone, a navigation system, a notebook computer, a desktop computer, and a game machine that utilize a semiconductor memory device as a work memory.

As is conventional in the art, embodiments may be described and illustrated in terms of blocks performing one or more functions. These blocks, which may be referred to herein as units or modules, etc., are physically implemented by analog and/or digital circuits (e.g., logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc.), and may optionally be driven by firmware and/or software. For example, these circuits may be implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board or the like. The circuitry making up the blocks may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some of the functions of the blocks and a processor for performing other functions of the blocks. Each block of an embodiment may be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure. Similarly, the blocks of an embodiment may be physically combined into more complex blocks without departing from the scope of the disclosure. An aspect of the embodiments may be implemented by instructions stored in a non-transitory storage medium and executed by a processor.

While the present disclosure has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that many changes in form and details of the present disclosure may be made therein without departing substantially from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A semiconductor memory device, comprising:

an external resistor disposed on the board; and

a plurality of memory dies mounted on the board and commonly connected to the external resistor, one of the plurality of memory dies being designated as a master die and the remaining memory dies of the plurality of memory dies except the master die being designated as a plurality of slave dies, wherein:

the master wafer is configured to:

performing a first impedance calibration operation in response to a first impedance calibration command to determine a resistance of a first output driver and a first reference output high level voltage of the first output driver during an initialization sequence of the semiconductor memory device; and

storing in a first set of registers in the host die first calibration data, a first voltage, and a first temperature associated with the first impedance calibration operation, and

after the first impedance calibration operation is completed, each of the plurality of slave wafers is configured to:

performing a second impedance calibration operation in response to the first impedance calibration command to determine a resistance of a second output driver and a second reference output high level voltage of the second output driver during the initialization sequence; and

second calibration data associated with the second impedance calibration operation and deviation data corresponding to a difference between the first calibration data and the second calibration data are stored in a second set of registers in the slave wafer.

2. The semiconductor memory device of claim 1, wherein each of the plurality of slave dies is configured to:

connecting to the first register set in the host die through a connection pad;

generating the deviation data by referring to the first register set; and

storing the deviation data in the second set of registers.

3. The semiconductor memory device of claim 1, wherein the master die is configured to:

occasionally comparing the first voltage and the first temperature with a second voltage and a second temperature of the semiconductor memory device during an idle period of the semiconductor memory device based on a detection signal associated with a change in an operating voltage and an operating temperature of the semiconductor memory device;

performing a background impedance calibration operation when a first difference between the second voltage and the first voltage and a second difference between the second temperature and the first temperature are outside a reference range;

storing, in the first set of registers, third calibration data associated with the background impedance calibration operation, the second voltage, and the second temperature; and

providing a calibration trigger signal associated with the background impedance calibration operation to the plurality of slave wafers.

4. The semiconductor memory device of claim 3, wherein each of the plurality of slave dies is configured to: updating the second calibration data stored in the second set of registers by a difference indicated by deviation data during the idle period in response to the calibration trigger signal after the background impedance calibration operation is completed.

5. The semiconductor memory device of claim 3, wherein the master die further comprises:

an impedance pad connected to the external resistor;

a first connection pad connected to the second connection pad of each of the plurality of slave chips; and

an impedance calibration circuit connected between the impedance pad and the first connection pad.

6. The semiconductor memory device according to claim 5, wherein:

the impedance calibration circuit further comprises:

a calibration controller configured to receive the first impedance calibration command from a corresponding command decoder; and

a calibration circuit connected to the external resistor through the impedance pad, the calibration circuit configured to:

performing the first impedance calibration operation in response to a calibration enable signal from the calibration controller to provide a pull-up control code and a pull-down control code to the first output driver;

storing the pull-up control code and the pull-down control code in the first set of registers; and

providing a first comparison signal and a second comparison signal to the calibration controller indicating that the first impedance calibration operation is complete, and

the calibration controller is configured to store the first voltage and the second voltage in the first set of registers based on the first comparison signal and the second comparison signal.

7. The semiconductor memory device according to claim 6, wherein:

the calibration controller is configured to:

comparing the first voltage and the first temperature with a second voltage and a second temperature of the semiconductor memory device based on a detection signal associated with an operating voltage and an operating temperature of the semiconductor memory device during an idle period of the semiconductor memory device; and

activating the calibration enable signal when a first difference between the second voltage and the first voltage and a second difference between the second temperature and the first temperature are outside a reference range, and

the calibration circuit is configured to:

performing a background impedance calibration operation associated with the second voltage and the second temperature in response to the calibration enable signal;

8. The semiconductor memory device according to claim 7, wherein the calibration controller comprises:

a timer configured to generate an interval signal that is periodically activated during the idle period;

a comparator configured to compare the first voltage and the first temperature with a second voltage and a second temperature, respectively, and configured to generate a comparison signal indicative of the first difference and the second difference based on a comparison result; and

logic configured to activate the calibration enable signal based on the interval signal and the comparison signal when the first difference and the second difference are outside of the reference range.

9. The semiconductor memory device according to claim 6, wherein the calibration circuit comprises:

a first code generator configured to generate the pull-up control code obtained from a result of comparing a target output high level voltage with a first voltage at a first node between a pull-up driver and a first replica pull-down driver;

a first code storage circuit configured to store the pull-up control code when the target output high level voltage becomes the same as the first voltage;

a second code generator configured to generate the pull-down control code obtained from a result of comparing the target output high-level voltage with a second voltage at a second node connected to the impedance pad; and

a second code storage circuit configured to store the pull-down control code when the target output high-level voltage becomes the same as the second voltage.

10. The semiconductor memory device according to claim 6, wherein:

the main chip further includes a data output circuit configured to output a data signal by driving data based on the pull-up control code and the pull-down control code, and

the data output circuit includes the first output driver.

11. The semiconductor memory device of claim 6, wherein each of the plurality of slave dies further comprises:

an impedance pad connected to the external resistor;

a second connection pad connected to the first connection pad of the main wafer;

a signal pad configured to receive a calibration trigger signal from the host die; and

an impedance calibration circuit connected between the impedance pad, the second connection pad, and the signal pad.

12. The semiconductor memory device according to claim 11, wherein:

the impedance calibration circuit further comprises:

a calibration controller comprising a timer, the calibration controller configured to receive the first impedance calibration command from a corresponding command decoder, and configured to receive the calibration trigger signal from the signal pad;

a buffer connected to the second connection pad, the buffer configured to temporarily store the first calibration data;

performing the second impedance calibration operation in response to a calibration enable signal from the calibration controller to generate second calibration data and provide a pull-up control code and a pull-down control code to the second output driver; and is

Storing the pull-up control code and the pull-down control code in the second set of registers; and

a calculator connected to the buffer, the calculator configured to generate the deviation data based on a difference between the first calibration data and the second calibration data, and

13. The semiconductor memory device according to claim 12, wherein the timer is configured to activate the calibration enable signals in a determined order according to one of the first impedance calibration command received by the calibration controller and the calibration trigger signal received by the calibration controller.

14. The semiconductor memory device according to claim 12, wherein:

the calibration controller is configured to: activating the calibration enable signal in response to the calibration trigger signal associated with changes in operating voltage and operating temperature of the semiconductor memory device during an idle period of the semiconductor memory device, and

the calibration circuit is configured to: updating the second calibration data stored in the second register set by a difference indicated by deviation data in response to the calibration enable signal during an idle period of the semiconductor memory device.

15. The semiconductor memory device according to claim 1, wherein:

the main wafer is mounted on the plate;

the plurality of slave wafers are stacked on the master wafer; and is

The master die is connected to a corresponding one of the plurality of slave dies by a corresponding one of a plurality of wires.

16. The semiconductor memory device according to claim 1, further comprising:

a voltage/temperature sensor configured to:

sensing an operating voltage and an operating temperature of the semiconductor memory device;

providing the main wafer with a detection signal that is activated when the operating voltage and the operating temperature change beyond a reference range; and

providing the operating voltage and the operating temperature to the main wafer, and

the master wafer and the plurality of slave wafers are configured to: in the idle mode, a background impedance calibration operation is performed in response to a calibration trigger signal aperiodically based on the detection signal.

17. A memory system, comprising:

a semiconductor memory device including a plurality of memory dies; and

a memory controller configured to control the semiconductor memory apparatus, wherein:

the semiconductor memory device includes:

an external resistor disposed on the board; and

the plurality of memory dies mounted on the board and commonly connected to the external resistor, one of the plurality of memory dies being designated as a master die and remaining ones of the plurality of memory dies other than the master die being designated as a plurality of slave dies,

the master wafer is configured to:

performing a first impedance calibration operation in response to an impedance calibration command to determine a resistance of a first output driver and a first reference output high level voltage of the first output driver during an initialization sequence of the semiconductor memory device; and

during the initialization sequence, performing a second impedance calibration operation in response to the impedance calibration command to determine a resistance of a second output driver and a second reference output high level voltage of the second output driver; and

18. A semiconductor memory device, comprising:

a first memory die configured to:

performing a first impedance calibration operation on the external resistance to obtain first calibration data, an

Determining a first resistance of a first output driver based on the first calibration data; and

a second memory die configured to:

performing a second impedance calibration operation on the external resistance to obtain second calibration data, an

Determining a second resistance of a second output driver based on a difference between the second calibration data and the first calibration data.

19. The semiconductor memory device according to claim 18, wherein the second output driver determines the second resistance in response to a command received from the first output driver.

20. The semiconductor memory device according to claim 18, wherein the second output driver determines the second resistance based only on the second calibration data before the second output driver determines the second resistance based on a difference between the second calibration data and the first calibration data, and

wherein the second output driver determines the second resistance based on both the second calibration data and a difference between the second calibration data and the first calibration data.