KR20030002503A - Semiconductor memory device having test mode of delay locked loop - Google Patents

Abstract

PURPOSE: A semiconductor memory device having a delay locked loop test mode is provided, which comprises a specific mode to test a delay locked loop, and tests whether the delay locked loop operates normally or not in the test mode state. CONSTITUTION: According to the semiconductor memory device comprising a data path(110) to transfer data read from a memory core during a normal operation, a delay locked loop(DLL)(150) receives an external clock signal, and generates at least one internal clock signal synchronized to the external clock signal. A mode register(100) generates a delay locked loop test mode signal by receiving one of addresses, in response to commands inputted from the external. A delay locked loop test pattern generation part(120) generates a test pattern to test the delay locked loop. At least one multiplexer(130) receives data being output through the data path from the memory core as the first input, and receives the test pattern as the second input, and outputs the first input and the second input selectively in response to the delay locked loop test mode signal. And at least one data output buffer(140) buffers data from the multiplexer in response to the internal clock signal, and outputs the buffered data.

Description

Semiconductor memory device having a delay locked loop test mode

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a delayed synchronous loop test mode.

In general, high speed memory devices such as Double Data Rate (DDR) SDRAM and Rambus DRAM have a delayed synchronization loop to facilitate data transmission and reception with an external memory controller. (Delay Locked Loop: hereinafter referred to as DLL) is used a lot. That is, the DLL functions to receive an external clock signal and generate an internal clock signal synchronized with the external clock signal. Therefore, the data is output in the memory by the internal clock signal generated by the delay synchronization loop.

In addition, in the general semiconductor memory device, various tests are performed to determine whether the respective internal circuits operate normally. However, the DLL does not have a specific test mode, and it is determined whether or not an abnormality or characteristic of the operation is performed by simply applying a read command to the memory and checking the output data. However, the memory does not simply repeat the data read operation but operates with an active instruction or a precharge instruction. Also, data is often not output between commands and instructions applied to the memory. As described above, even if the data is not outputted, even if the DLL is affected by power noise generated by an operation such as an active command or a refresh, there is a problem in that the occurrence of a malfunction cannot be accurately detected.

An object of the present invention is to provide a semiconductor memory device having a specific mode for testing a delayed synchronization loop and capable of testing whether the delayed synchronization loop operates normally in the test mode.

1 is a block diagram illustrating a semiconductor memory device having a delay locked loop test mode according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram illustrating a multiplexer and a delay synchronization loop test pattern generator in the semiconductor memory device shown in FIG. 1.

3 is a block diagram illustrating a semiconductor memory device having a delayed synchronization loop test mode according to another embodiment of the present invention.

In order to achieve the above object, a semiconductor memory device having a delayed synchronous loop test mode according to the present invention is a semiconductor memory device having a data path for transferring data read from a memory core in a normal operation, the external clock signal Is a delayed synchronous loop for generating at least one internal clock signal synchronized with an external clock signal, and is assigned one of addresses represented by a plurality of bits in response to predetermined commands input from the outside. A mode register for generating a test mode signal, a delayed synchronous loop test pattern generator for generating a predetermined test pattern for testing a delayed synchronous loop, and receiving predetermined bit data output through a data path from a memory core as a first input, A second input of the test pattern of a predetermined bit At least one multiplexer for selectively outputting a first input and a second input in response to a delayed synchronous loop test mode signal, and buffering data output from at least one multiplexer in response to the internal clock signal; It is preferably composed of at least one data output buffer for outputting the data.

In order to achieve the above object, the semiconductor memory device having a delayed synchronous loop test mode according to the present invention, a semiconductor memory device having a data path for transferring data read from the memory core in the normal operation, a plurality of registers A delayed synchronous loop for generating at least one internal clock signal synchronized with an external clock signal and outputting each bit data of the registers in a test mode; A mode register for allocating one of the addresses represented by bits to generate a delayed synchronous loop test mode signal, and receiving predetermined bit data output from the memory core through the data path as a first input, and each bit of the internal registers of the delayed synchronous loop. Take data as second input At least one multiplexer selectively outputting the first input and the second input in response to the delayed synchronous loop test mode signal, and buffers the data output from the at least one multiplexer in response to an internal clock signal, and buffers the buffered data. It is preferably composed of at least one data output buffer for output.

Hereinafter, a semiconductor memory device having a delayed synchronization loop (DLL) test mode according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a semiconductor memory device having a DLL test mode according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor memory device may include a mode register 100, a memory core and a data path 110, a DLL test pattern generator 120, multiplexers 130, a delay lock loop (DLL), and a data output buffer. Field 140.

The mode register 100 receives one of the addresses ADDR represented by a plurality of bits in response to a plurality of commands CMD applied from the outside to generate the DLL test mode signal DLL_TEST. As described above, the DLL test mode can be entered by a mode register set that can set a predetermined value in the mode register 100 to determine a specific mode. That is, the mode register set may be used to determine an operation mode of the semiconductor memory device, for example, a column address strobe (hereinafter referred to as CAS) latency, burst length, burst type, and the like. It can be used to determine entry into a test mode to distinguish between features or good quality of memory products. In order to enter the test mode by the mode register set, predetermined commands CMD are set to a constant level at a predetermined time, for example, at the rising edge of the external clock signal, and a predetermined value is supplied to the address terminal ADDR. do. Here, the command ADDR is a row address strobe (hereinafter referred to as RAS), a column address strobe (hereinafter referred to as CAS), a write enable (WE) and a chip select (CS). It can be a command such as. Supplying a predetermined value to the address ADDR may be implemented such that the semiconductor memory device enters the test mode by, for example, setting a specific bit to 1 among the address ADDR consisting of a plurality of bits. have. Assuming that the semiconductor memory device of the present invention is a DDR SDRAM, it can be implemented to be in a test mode by inputting 1 into the seventh address bit. As such, semiconductor memory designers code the addresses to provide various test modes. Accordingly, in the present invention, the DLL test mode signal DLL_TEST may be generated by being assigned one of the coded addresses for the DLL test.

The memory core and the data path 110 represent a block diagram showing a path through which data output from the memory core (not shown) is transferred. The memory core and data path 110 may include a memory cell array, a bit line sense amplifier, an input / output line sense amplifier, and the like. Here, the data output from the memory core and the data path 110 may be referred to as data read from a memory cell array (not shown), which is applied to the first input MIN1 of the multiplexers 130.

The DLL test pattern generator 120 generates a predetermined test pattern to test whether the DLL operates normally in the DLL test mode. Here, the test pattern may be implemented in various ways, but as an example, a high level, that is, "1" data is output on the rising edge of the external clock signal CLK, and a low level, that is, on the falling edge, A test pattern may be generated such that data of "0" is output. Here, the test pattern for the DLL test is applied as the second input MIN2 of the multiplexer 130 and consists of predetermined bit data.

The multiplexers 130 receive the data output from the memory core and the data path 110 as the first input MIN1 and the data output from the DLL test pattern generator 120 as the second input MIN2. In response to the DLL test mode signal (DLL_TEST), one of two inputs (MIN1 and MIN2) is selectively output. Here, the output data of the multiplexer 130 is represented by MOUT. That is, in the normal operation mode according to the operation mode of the semiconductor memory device, the first input MIN1 becomes a plurality of bits of output data MOUT, and in the DLL test mode, the second input MIN2 becomes the output data ( MOUT). Although not specifically illustrated in FIG. 1, the data MIN1 output through the memory core and the data path 110 includes data output from the actual memory core and a control signal for controlling the data output buffer. In addition, a plurality of multiplexers may be provided inside the semiconductor memory device, and according to implementation, only one multiplexer may be used.

The DLL 150 generates internal clock signals CLK_F and CLK_S synchronized with the clock signal CLK from a clock signal CLK applied from the outside. In FIG. 1, a clock signal generated in synchronization with a first edge of the external clock signal CLK, for example, a rising edge, is represented as a first internal clock signal CLK_F. In addition, the clock signal generated in synchronization with the second edge of the external clock signal CLK, for example, the falling edge, is represented by the second internal clock signal CLK_S. That is, the first and second internal clock signals CLK_F and CLK_S are signals generated in response to the rising edge and the falling edge of the external clock signal CLK, and may be referred to as signals that are delayed by a predetermined time with respect to the external clock signal CLK. Can be.

The data output buffers 140 input a plurality of bits of data MOUT applied from the multiplexers 130 to the first and second internal clock signals CLK_F and CLK_S generated by the delay lock loop 150. Buffer in response and output the buffered data through each output terminal OUT. Here, the output terminal OUT may be a data input / output terminal DQ provided in plural in the memory, or may be a data output strobe terminal DQS. That is, in the case of DDR SDRAM, a plurality of DQ terminals and one DQS terminal are provided. In the case of the DQS terminal, the data output buffer 140 may be an output buffer for buffering the data output strobe signal.

FIG. 2 is a detailed circuit diagram illustrating the multiplexer 130 and the DLL test pattern generator 120 of the semiconductor memory device shown in FIG. 1. Referring to FIG. 2, the multiplexer 130 includes first to third data transmitters 200, 210, and 220.

The first data transmitter 200 of FIG. 2 includes transmission gates TG21 and TG22 having inputs different from each other and outputs connected to each other, and an inverter 205. In addition, the second data transmitter 210 includes transmission gates TG23 and TG24 and an inverter 215, and the third data transmitter 220 includes transmission gates TG25 and TG26 and an inverter 225. It consists of.

The transmission gates TG21, TG23, and TG25 of each of the first to third data transmitters 200 to 220 are means for transferring the first input MIN1 during normal operation, respectively, and the DLL test mode signal DLL_TEST. Is turned on to deliver the respective bit data output from the first input MIN1, i.e., the data path. The data MIN1 connected to the inputs of the transmission gates TG21, TG23, and TG25 include first and second data DOi_F1 and DOi_S1 and a buffer enable signal DQBUFEN1, respectively. Assuming that the semiconductor memory device is a DDR SDRAM, DOi_F1 represents data input in response to the rising edge of the clock signal CLK among data read out from the memory core 110, and DOi_S1 represents the falling of the clock signal CLK. Represents data that is input in response to an edge. Also, DQBUFEN1 indicates a buffer enable signal for enabling the corresponding data output buffer. Therefore, during the normal operation of the semiconductor memory device, the data DOi_F1 and DOi_S1 and the buffer enable signal DQBUFEN1 transmitted through the data path are transmitted through the corresponding output terminals DOi_F2, DOi_S2, Output to DQBUFEN2). The data DOi_F2, DOi_S2, and DQBUFEN2 become respective output data MOUT of the multiplexer 130 shown in FIG.

In addition, the transmission gates TG22, TG24, and TG26 of the first to third data transmitters 200 to 220 are means for transmitting the second input MIN2 during the DLL test operation, and the DLL test mode signal ( When DLL_TEST is enabled, it is turned on to transmit a test pattern output from the second input MIN2, that is, the DLL test pattern generator 120. In detail, an input of the transfer gates TG22 and TG26 is connected to a power supply voltage Vdd, and an input of the transfer gate TG24 is connected to a ground voltage Vss.

Referring to FIG. 2, the DLL test pattern generator 120 implements a high level and a low level pattern by using a power supply voltage Vdd and a ground voltage Vss, respectively. Therefore, when the semiconductor memory device enters the DLL test mode, preset test pattern data of 0 or 1 is transferred to the corresponding output terminals DOi_F2, DOi_S2, and DQBUFEN2 through the data transfer units 200 to 220 of the multiplexer 130. Is output.

1 and 2, the operation of the semiconductor memory device having the DLL test mode according to the present invention will be described in detail.

First, the operation in the normal mode is described. At this time, since the DLL test mode signal DLL_TEST is not enabled, the DLL test mode signal DLL_TEST is in a first level, for example, a low level state. At this time, the output signals of the inverters 205, 215, and 225 of the first to third transmission units 200 to 220 become high levels, and the transmission gates TG21, TG23, and TG25 are turned on. If the buffer enable signal DQBUFEN1 is enabled, a high level buffer enable signal is transmitted through the turned-on transmission data TG25 and output as DQBUFEN2. In addition, when the clock signal CLK rises, the first data DOi_F is transmitted through the turned-on transfer gate TG21 and output as DOi_F2. At this time, when the clock signal CLK falls, the second data DOi_S1 is transferred through the turned-on transfer gate TG23 and output as DOi_S2. As such, in the normal mode, the data core MIN1 from the memory core and the data path 110 is output as MOUT through the multiplexers 130.

However, in the DLL test mode, since the DLL test mode signal DLL_TEST is enabled at a high level, the transfer gates TG22, TG24, and TG26 of each data transmission unit 200, 210, and 220 are turned on. Therefore, the test pattern MIN2 generated by the DLL test pattern generator 150 is output through the turned-on transfer gates TG22, TG24, and TG26 of the first to third data transmitters 200 to 220. That is, at the time when the buffer enable signal DQBUFEN2 is output in the normal operation, the high level data connected to the power supply voltage Vdd is output as a test pattern, and at the time when the external clock signal CLK rises and falls, respectively. The high level power supply voltage Vdd and the low level ground voltage VSS are output as test patterns. At this time, the data MOUT output through the multiplexer 130 is buffered in response to the first and second internal clock signals CLK_F and CLK_S in the data output buffer 140. Therefore, in the present invention, it is possible to detect whether the DLL operates normally not only in the section in which data is output, but also at the time when a precharge, an active instruction, or the like is applied.

As such, it can be seen that the circuit shown in FIG. 2 is multiplexed to output different data in the normal operation mode and the test mode. In the semiconductor memory device of FIG. 1, the multiplexers 130 may be connected to a data output buffer connected to all data output terminals DQ and data strobe output terminals DQS. However, in order to minimize the increase in the memory size according to the increase in the multiplexer, the multiplexer may be implemented to be connected only to the data output buffer connected to the data strobe output terminal DQS. If multiplexers are provided for all output terminals DQ and DQS, it is also possible to measure skew between each data output.

3 is a block diagram illustrating a semiconductor memory device having a DLL test mode according to another exemplary embodiment of the present invention. Referring to FIG. 3, a semiconductor memory device includes a mode register 300, a memory core and data path 310, multiplexers 330, a delay lock loop (DLL) 350, and data output buffers 340. do.

Since the mode register 300 and the core and data path 310 of FIG. 3 perform the same functions as the mode register 100 and the core and data path 110 of FIG. 1, detailed descriptions thereof will be omitted. As in FIG. 1, the data output from the memory core and the data path 310 in the normal operation of the memory is represented by MIN1.

The DLL 350 includes a plurality of registers, generates internal clock signals CLK_F and CLK_S synchronized with the external clock signal CLK, and outputs each bit data of the registers in the DLL test mode. That is, the registers are composed of a number of flip-flops, and store state information of the DLL, for example, current locking information. Therefore, when testing a DLL, it is possible to detect whether the DLL is operating normally by analyzing the register values.

The multiplexer 330 applies the data output from the memory core and the data path 310 to the first input MIN1 and the bit data REG_V of each register output from the DLL 350 to the second input MIN2. Is applied. Therefore, the multiplexer 330 selectively outputs the first and second inputs MIN1 and MIN2 in response to the DLL test mode signal DLL_TEST. In a general case, the number of bits of the data MIN2 output from the DLL 350 is greater than the number of bits of the first input MIN1. Therefore, in order to output register values through a limited number of DQ terminals and DQS terminals, an encoder or a parallel / serial conversion circuit is added between the DLL 350 and the input terminals of the multiplexer 330 to input the multiplexer 330. The number of bits applied can be reduced. As another example, an encoder or a parallel / serial conversion circuit may be provided in the data output buffer 340 to be enabled only in the test mode. In this case, the data MOUT output from the multiplexer 330 is applied to the data output buffer 340 and buffered in response to the first and second internal clock signals CLK_F and CLK_S.

The operation of the semiconductor memory device shown in FIG. 3 is almost similar to that of the semiconductor memory device shown in FIG. 1. However, in the DLL test mode, there is a difference in determining whether the DLL operates normally by using register values output from the registers (not shown) of the DLL 350. The semiconductor memory device shown in FIG. 3 can be advantageously applied, particularly when the DLL is implemented in a digital type.

According to the present invention, the semiconductor memory device includes a specific mode for testing a DLL, and in a DLL test mode state, a specific test pattern is output or register values indicating state information of the DLL are output so that data is not read. It is effective to easily detect whether the DLL works normally even in the non-operational period.

Claims (7)

A semiconductor memory device having a data path for transferring data read from a memory core in a normal operation, comprising: A delay synchronization loop configured to receive an external clock signal and generate at least one internal clock signal synchronized with the external clock signal; A mode register configured to generate a delayed synchronous loop test mode signal by receiving one of addresses represented by a plurality of bits in response to predetermined commands input from the outside; A delay synchronization loop test pattern generator for generating a predetermined test pattern to test the delay synchronization loop; Accepts predetermined bit data output from the memory core through the data path as a first input, accepts the test pattern of a predetermined bit as a second input, and responds to the first input and the response in response to the delayed synchronous loop test mode signal; At least one multiplexer for selectively outputting a second input; And And at least one data output buffer for buffering the data output from the at least one multiplexer in response to the internal clock signal and outputting the buffered data. The method of claim 1, wherein the delayed synchronization loop test pattern generator, And generating the test pattern to indicate a first level at a first edge of the external clock signal and a second level at a second edge. The method of claim 1, wherein the at least one multiplexer is At least one data transfer unit configured to transfer data output from the memory core or the delayed synchronization loop test pattern generator according to an operation mode of the semiconductor memory device, Each data transmission unit, A first transmission gate which is turned on when the delay locked loop test mode signal is disabled and transfers each bit data output from the data path in the turned on state; And And a second transfer gate which is turned on when the delay locked loop test mode signal is enabled and transfers the test pattern in the turned-on state. The method of claim 3, wherein each of the data output from the data path, A first data synchronized with a first edge of the external clock signal, a second data synchronized with a second edge of the external clock signal, and a buffer enable signal for enabling the data output buffer. Semiconductor memory device. A semiconductor memory device having a data path for transferring data read from a memory core in a normal operation, comprising: A delay synchronization loop including a plurality of registers, generating at least one internal clock signal synchronized with an external clock signal, and outputting each bit data of the registers in a test mode; A mode register configured to generate a delayed synchronous loop test mode signal by receiving one of addresses represented by a plurality of bits in response to predetermined commands input from the outside; Accepts predetermined bit data output from the memory core through the data path as a first input, accepts each bit data of internal registers of the delayed synchronization loop as a second input, and responds to the delayed synchronization loop test mode signal. At least one multiplexer for selectively outputting a first input and said second input; And And at least one data output buffer for buffering the data output from the at least one multiplexer in response to the internal clock signal and outputting the buffered data. The semiconductor memory device of claim 5, wherein the semiconductor memory device comprises: And an encoder for encoding bit data output from the registers of the delay synchronization loop and applying the encoded data to a second input of the multiplexer. The semiconductor memory device of claim 5, wherein the semiconductor memory device comprises: And a parallel / serial conversion unit for converting bit data output from each register of the delay lock loop into serial data and applying the converted serial data to a second input of the multiplexer. .