KR20240033637A - Memory device, method of operating the memory device and memory system including thereof - Google Patents

Abstract

Disclosed is a memory device, a method of operating the memory device, and a memory system. A memory device according to the present disclosure includes a data sampler that samples a data signal provided from a memory controller based on a write data strobe signal provided from the memory controller, and a delay change amount and voltage according to temperature on the transmission path of the write data strobe signal. A measurement circuit that measures the amount of delay change according to temperature change, a storage circuit that stores a coefficient code that controls the amount of delay change in the transmission path of the write data strobe signal according to temperature change, a temperature sensor that detects temperature, the detected temperature, and the amount of delay change according to temperature. , a monitoring circuit that generates a coefficient code determined by comparing the delay change amount and delay change amount according to voltage, a reference voltage generator that generates a reference voltage from the power supply voltage based on the determined coefficient code, and a voltage that generates an adjustment voltage based on the reference voltage. It may include a write data strobe signal transfer circuit that transfers the write data strobe signal to the data sampler using a regulator and an adjustable voltage.

Description

Memory device, method of operating the memory device, and memory system including the same {MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THEREOF}

The technical idea of the present disclosure relates to a semiconductor device, and more specifically, to a memory device that adjusts delay in a data clock path, a method of operating the memory device, and a memory system including the same.

Electronic devices such as smartphones, graphics accelerators, and AI accelerators can process data using memory devices such as DRAM (Dynamic Random Access Memory). Electronic devices can control internal or external memory devices through a memory controller. The memory controller can transmit various signals to the memory device to control the memory device.

Memory devices and memory controllers can transmit and receive data through data signals. A memory device may sample a data signal using a data clock signal (or write data strobe signal) provided from a memory controller. For example, the memory device may sample the data signal based on the edge timing of the data clock signal. In order to sample a data signal based on the data clock signal, the memory device may transmit the data clock signal to a circuit for sampling the data signal. The memory controller may perform training on the data clock signal to compensate for delay on a path for transmitting the data clock signal (hereinafter referred to as a data clock path).

Delay on the data clock path may vary depending on temperature changes in the memory device. If the sampling timing changes depending on the delay change in the data clock path, the S/H (Setup/Hold) margin may be reduced. The memory controller can perform retraining to compensate for delay changes due to temperature changes. Accordingly, the memory controller can adjust the delay on the data clock path. However, if retraining is performed, the resources used for training may increase.

The problem to be solved by the technical idea of the present disclosure is to provide a memory device that adjusts the delay on the data clock path according to real-time temperature changes without retraining by a memory controller, a method of operating the memory device, and a memory system including the same. .

A memory device according to the present disclosure includes a data sampler that samples a data signal provided from the memory controller based on a write data strobe signal provided from the memory controller, a delay change amount according to temperature on a transmission path of the write data strobe signal, and A measuring circuit that measures the amount of delay change according to voltage, a storage circuit that stores a coefficient code that adjusts the amount of delay change in the transmission path of the write data strobe signal according to temperature change, a temperature sensor that detects temperature, the detected temperature, the A monitoring circuit that generates a coefficient code determined by comparing the delay change amount according to temperature, the delay change amount according to the voltage, and the delay change amount, a reference voltage generator that generates a reference voltage from the power supply voltage based on the determined coefficient code, and the reference voltage It may include a voltage regulator that generates an adjustment voltage based on and a write data strobe signal transmission circuit that transmits the write data strobe signal to the data sampler using the adjustment voltage.

In a method of operating a memory device configured to sample a data signal provided from a memory controller based on a write data strobe signal provided from the memory controller according to the technical idea of the present disclosure, the temperature on the transmission path of the write data strobe signal is measuring the delay change amount according to the voltage and the delay change amount according to the voltage, generating the delay change amount based on the coefficient code according to the temperature change of the memory device, the delay change amount according to the temperature, the delay change amount according to the voltage, and the delay Generating a coefficient code determined by comparing the amount of change; and sampling the data signal by adjusting a delay on a transmission path of the write data strobe signal according to a temperature change of the memory device based on the determined coefficient code. You can.

In the memory system according to the technical idea of the present disclosure, a memory device for monitoring a delay change amount according to temperature, a delay change amount according to voltage, and a delay change amount for a write data strobe signal for sampling a data signal, and a memory device for controlling the delay change amount It includes a memory controller that determines a coefficient code, wherein the memory device compares the delay change amount according to the temperature, the delay change amount according to the voltage, and the delay change amount, and transmits the write data strobe signal according to the temperature change of the memory device. It may be configured to sample the data signal by adjusting the delay on the path.

According to the technical idea of the present disclosure, the delay on the data clock path can be adjusted according to temperature changes detected in real time, taking into account the characteristics of circuits on the data clock path. That is, changes in delay on the data clock path due to temperature changes can be compensated for without retraining the data clock signal. Accordingly, the S/H margin for sampling a data signal can be improved and data errors can be reduced regardless of temperature changes.

The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the technical field to which the exemplary embodiments of the present disclosure belong from the following description. It can be clearly derived and understood by those who have it. That is, unintended effects resulting from implementing the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure.
FIG. 2 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
Figure 3 is a block diagram showing a memory device for delay adjustment on a WDQS path according to an exemplary embodiment of the present disclosure.
4 is a flowchart showing a delay adjustment operation of a memory system according to an exemplary embodiment of the present disclosure.
FIG. 5 is a graph showing an example of a change in delay on a WDQS path depending on the temperature characteristics of an element of a memory device according to an exemplary embodiment of the present disclosure.
FIG. 6 is a graph showing an example of a change in delay on a WDQS path according to supply voltage characteristics of an element of a memory device according to an exemplary embodiment of the present disclosure.
Figure 7 is a table of exemplary operations of the monitoring circuit of Figure 3;
Figure 8 is a graph showing the results of temperature compensation according to an exemplary embodiment of the present disclosure.
Figure 9 is a block diagram showing a stacked memory device according to an exemplary embodiment of the present disclosure.
FIG. 10 is a diagram showing a semiconductor package according to an exemplary embodiment of the present disclosure.
FIG. 11 is a diagram showing an example of implementation of a semiconductor package according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , the memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may control the overall operation of the memory device 200. For example, the memory controller 100 may control the memory device 200 so that data (DATA) is output from the memory device 200 or data (DATA) is stored in the memory device 200.

The memory controller 100 may transmit various signals to the memory device 200 and receive various signals from the memory device 200. For example, the memory controller 100 transmits a command/address signal (CA), a clock signal (CK), a write data strobe signal (WDQS), and a data signal (DQ) to the memory device 200, and A data signal (DQ) can be received from 200. The command/address signal (CA) includes a command (CMD) and/or an address (ADD). The data signal DQ may include data DATA.

The memory controller 100 may be implemented in a host (not shown) and may access the memory device 200 according to a request from a processor (not shown) within the host. For example, the memory controller 100 may access the memory device 200 using a Direct Memory Access (DMA) method. For example, the memory controller 100 may be implemented as part of a system-on-chip (SoC), but is not limited thereto.

The memory device 200 may operate as a buffer memory, working memory, or main memory for a host including the memory controller 100. The memory device 200 may operate under the control of the memory controller 100. For example, the memory device 200 may output stored data (DATA) under control of the memory controller 100 or may store data (DATA) provided from the memory controller 100.

The memory device 200 may receive various signals from the memory controller 100 and transmit various signals to the memory controller 100 . For example, the memory device 200 receives a command/address signal (CA), a clock signal (CK), a write data strobe signal (WDQS), and a data signal (DQ) from the memory controller 100, and A data signal (DQ) can be transmitted to (200).

The memory controller 100 may include a phase locked loop 110, a first transmitter 130, a second transmitter 140, a phase controller 150, a third transmitter 160, and a fourth transmitter 170. there is. The phase locked loop 110 may generate an internal clock signal (ICS). For example, the internal clock signal (ICS) can toggle between high and low levels with a specific frequency.

The first transmitter 130 may transmit the command/address signal (CA) to the memory device 200 based on the internal clock signal (ICS). For example, the first transmitter 130 transmits a command (CMD) and/or an address (ADD) to a memory device through a command/address signal (CA) at the timing of the rising edge and/or falling edge of the internal clock signal (ICS). It can be sent to (200). The command/address signal (CA) may be transmitted to the memory device 200 through the command/address pin (CA_P').

The second transmitter 140 may transmit the internal clock signal ICS as a clock signal CK to the memory device 200. For example, the divided internal clock signal dICS and the clock signal CK may have the same frequency and the same phase. The clock signal CK may be transmitted to the memory device 200 through the clock pin CK_P'.

The third transmitter 160 may transmit the internal clock signal (ICS) as a write data strobe signal (WDQS) to the memory device 200. For example, the internal clock signal (ICS) and the write data strobe signal (WDQS) may have the same frequency and the same phase. The write data strobe signal WDQS may be transmitted to the memory device 200 through the write data strobe pin W_P'.

The fourth transmitter 170 may transmit the data signal DQ to the memory device 200 based on the internal clock signal ICS. For example, the fourth transmitter 170 may transmit data DATA to the memory device 200 through the data signal DQ at the timing of the rising edge and/or falling edge of the internal clock signal ICS. The data signal DQ may be transmitted to the memory device 200 through the data pin D_P'.

As described above, the clock signal CK and the write data strobe signal WDQS may be generated through one phase locked loop 110. Accordingly, the operating current of the memory controller 100 may be reduced. However, the present disclosure is not limited to this, and each of the clock signal CK and the write data strobe signal WDQS may be generated through separate phase-locked loops.

The memory device 200 may include a command/address sampler 210, a clock receiver 220, a write data strobe signal (WDQS) transmission circuit 230, and a data sampler 240.

The clock receiver 220 may receive the clock signal CK from the memory controller 100 through the clock pin CK_P. The clock signal CK received by the clock receiver 220 may be transmitted to the command/address sampler 210.

The command/address sampler 210 may receive a command/address signal (CA) from the memory controller 100 through a command/address pin (CA_P). The command/address sampler 210 may sample the command/address signal (CA) based on the clock signal (CK). For example, the command/address sampler 210 may sample the command/address signal CA at the timing of the rising edge and/or falling edge of the clock signal CK. Accordingly, the memory device 200 may obtain a command and/or address (CMD/ADD).

The WDQS transmission circuit 230 may receive the write data strobe signal (WDQS) from the memory controller 100 through the write data strobe pin (W_P). The WDQS transmission circuit 230 may transmit the write data strobe signal (WDQS) to the data sampler 240. In an example embodiment, the WDQS transfer circuit 230 may include a write data strobe signal (WDQS) receiver and a write data strobe signal (WDQS) tree circuit. For example, the write data strobe signal receiver may receive the write data strobe signal (WDQS) provided through the write data strobe pin (W_P). The write data strobe signal tree circuit may include a plurality of repeaters for transmitting the write data strobe signal WDQS output from the write data strobe signal receiver to the data sampler 240. For example, each of the plurality of repeaters may be implemented with at least one buffer or inverter.

The data sampler 240 may receive the data signal DQ from the memory controller 100 through the data pin D_P. The data sampler 240 may sample the data signal DQ based on the write data strobe signal WDQS. For example, the data sampler 240 may sample the data signal DQ at the timing of the rising edge and/or falling edge of the write data strobe signal WDQS. Accordingly, the memory device 200 may obtain data (DATA).

As described above, the memory device 200 may sample the data signal DQ based on the write data strobe signal WDQS, which is different from the clock signal CK. That is, the write data strobe signal (WDQS) may be a clock signal (i.e., a data clock signal) for data communication.

In an exemplary embodiment, the path through which the write data strobe signal (WDQS) is transmitted from the write data strobe pin (W_P) to the data sampler 240 (hereinafter referred to as the WDQS path (WDQS_P)) is from the data pin (D_P). It may not match the path through which the data signal DQ is transmitted to the data sampler 240 (hereinafter referred to as the DQ path DQ_P). For example, circuits on the WDQS path and the DQ paths (WDQS_P, DQ_P) may be arranged asymmetrically. For example, the number of transistors included in the WDQS path (WDQS_P) may be different from the number of transistors included in each DQ path (DQ_P). In this case, even if training is performed on the write data strobe signal (WDQS) during the initialization process of the memory device 200, the delay change on the WDQS path (WDQS_P) and the delay change on the DQ path (DQ_P) due to temperature changes are different. You can. Accordingly, the arrival timing (i.e., sampling timing) of the write data strobe signal WDQS transmitted to the data sampler 240 may vary. In particular, the delay change on the WDQS path (WDQS_P) according to temperature changes may vary depending on the characteristics of the elements on the WDQS path (WDQS_P). Accordingly, the S/H margin of the data sampler 240 may be reduced.

According to embodiments of the present disclosure, delay changes on the WDQS path due to temperature changes can be compensated for without retraining the write data strobe signal (WDQS). The memory device 200 may adjust the delay on the WDQS path according to temperature changes detected in real time, taking into account the characteristics of the circuits on the WDQS path. Accordingly, the delay on the WDQS path based on training performed during the initialization process of the memory device 200 can be maintained. Therefore, regardless of temperature changes, the S/H margin of the data sampler 240 can be improved and data errors can be reduced.

FIG. 2 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , the memory system 20 may include a memory controller 300 and a memory device 400. The memory controller 300 and the memory device 400 may correspond to the memory controller 100 and the memory device 200 of FIG. 1 . Accordingly, redundant descriptions below may be omitted.

The memory controller 300 may include a code decision circuit 310. The code decision circuit 310 may control an initialization operation or a test operation of the memory device 400. The code decision circuit 310 may determine a code in an initialization operation or test operation of the memory device 400 and set the determined code in the memory device 400 . Here, determining a code may mean determining a coefficient code. For example, the coefficient code may include Negative Temperature Coefficient (NTC) and Positive Temperature Coefficient (PTC). NTC's resistance value may decrease as the temperature value increases, and PTC's resistance value may increase as the temperature value increases. The coefficient code can adjust the LDO reference voltage change according to the temperature change. For example, the coefficient code may correspond to a delay adjustment amount for adjusting the delay on the WDQS path, and the coefficient code may be referred to as a delay code. When the delay on the WDQS path is adjusted according to the coefficient code, the delay on the WDQS path can be kept constant regardless of temperature changes. For example, the code decision circuit 310 may be implemented with a processor such as a CPU of the memory controller 300, but the present disclosure is not limited thereto.

In an example embodiment, code decision circuit 310 may determine a coefficient code based on a predetermined temperature. Additionally, the code decision circuit 310 may transmit the determined coefficient code to the memory device 400. The code decision circuit 310 may determine a coefficient code based on information of the write data strobe signal WDQS for temperature.

The memory device 400 may include a WDQS transfer circuit 410, a data sampler 420, and a storage circuit 450. The WDQS transmission circuit 410 may transmit the write data strobe signal (WDQS) provided from the memory controller 300 to the data sampler 420. The data sampler 420 may sample the data signal DQ provided from the memory controller 300 based on the write data strobe signal WDQS.

The storage circuit 450 may store the coefficient code provided from the memory controller 300. In an example embodiment, storage circuit 450 may be implemented as a resistor or fuse. For example, when the first code and the second code are set during the initialization process of the memory device 400, the storage circuit 450 may be a mode register. For example, when a coefficient code is set during a test process of the memory device 400, the storage circuit 450 may be a test mode register or a fuse.

Figure 3 is a block diagram showing a memory device for delay adjustment on a WDQS path according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3 , the memory device 500 may correspond to the memory devices 200 and 400 described with reference to FIGS. 1 and 2 . Accordingly, redundant descriptions below may be omitted.

Memory device 500 includes storage circuit 510, temperature sensor 520, monitoring circuit 530, reference voltage generator 540, voltage regulator 550, WDQS transfer circuit 560, and data sampler 570. ) may include. The storage circuit 510 corresponds to the storage circuit 450 in FIG. 2, and the WDQS transfer circuit 560 and data sampler 570 correspond to the WDQS transfer circuit 230 and the data sampler 240 in FIG. 1, respectively. We can respond.

The storage circuit 510 may store the coefficient code (CCODE). As described with reference to FIGS. 1 and 2 , the coefficient code CCODE may be determined by the memory controllers 100 and 300 during an initialization process or a test process. For example, storage circuit 510 may be implemented as one of a mode register, a test mode register, and a fuse.

Measurement circuit 515 may measure temperature and voltage on the WDQS path. For example, the measurement circuit 515 measures the delay change amount according to temperature on the WDQS path ( , TD) and delay change according to voltage ( , VD) can be measured. The measurement circuit 515 may transmit the delay change amount (TD) according to temperature and the delay change amount (VD) according to voltage to the monitoring circuit 530.

The temperature sensor 520 may detect the temperature of the memory device 500. The temperature sensor 520 may provide a temperature code (TCODE) based on the current sensed temperature to the monitoring circuit 530.

The monitoring circuit 530 may monitor the delay change amount (TVD). Delay change amount ( , TVD) is the amount of change in temperature ( The amount of change in LDO reference voltage according to ) ( ) can be. In other words, the delay change (TVD) is the change in LDO reference voltage ( ) is the amount of change in temperature ( ) means divided by The determined coefficient code (CCODE) may correspond to a delay adjustment amount for adjusting the delay on the WDQS path. For example, the monitoring circuit 530 may calculate the temperature change based on a predetermined reference temperature and a temperature code (TCODE). Additionally, the monitoring circuit 530 may compare the delay change amount (TD) according to temperature and the delay change amount (VD) and delay change amount (TVD) according to voltage. If the ratio of the delay change according to temperature (TD) divided by the delay change according to voltage (VD) is equal to the delay change (TVD) multiplied by -1, the determined coefficient code (CCODE) to adjust the delay is output. can do. For example, when the delay on the WDQS path is adjusted according to the determined coefficient code (CCODE), the delay on the WDQS path can be maintained constant regardless of temperature changes.

The reference voltage generator 540 may generate the reference voltage VREF from the power supply voltage VDDQ based on the determined coefficient code CCODE. The reference voltage generator 540 may generate a reference voltage VREF having a level corresponding to the determined coefficient code CCODE.

The voltage regulator 550 may generate a control voltage (VLDO) based on the reference voltage (VREF). For example, the voltage regulator 550 may generate the control voltage VLDO having a level lower than the level of the reference voltage VREF. The regulated voltage (VLDO) output from the voltage regulator 550 may be provided to the WDQS transfer circuit 560.

The WDQS transfer circuit 560 may transfer the write data strobe signal (WDQS) to the data sampler 570. The WDQS transfer circuit 560 may transfer the write data strobe signal (WDQS) to the data sampler 570 using the power supply voltage (VDDQ) and the control voltage (VLDO). For example, some of the repeaters (or inverters) of the WDQS transfer circuit 560 may operate using the power supply voltage (VDDQ), and others may operate using the regulation voltage (VLDO). In this case, the delay of the data strobe signal WDQS transmitted through repeaters operating using the control voltage VLDO can be controlled according to the level of the control voltage VLDO.

The data sampler 570 may sample the data signal DQ based on the write data strobe signal WDQS. When the delay on the WDQS path is adjusted based on the control voltage (VLDO), the S/H margin of the data sampler 570 can be improved regardless of temperature. Accordingly, the error rate of data output from the data sampler 570 can be reduced.

As described above, the memory device 500 is based on the pre-stored coefficient code (CCODE), delay change according to temperature (TD), delay change according to voltage (VD), delay change (TVD), and temperature code (TCODE). It is possible to control the level of the regulation voltage (VLDO) applied to the WDQS transfer circuit 560 through the voltage regulator 550. Accordingly, the memory device 500 can adjust the delay on the WDQS path according to the temperature detected in real time without retraining by the memory controllers 100 and 300.

4 is a flowchart showing a delay adjustment operation according to a memory system according to an exemplary embodiment of the present disclosure.

Specifically, an operation in which a memory system adjusts the delay on the WDQS path based on temperature changes will be described with reference to FIG. 4.

Referring to FIGS. 3 and 4 together, in step S110, the memory device 500 may measure the delay change amount (TD) according to temperature on the WDQS path. For example, the memory device 500 may measure the delay change (TD) according to temperature on the WDQS path through the measurement circuit 515.

In step S120, the memory device 500 may measure the delay change (VD) according to the voltage on the WDQS path. For example, the memory device 500 may measure the delay change (VD) according to the voltage on the WDQS path through the measurement circuit 515.

Referring to FIGS. 2 to 4 together, in step S130, the memory controller 300 may enable the coefficient code CCODE. For example, the memory controller 300 may enable the coefficient code (CCODE) through the code decision circuit 310. The code decision circuit 310 may enable the coefficient code (CCODE) according to the enable command. When the coefficient code CCODE is enabled, the code decision circuit 310 may transmit the coefficient code CCODE to the memory device 400.

In step S140, the memory device 500 may generate a delay change amount (TVD) based on the coefficient code (CCODE). For example, the memory device 500 may monitor the delay change TVD based on the coefficient code CCODE through the monitoring circuit 530.

In step S150, the memory device 500 may determine whether the ratio of the delay change amount (TD) according to temperature divided by the delay change amount (VD) according to voltage is equal to the delay change amount (TVD) multiplied by -1. For example, the memory device 500 divides the delay change amount (TD) according to temperature by the delay change amount (VD) according to voltage through the monitoring circuit 530, and the ratio is the delay change amount generated based on the coefficient code (CCODE). You can check whether it is the same as (TVD) multiplied by -1.

If the ratio of the delay change according to temperature (TD) divided by the delay change according to voltage (VD) is not equal to the delay change (TVD) multiplied by -1, the coefficient code (CCODE) is used in step S160. You can change it. For example, the memory controller 300 may change the coefficient code (CCODE) through the code decision circuit 310.

On the other hand, if the ratio of the delay change according to temperature (TD) divided by the delay change according to voltage (VD) is equal to the delay change (TVD) multiplied by -1, the coefficient code (CCODE) is determined in step S170. You can. For example, the memory device 500 and the monitoring circuit 530 may output the determined coefficient code (CCODE). The determined coefficient code (CCODE) may correspond to a delay adjustment amount for adjusting the delay on the WDQS path.

In step S180, the data signal DQ may be sampled based on the write data strobe signal WDQS according to the real-time temperature. Referring to FIG. 1 , for example, the write data strobe signal WDQS may be transmitted to the data sampler 240 through the WDQS transmission circuit 230. In this case, regardless of temperature changes of the memory device 200, the timing at which the write data strobe signal WDQS reaches the data sampler 240 may be kept constant. More specifically, the value of the voltage on the WDQS path can be adjusted according to the temperature change on the WDQS path using the delay change (TVD) value determined in step S150. If the temperature (t1) on the WDQS path monitored at the first time point is different from the temperature (t2) on the WDQS path monitored at the second time point after the first time point, the difference between t2 and t1 (t2-t1) The voltage on the WDQS path can be increased by the value multiplied by the delay change (TVD). That is, the voltage (v2) on the WDQS path at the second time point is the difference between t2 and t1 (t2-t1) multiplied by the delay change (TVD) added to the voltage (v1) on the WDQS path at the first time point. It can be set to be the same as the result. The data sampler 240 may sample the data signal DQ based on the write data strobe signal WDQS.

According to the memory system 10 of the present disclosure, the memory device 200 can compensate for delay changes on the WDQS path due to real-time temperature changes based on a coefficient code (CCODE) determined during an initialization process or a test process. That is, the delay on the WDQS path can be maintained constant without retraining by the memory controller 100. Accordingly, retraining to compensate for changes in delay on the WDQS path due to temperature changes may not be performed.

FIG. 5 is a graph showing an example of a change in delay on a WDQS path depending on the temperature characteristics of an element of a memory device according to an exemplary embodiment of the present disclosure.

The horizontal axis of Figure 5 represents temperature, and the vertical axis represents delay on the WDQS path. Referring to Figures 2 and 5, the amount of delay change on the WDQS path according to temperature change may vary depending on the device characteristics of the WDQS transfer circuit 410. Here, the amount of delay change on the WDQS path according to temperature change may be the delay change amount (TD) according to temperature described with reference to FIGS. 3 and 4. Device characteristics can be distinguished by the process corner of the device (e.g., transistor) on the WDQS path. For example, device characteristics can be divided into a slow process corner, a typical process corner, and a fast process corner.

When the elements of the WDQS transfer circuit 410 have first device characteristics (e.g., when the elements of the WDQS transfer circuit 410 correspond to a slow process corner), as the temperature of the memory system 20 increases, Delay on the WDQS path can be reduced.

When the elements of the WDQS transfer circuit 410 have secondary device characteristics (e.g., when the elements of the WDQS transfer circuit 410 correspond to a general process corner), as the temperature of the memory system 20 increases, Delay on the WDQS path can be reduced. As shown in FIG. 5, the delay reduction amount corresponding to the second device characteristic may be smaller than the delay reduction amount corresponding to the first device characteristic.

When the elements of the WDQS transfer circuit 410 have third device characteristics (e.g., when the elements of the WDQS transfer circuit 410 correspond to a fast process corner), as the temperature of the memory system 20 increases, Delay on the WDQS path may increase.

As shown in FIG. 5, the delay on the WDQS path according to the device characteristics of the WDQS transfer circuit 410 may change linearly (or almost linearly) according to temperature changes. Accordingly, a coefficient code reflecting device characteristics can be calculated based on delay values on the WDQS path corresponding to the current temperature. For example, the coefficient code can be calculated as the slope of the delay change according to temperature. Accordingly, when the memory device 400 compensates for a change in delay using a coefficient code calculated based on delay values of temperature, temperature compensation reflecting device characteristics may be performed.

FIG. 6 is a graph showing an example of a change in delay on a WDQS path according to supply voltage characteristics of an element of a memory device according to an exemplary embodiment of the present disclosure.

The horizontal axis of Figure 6 represents the supply voltage, and the vertical axis represents the delay on the WDQS path.

Referring to Figures 2 and 6, the amount of delay change on the WDQS path according to the supply voltage change may vary depending on the device characteristics of the WDQS transfer circuit 410. Here, the amount of delay change on the WDQS path according to the change in supply voltage may be the amount of delay change (VD) according to voltage described with reference to FIGS. 3 and 4. As the supply voltage increases, the amount of delay change may increase.

As shown in FIG. 6, the delay on the WDQS path according to the device characteristics of the WDQS transfer circuit 410 may change linearly (or almost linearly) according to the change in supply voltage. Accordingly, a coefficient code reflecting device characteristics can be calculated based on delay values on the WDQS path corresponding to the supply voltage. For example, the coefficient code can be calculated as the slope of the delay change according to voltage. Accordingly, when the memory device 400 compensates for delay changes using a coefficient code calculated based on voltage delay values, temperature compensation reflecting device characteristics may be performed.

Figure 7 is a table of exemplary operations of the monitoring circuit of Figure 3;

Referring to FIGS. 3 and 7 together, the monitoring circuit 530 may calculate a temperature code (TCODE), which is a temperature change, by comparing the current temperature and the reference temperature. For example, the reference temperature may be stored in advance in the monitoring circuit 530.

The monitoring circuit 530 can monitor the temperature code (TCODE) and coefficient code (CCODE).

As shown in FIGS. 3 and 7, the monitoring circuit 530 may output a first coefficient code (CCODE1) in response to the first temperature code (TCODE1), and output a first coefficient code (CCODE1) in response to the second temperature code (TCODE2). The second coefficient code (CCODE2) can be output, and the nth coefficient code (CCODEn) can be measured in response to the nth temperature code (TCODEn).

As described with reference to FIG. 7, the coefficient coat (CCODE) may reflect the device characteristics of the WDQS transfer circuit.

Figure 8 is a graph showing the results of temperature compensation according to an exemplary embodiment of the present disclosure.

Content that overlaps with FIG. 5 will be omitted and FIG. 8 will be described below.

Referring to Figures 5 and 8, the delay reduction amount of the first result may be smaller than the delay reduction amount in the case of having the first element specification.

The delay reduction amount of the second result may be smaller than the delay reduction amount in the case of having the second element specification.

The delay reduction amount of the third result may be greater than the delay reduction amount in the case of having the third element specification.

According to the embodiments of FIG. 8, the delay on the data clock path can be adjusted according to temperature changes detected in real time, taking into account the characteristics of circuits on the data clock path. That is, changes in delay on the data clock path due to temperature changes can be compensated for without retraining the data clock signal. Accordingly, the S/H margin for sampling a data signal can be improved and data errors can be reduced regardless of temperature changes.

Figure 9 is a block diagram showing a stacked memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 9 , the stacked memory device 700 may correspond to the memory devices 200, 400, and 500 described with reference to FIGS. 1 to 8. The stacked memory device 700 may include a buffer die 710 and a plurality of core dies 720 to 750. For example, the buffer die 710 may also be referred to as an interface die, base die, logic die, master die, etc., and each of the core dies 720 to 750 may also be referred to as a memory die, slave die, etc. there is. In FIG. 9 , the stacked memory device 700 is shown to include four core dies 720 to 750, but the number of core dies may vary. For example, stacked memory device 700 may include 8, 12, or 16 core dies.

The buffer die 710 and the core dies 720 to 750 may be stacked and electrically connected through through silicon vias (TSV). Accordingly, the stacked memory device 700 may have a three-dimensional memory structure in which a plurality of dies 710 to 750 are stacked. For example, the stacked memory device 700 may be implemented based on High Bandwidth Memory (HBM) or Hybrid Memory Cube (HMC) standards.

The stacked memory device 700 may support a plurality of functionally independent channels (or vaults). For example, as shown in FIG. 9, the stacked memory device 700 can support 16 channels (CH0 to CH15). When each of the channels (CH0 to CH15) supports 64 data transmission paths (i.e., when there are 64 data signal (DQ) pins corresponding to each of the channels (CH0 to CH15)), 16 channels The stacked memory device 700 including (CH0 to CH15) can support 1024 data transmission paths. However, the present disclosure is not limited thereto, and the stacked memory device 700 may support more than 1024 data transmission paths and various numbers of channels (eg, 8 channels). For example, if the stacked memory device 700 supports 8 channels and each of the channels supports 128 data transmission paths, the stacked memory device 700 can support 1024 data transmission paths.

Each of the core dies 720 to 750 may support at least one channel. For example, as shown in FIG. 9, each of the core dies 720 to 750 may support 4 channels (CH0-CH3, CH4-CH7, CH8-CH11, CH12-CH15). In this case, the core dies 720 to 750 may support different channels. However, the present disclosure is not limited to this, and at least two of the core dies may support the same channel. For example, when the stacked memory device 700 includes 8 core dies, one of the four core dies forming one stack and one of the four core dies forming another stack are The same channel can be supported. In this case, core dies supporting the same channel can be distinguished by a stack ID (SID).

Each of the channels can configure an independent command and data interface. For example, each channel may be independently clocked based on independent timing requirements and may not be synchronized with each other.

Each of the channels may include a plurality of memory banks 701. Each of the memory banks 701 may include memory cells connected to word lines and bit lines, a sense amplifier, etc. For example, each of the channels CH0 to CH15 may include 32 memory banks 701. However, the present disclosure is not limited to this, and each of the channels CH0 to CH15 may include eight or more memory banks 701. In FIG. 9, the memory banks 701 included in one channel are shown as included in one core die. However, the memory banks 701 included in one channel may be distributed over a plurality of core dies. there is. For example, when two of the core dies support the first channel (CH0), the memory banks 701 of the first channel (CH0) may be distributed across the two core dies.

In an example embodiment, one channel may be divided into two independently operating pseudo channels. For example, pseudo channels may share the channel's command and clock inputs (e.g., clock signal (CK) and/or clock enable signal (CKE)), but may decode and execute commands independently. . For example, if one channel supports 64 data transmission paths, each of the pseudo channels can support 32 data transmission paths. For example, if one channel includes 32 memory banks 701, each of the pseudo channels may include 16 memory banks 701.

The buffer die 710 and the core dies 720 to 750 may include a TSV area 702. TSVs configured to penetrate the dies 710 to 750 may be disposed in the TSV area 702. The buffer die 710 can transmit and receive various signals with the core dies 720 to 750 through TSVs. Each of the core dies 720 to 750 may transmit and receive signals with the buffer die 710 and other core dies through TSVs. In this case, signals can be transmitted and received independently through corresponding TSVs for each channel. For example, an external host device (e.g., the memory controller 100 in FIG. 1) transmits a data signal to the first channel CH0 to store data in the memory cell of the first channel CH0. In this case, the buffer die 710 may transmit a data signal to the first core die 720 through TSVs corresponding to the first channel CH0. Accordingly, data may be stored in the memory cell of the first channel CH0.

In an example embodiment, the power supply voltage (VDDQL) may be used for signal transmission through TSVs. The power supply voltage (VDDQL) may be smaller than the power supply voltage (VDDQ) used for the overall operation of the buffer die 710. For example, the power supply voltage (VDDQ) may be 1.1V, and the power supply voltage (VDDQL) may be 0.4V.

The buffer die 710 may include a physical layer (PHY, 711). The physical layer 711 may include interface circuits for communication with an external host device. In an exemplary embodiment, the physical layer 711 may include an interface circuit corresponding to each of the channels CH0 to CH15. For example, an interface circuit corresponding to one channel may include components 210 to 240 of the memory device 200 of FIG. 1 . Signals received from the host device through the physical layer 711 may be transmitted to the core dies 720 to 750 through TSVs.

In an example embodiment, the buffer die 710 may include a channel controller corresponding to each of the channels. The channel controller can manage memory reference operations of the corresponding channel and determine timing requirements of the corresponding channel.

In an example embodiment, the buffer die 710 may include a plurality of pins for receiving signals from an external host device. The buffer die 710 sends a clock signal (CK), a command/address signal (CA), a write data strobe signal (WDQS), and a data signal (DQ) through a plurality of pins, as described with reference to FIG. It is possible to receive and transmit a data signal (DQ).

In an example embodiment, the stacked memory device 700 may further include an Error Correction Code (ECC) circuit to detect and correct data errors. For example, in a write operation, the ECC circuit may generate parity bits for data delivered from the host device. In a read operation, the ECC circuit may detect and correct an error in data transmitted from one of the core dies 720 to 750 using parity bits, and transmit the error-corrected data to the host device.

In an exemplary embodiment, the stacked memory device 700 may store a coefficient code for compensating for a change in delay on the WDQS path due to a change in temperature, as described with reference to FIGS. 1 to 8 . For example, the coefficient code may be determined during the initialization or testing process of the stacked memory device 700. The stacked memory device 700 can adjust the delay on the WDQS path according to the real-time temperature based on the stored coefficient code or the determined coefficient code. Accordingly, even if the temperature of the stacked memory device 700 changes, the stacked memory device 700 can maintain the delay on the WDQS path constant without retraining by the host device. Accordingly, the S/H margin for sampling the data signal DQ can be improved regardless of temperature changes.

FIG. 10 is a diagram showing a semiconductor package according to an exemplary embodiment of the present disclosure.

Referring to FIG. 10 , the semiconductor package 1000 may include a stacked memory device 1100, a system-on-chip 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer die 1110 and core dies 1120 to 1150. The stacked memory device 1100 may correspond to the stacked memory device 700 described with reference to FIG. 9 .

Each of the core dies 1120 to 1150 may include memory cells for storing data. The buffer die 1110 may include a physical layer 1111 and a direct access area (DAB) 1112. The physical layer 1111 may be electrically connected to the physical layer 1210 of the system-on-chip 1200 through the interposer 1300. The stacked memory device 1100 may receive signals from the system-on-chip 1200 through the physical layer 1111, or may transmit signals to the system-on-chip 1200. The physical layer 1111 may include components of the buffer die 710 described with reference to FIG. 9 .

The direct access area 1112 may provide an access path for testing the stacked memory device 1100 without going through the system-on-chip 1200. Direct access area 1112 may include conductive means (e.g., ports or pins) that can communicate directly with an external test device. The test signal received through the direct access area 1112 may be transmitted to the core dies 1120 to 1150 through the TSVs. For testing of the core dies 1120 to 1150, data read from the core dies 1120 to 1150 may be transmitted to a test device through the TSVs and the direct access area 1112. Accordingly, a direct access test on the core dies 1120 to 1150 may be performed.

The buffer die 1110 and the core dies 1120 to 1150 may be electrically connected to each other through TSVs 1101 and bumps 1102. The buffer die 1110 receives signals provided to each channel from the system-on-chip 1200 through bumps 1102 allocated for each channel, or sends signals through the bumps 1102 to the system-on-chip 1200. It can be sent to . For example, bumps 1102 may be micro bumps.

The system-on-chip 1200 can execute applications supported by the semiconductor package 1000 using the stacked memory device 1100. For example, the system-on-chip 1200 includes a Central Processing Unit (CPU), an Application Processor (AP), a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), a Tensor Processing Unit (TPU), and a Vision Processing Unit (VPU). ), an Image Signal Processor (ISP), and a Digital Signal Processor (DSP) may be used to execute specialized operations.

The system-on-chip 1200 can control the overall operation of the stacked memory device 1100. The system-on-chip 1200 may correspond to the memory controllers 100 and 300 described above. System-on-chip 1200 may include a physical layer 1210. The physical layer 1210 may include an interface circuit for transmitting and receiving signals to and from the physical layer 1111 of the stacked memory device 1100. For example, the physical layer 1210 may include components of the memory controller 100 of FIG. 1 . The system-on-chip 1200 may provide various signals to the physical layer 1111 through the physical layer 1210. Signals provided to the physical layer 1111 may be transmitted to the core dies 1120 to 1150 through the interface circuit of the physical layer 1111 and the TSVs 1101.

The interposer 1300 may connect the stacked memory device 1100 and the system-on-chip 1200. The interposer 1300 connects the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the system-on-chip 1200 and may provide physical paths formed using conductive materials. . Accordingly, the stacked memory device 1100 and the system-on-chip 1200 are stacked on the interposer 1300 and can transmit and receive signals to each other.

Bumps 1103 may be attached to the top of the package substrate 1400, and solder balls 1104 may be attached to the bottom. For example, bumps 1103 may be flip-chip bumps. The interposer 1300 may be stacked on the package substrate 1400 through bumps 1103 . The semiconductor package 1000 can transmit and receive signals with other external packages or semiconductor devices through the solder ball 1104. For example, the package substrate 1400 may be a printed circuit board (PCB).

In an example embodiment, the physical layer 1111 of the buffer die 1110 may receive the write data strobe signal WDQS and the data signal DQ from the system-on-chip 1200 through bumps 1102. . The physical layer 1111 may sample the data signal DQ based on the write data strobe signal WDQS having an adjusted delay coefficient code, as described with reference to FIGS. 1 to 9 .

FIG. 11 is a diagram showing an example of implementation of a semiconductor package according to an exemplary embodiment of the present disclosure.

Referring to FIG. 11 , a semiconductor package 2000 may include a plurality of stacked memory devices 2100 and a system-on-chip 2200. Each of the stacked memory devices 2100 may correspond to the stacked memory device 1100 of FIG. 10 and the system-on-chip 2200 may correspond to the system-on-chip 1200 of FIG. 10 . The stacked memory devices 2100 and the system-on-chip 2200 may be stacked on the interposer 2300, and the interposer 2300 may be stacked on the package substrate 2400. The semiconductor package 2000 can transmit and receive signals with other external packages or semiconductor devices through the solder ball 2001 attached to the lower part of the package substrate 2400.

Each of the stacked memory devices 2100 may be implemented based on the HBM standard. However, the present disclosure is not limited thereto, and each of the stacked memory devices 2100 may be implemented based on GDDR, HMC, or Wide I/O standards.

The system-on-chip 2200 may include at least one processor, such as a CPU, AP, GPU, or NPU, and a plurality of memory controllers for controlling a plurality of stacked memory devices 2100. The system-on-chip 2200 can transmit and receive signals with a corresponding stacked memory device through a memory controller.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached patent claims.

Claims (10)

a data sampler that samples a data signal provided from the memory controller based on a write data strobe signal provided from the memory controller;
a measurement circuit that measures a delay change according to temperature and a delay change according to voltage on a transmission path of the write data strobe signal;
a storage circuit that stores a coefficient code that adjusts the amount of delay change in a transmission path of the write data strobe signal according to temperature changes;
A temperature sensor that detects temperature;
a monitoring circuit that generates a coefficient code determined by comparing the sensed temperature, the delay change amount according to the temperature, the delay change amount according to the voltage, and the delay change amount;
a reference voltage generator that generates a reference voltage from the power supply voltage based on the determined coefficient code;
a voltage regulator that generates an adjusted voltage based on the reference voltage; and
A memory device comprising a write data strobe signal transmission circuit that transmits the write data strobe signal to the data sampler using the control voltage. a first pin that receives the data signal from a controller; and
Further comprising a second pin that receives the write data strobe signal from the memory controller,
The data signal path corresponding to the first path from the first pin to the data sampler does not match the transmission path of the write data strobe signal corresponding to the second path from the second pin to the data sampler. Not a memory device. According to claim 1,
The write data strobe signal transmission circuit transmits the write data strobe signal to the data sampler based on a delay corresponding to the determined first code and the determined second code. According to claim 1,
The determined coefficient code is a memory device characterized in that it is generated when the ratio of the temperature measurement value divided by the voltage measurement value is the same as the delay change amount. According to claim 1,
The coefficient code is a memory device characterized in that the amount of change in the write data strobe signal according to the temperature change of the memory device. According to clause 5,
A memory device, wherein each of the coefficient codes operates in response to a coefficient code enable command provided from the memory controller. According to claim 1,
A memory device that stores the coefficient code in a mode register in response to a mode register set command provided from the memory controller. A method of operating a memory device configured to sample a data signal provided from a memory controller based on a write data strobe signal provided from the memory controller, comprising:
measuring a delay change according to temperature and a delay change according to voltage on a transmission path of the write data strobe signal;
generating a delay change amount based on a coefficient code according to a temperature change of the memory device;
generating a coefficient code determined by comparing the delay change amount according to the temperature, the delay change amount according to the voltage, and the delay change amount; and
A method of operating a memory device comprising sampling the data signal by adjusting a delay in a transmission path of the write data strobe signal according to a change in temperature of the memory device based on the determined coefficient code. According to clause 8,
The step of generating the determined coefficient code is,
A method of operating a memory device, characterized in that the ratio of the delay change according to the temperature divided by the delay change according to the voltage is equal to the delay change. According to clause 8,
If the ratio divided by the delay change according to the temperature and the delay change according to the voltage is different from the delay change,
A method of operating a memory device, characterized in that the amount of delay change is controlled by adjusting the coefficient code.

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