CN117640288A

CN117640288A - Data transmission method, device, system, slave equipment and storage medium

Info

Publication number: CN117640288A
Application number: CN202311824146.3A
Authority: CN
Inventors: 林敏�; 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-03-01

Abstract

The embodiment of the invention discloses a data transmission method, a device, a system, a slave device and a storage medium, wherein the data transmission method comprises the following steps: responding to the target interaction indication signal, and initiating a DMA request signal to a local DMA controller; the target interaction indication signal comprises an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge moment of the last address pulse signal sent by the host device in the I2C communication system; performing data interaction with a local DMA controller through a DMA request signal to obtain DMA interaction data; in the event that it is determined that the handshake process is completed with the host device, the DMA interaction data is sent to the host device. The technical scheme of the embodiment of the invention can improve the robustness of the I2C data communication, thereby improving the data transmission quality between the master device and the slave device in the I2C-based data transmission system.

Description

Data transmission method, device, system, slave equipment and storage medium

Technical Field

The embodiment of the invention relates to the technical field of communication, in particular to a data transmission method, a device, a system, slave equipment and a storage medium.

Background

I2C (Inter-Integrated Circuit, bidirectional two-wire synchronous serial bus) is a common bus protocol, and is generally applied as an IP of a communication interface, for example, bootLoader and Inter-system bus extension. The I2C can complete communication by using a small amount of buses, saves design space, has lower communication power consumption, and has good popularity and practicality.

The I2C interface can finish stable and reliable data transmission for different application scenes through a small number of buses, and mainly depends on an optional address mode and an optional working mode. The address modes of the I2C are classified into 7-bit address and 10-bit address, and the operation modes of the I2C may be classified into Standard Mode (Standard Mode, typically 100 Khz), fast Mode (Fast Mode, typically 400 Khz), fast Mode Plus (Fast mode+, typically 1 Mhz) and High Speed Mode (High Mode, 3.4 Mhz). Meanwhile, the I2C can support two modes, namely Clk struct Mode (clock stretching Mode) and Clk Nostrech Mode (clock non-stretching Mode), wherein Clk Nostrech Mode Mode is widely applied.

The inventors found in the course of implementing the present invention that: with the iteration and innovation of the technology, the market has put forward higher demands on the speed and data reliability of common I2C communication, and the data communication can be required to be completed with a host in real time and rapidly under different address modes without any problem affecting the communication quality. However, the maximum operating frequency of the product is limited due to the influence of the process, the operating temperature, the power consumption and the critical path, so when the operating frequency of the product is lower, the I2C selects Clk Nostrech Mode, the slave device and the DMA (Direct Memory Access ) cooperate to form a difficulty, and in the process of performing data interaction between the host device and the slave device based on the I2C, partial byte data is easily discarded in the High Speed Mode or the Fast Mode Plus Mode, so that the data communication quality between the host device and the slave device is affected, and the success or failure of the product is affected by serious problems.

Disclosure of Invention

The embodiment of the invention provides a data transmission method, a device, a system, slave equipment and a storage medium, which can improve the robustness of I2C data communication and further improve the data transmission quality between the master equipment and the slave equipment in an I2C-based data transmission system.

According to an aspect of the present invention, there is provided a data transmission method applied to a slave device in an I2C-based data transmission system, the slave device being at Clk No strech Mode; the method comprises the following steps:

responding to the target interaction indication signal, and initiating a DMA request signal to a local DMA controller; wherein the target interaction indication signal comprises an address matching signal or an IRQ (interrupt ReQuest) signal; the address matching signal is triggered at the time of the falling edge of the last address pulse signal sent by the host equipment in the I2C communication system;

performing data interaction with the local DMA controller through the DMA request signal to obtain DMA interaction data;

and sending the DMA interaction data to the host device under the condition that the handshake process is completed with the host device.

According to another aspect of the present invention, there is provided a data transmission apparatus configured as a slave device in an I2C-based data transmission system, the slave device being at Clk No strech Mode; the device comprises:

The DMA request signal initiating module is used for responding to the target interaction indication signal and initiating a DMA request signal to the local DMA controller; wherein the target interaction indication signal comprises an address matching signal or an IRQ signal; the address matching signal is triggered at the time of the falling edge of the last address pulse signal sent by the host equipment in the I2C communication system;

the DMA interaction data acquisition module is used for carrying out data interaction with the local DMA controller through the DMA request signal to obtain DMA interaction data;

and the DMA interaction data transmitting module is used for transmitting the DMA interaction data to the host equipment under the condition that the handshake process with the host equipment is determined to be completed.

According to another aspect of the present invention, there is provided a slave device including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the data transmission method according to any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute a data transmission method according to any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a data transmission system including a master device, a slave device, and an I2C bus; the host device is in communication connection with the slave device through the I2C bus, and the slave device is in Clk No strech Mode; wherein: the host device is configured to:

transmitting a slave device address signal to the slave device to perform a handshake procedure with the slave device through the slave device address signal;

the slave device is used for responding to the target interaction indication signal and initiating a DMA request signal to the local DMA controller; wherein the target interaction indication signal comprises an address matching signal or an IRQ signal; the address matching signal is triggered at the time of the falling edge of the last address pulse signal sent by the host equipment in the I2C communication system;

And sending the DMA interaction data to the host device through the I2C bus under the condition that the handshake process with the host device is determined to be completed.

According to the embodiment of the invention, the slave device in Clk No strech Mode responds to the address matching signal or the IRQ signal and other types of target interaction indicating signals, a DMA request signal is initiated to the local DMA controller, so that data interaction is carried out between the local DMA controller and the DMA request signal to obtain DMA interaction data, and the obtained DMA interaction data is sent to the host device after the handshake process with the host device is determined. The address matching signal is triggered by the slave device at the time of the falling edge of the last address pulse signal sent by the host device in the I2C communication system, and the triggering time of the address matching signal is earlier than the triggering time of the existing address matching signal. The IRQ signal can be triggered at any time according to the data interaction requirement of the slave machine, and is not limited by the triggering limitation of the address matching signal. Therefore, the speed of acquiring DMA interactive data by the slave device can be improved by triggering the target interactive indication signal in advance, so that the problem of poor data communication quality between the master device and the slave device in Clk No strech Mode state in the existing I2C-based data transmission system is solved, the robustness of I2C data communication can be improved, and the data transmission quality between the master device and the slave device in the I2C-based data transmission system is further improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a data transmission method according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of an I2C-based data transmission system according to a first embodiment of the present invention;

fig. 3 is a schematic flow chart of data communication between a host device and a slave device in an I2C-based data transmission system according to a first embodiment of the present invention;

FIG. 4 is a schematic diagram showing the effect of the cooperation between an I2C bus interface and a DMA of a slave device in the prior art;

FIG. 5 is a schematic diagram illustrating the effect of the I2C bus interface and the DMA of the slave device according to the first embodiment of the present invention;

Fig. 6 is a flowchart of a data transmission method according to a second embodiment of the present invention;

fig. 7 is a schematic diagram of a matching effect between an I2C bus interface and a DMA of a slave device according to a second embodiment of the present invention;

fig. 8 is a schematic diagram of a data transmission device according to a third embodiment of the present invention;

fig. 9 is a schematic structural diagram of a data transmission system according to a fourth embodiment of the present invention;

fig. 10 is a schematic structural diagram of a slave device according to a fifth embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the term "object" and the like in the description of the present invention and the claims and the above drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of a data transmission method provided in an embodiment of the present invention, where the embodiment is applicable to a case where a slave device in an I2C-based data transmission system obtains DMA interaction data according to an address matching signal or an IRQ signal and performs data transmission with a host, the method may be performed by a data transmission device, and the device may be implemented by software and/or hardware, and may be generally integrated in the slave device, where the slave device may be a terminal device or a server device of various types, and is used in cooperation with a host device in an I2C-based data transmission system, and the embodiment of the present invention does not limit a specific device type of the slave device. Accordingly, as shown in fig. 1, the method includes the following operations:

s110, responding to a target interaction indication signal, and initiating a DMA request signal to a local DMA controller; wherein the target interaction indication signal comprises an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge time of the last address pulse signal sent by the host device in the I2C communication system.

The target interaction indication signal may be a signal for indicating the slave device to interact with the local DMA control. Optionally, the target interaction indication signal may be a software-triggered signal or a hardware-triggered signal, so long as the target interaction indication signal can be used to indicate the slave device to interact with the local DMA control, and the signal type of the target interaction indication signal is not limited in the embodiment of the present invention. The local DMA controller, i.e. the DMA controller in the slave device performing the data transfer method, may perform DMA operations providing a high speed data transfer between the peripheral and the memory of the slave device or between the memory and the memory of the slave device. The DMA request signal may be used to instruct the start of a handshake with the native DMA controller and to retrieve interaction data. The address pulse signal, i.e. the address signal sent by the master device to the slave device, may be used to perform a handshake procedure with the slave device.

Fig. 2 is a schematic structural diagram of an I2C-based data transmission system according to a first embodiment of the present invention, and fig. 3 is a schematic flow chart of data communication between a host device and a slave device in the I2C-based data transmission system according to the first embodiment of the present invention. In a specific example, as shown in fig. 1 and fig. 2, the technical solution of the embodiment of the present invention is mainly applicable to such an application scenario: in an I2C-based data transmission system, a master device (Host) and Slave devices (Slave) are communicatively connected via an I2C bus. Wherein the number of slave devices may be one or more. All SDA (Serial Data Line) lines of all master and slave devices are connected on one Line, and the devices occupy the common Data Line in a time sharing way so as to realize Data transmission between every two devices. Thus, SDA conforms to the characteristics of a data bus. All the SCL (Serial Clock Line ) lines of the master and slave devices are connected on one line, and occupy the common clock line in a time sharing way so as to realize the mutual transmission clocks. Thus, SCL conforms to the characteristics of a clock bus.

As shown in fig. 3, when the slave device is in Clk Nostrech Mode state, the master device M0 may first send the corresponding slave address to the target slave device before initiating a read data request to the slave device, to complete a handshake process with the target slave device. After the host device and the target slave device complete the handshake process, the host device M0 may initiate a read data request to the target slave device in the state Clk Nostrech Mode. The target slave device handshakes with the local DMA controller in response to the read data request. After the target slave device completes the handshake process with the DMA controller, the data sent by the DMA controller may be acquired, and the acquired data may be fed back to the host device M0. It follows that the status of the slave DMA will affect the correctness of the data received by the host device M0. In practical applications, the product will choose the slave Clk Nostrech Mode to keep the communication efficiency, so the I2C bus in the I2C-based data transmission system needs to have high robustness, otherwise the communication efficiency and communication quality between the master and slave devices will be seriously affected.

Fig. 4 is a schematic diagram showing the matching effect between an I2C bus interface and a DMA of a slave device in the prior art. Taking the 7-bit address mode in I2C as an example, a waveform diagram of the current I2C in cooperation with a slave DMA controller to obtain slave data and turn on data transmission is shown in fig. 4. As shown in fig. 4, in the related art, after the master device completes the handshake with the slave address pulse signals A0 to A6 transmitted from the slave device through the master device, the master device transmits a W/R signal (read/write flag signal) to the slave device. The W/R signal may represent the type of interaction that the host device has with the slave device, such as reading data from the slave device or writing data to the slave device, etc. Correspondingly, when the slave device detects the rising edge of the W/R signal, the slave device triggers the generation of an address matching signal, namely an addr_match signal, which indicates that the handshake process is confirmed to be completed with the host device, and the slave device can start to interact with the local DMA control. After the slave device triggers the generation of the addr_match signal, a handshake process with the local DMA controller is started, and a DMA request signal, i.e., a dma_tx_req signal, is sent to the local DMA controller. Correspondingly, after receiving the dma_tx_req signal, the DMA controller of the slave device may feed back a dma_tx_ack signal to the slave device, which indicates that the DMA confirms that the DMA request signal is received, and may perform data interaction with the slave device, where the slave device completes a handshake process with the local DMA controller. After the slave device and the local DMA controller complete the handshake process, the slave device can acquire the interactive data of the local DMA controller and fill the sending buffer memory for sending to the host device.

As can be seen from fig. 4, in the current I2C-based data transmission system, the system reserves less than 1 SCL for the handshake process between the slave device and the local DMA, and if the dma_tx_req is not responded to by the DMA controller of the slave device in time, the first few bits of the first byte of data will be lost by the slave device, and the whole byte will be lost in severe cases, thereby affecting the communication quality between the slave device and the host device.

In order to solve the problems, the embodiment of the invention advances the time for triggering the interaction between the slave device and the local DMA controller. Specifically, the slave device may trigger generation of an address matching signal or an IRQ signal as the target interaction indication signal. When the address matching signal, i.e., the addr_match signal, is used as the target interaction indication signal, the generation of the address matching signal may be triggered in advance, for example, the generation of the address matching signal may be triggered at the time of the falling edge of the last address pulse signal sent by the host device, instead of triggering the generation of the address matching signal after the W/R signal is sent by the host device, so that the triggering time of the address matching signal may be processed in advance. When the IRQ signal is adopted as the target interaction indication signal, the host equipment can trigger to generate the IRQ signal at any time according to the requirement, and the IRQ signal is not limited by a handshake process with the host equipment and a detection process of the W/R signal.

In an optional embodiment of the invention, if the target interaction indication signal includes the address matching signal, before initiating a DMA request signal to the local DMA controller in response to the target interaction indication signal, the method may further include: detecting the moment when the last address pulse signal sent by the host equipment is converted from a high-level signal to a low-level signal; and triggering to generate the address matching signal when detecting that the last address pulse signal sent by the host equipment is converted from a high-level signal to a low-level signal.

Fig. 5 is a schematic diagram of a matching effect between an I2C bus interface and a DMA of a slave device according to a first embodiment of the present invention. As shown in fig. 5, alternatively, if the slave device selects the address matching signal as the target interaction indication signal, the slave device may detect signal information sent by the host device in real time, so as to trigger generation of the address matching signal by means of software. The slave device, upon detecting that the host device starts transmitting the address pulse signal, starts preparing to trigger generation of the address matching signal. Specifically, after the slave device detects that the host device has sent all address pulse signals, determining the moment when the last address pulse signal sent by the host device is converted from a high level signal to a low level signal, namely determining the falling edge moment of the last address pulse signal sent by the host device, and triggering to generate an address matching signal in the form of software at the moment. In this case, the trigger timing of the address matching signal is advanced from the rising edge timing of the read-write flag signal to the falling edge timing of the last address pulse signal. Because the address matching signal is triggered and generated in advance, the interaction time of the slave device and the local DMA controller is correspondingly advanced, correspondingly, the interaction time reserved for the slave device and the local DMA controller by the data communication system is prolonged, and the time for preparing DMA interaction data by the slave device is more abundant.

In an optional embodiment of the invention, if the target interaction indication signal includes the address matching signal, the initiating, in response to the target interaction indication signal, a DMA request signal to the local DMA controller may include: reading internal configuration information to obtain a preset signal trigger interval duration between the address matching signal and the DMA request signal; determining a trigger time of a rising edge of the address matching signal in response to the address matching signal; calculating the current trigger time length of the address matching signal by taking the trigger time of the rising edge of the address matching signal as a reference; and under the condition that the current trigger time length of the address matching signal reaches the trigger interval time length of the preset signal, initiating the DMA request signal to the local DMA controller.

The preset signal trigger interval duration may be an interval duration between a trigger time of the address matching signal and a trigger time of the DMA request signal. The current trigger time period may be a statistical time period after the address matching signal is triggered.

In the embodiment of the invention, when the address matching signal is triggered in a software form, in order to further prolong the interaction time reserved for the slave device and the local DMA controller by the data communication system, the time for triggering the slave device to interact with the local DMA controller according to the address matching signal can be configured as required. Specifically, before the slave device interacts with the host device, a user may configure internal configuration information of the slave device, determine parameters of a preset signal trigger interval duration between the address matching signal and the DMA request signal, and modify parameters of the preset signal trigger interval duration as required.

As shown in fig. 5, the minimum value of the preset signal trigger interval duration, that is, can be 0, which means that the slave device can start to handshake with the local DMA controller while the address matching signal is triggered. The maximum value of the preset signal triggering interval duration cannot exceed 2.5 SCLs, so that the handshake failure caused by too short duration reserved for the slave device and the local DMA controller is avoided, and further interaction failure between the slave device and the local DMA is caused. If the user does not configure the preset signal trigger interval duration, the preset signal trigger interval duration can take a default value.

Correspondingly, in the communication process, the slave device can read the internal configuration information to acquire the preset signal trigger interval duration between the address matching signal and the DMA request signal. When the slave device also detects the address matching signal, the trigger time of the rising edge of the address matching signal can be determined, the trigger time of the rising edge of the address matching signal is taken as the trigger time starting point, and the accumulated time length of the address matching signal from the trigger time starting point is calculated as the current trigger time length. Meanwhile, the slave equipment calculates whether the current trigger time length reaches the preset signal trigger interval time length or not in real time. If the slave device determines that the current trigger time length of the address matching signal reaches the preset signal trigger interval time length, the slave device can start to initiate a DMA request signal to the local DMA controller so as to start executing a handshake process with the local DMA controller.

According to the technical scheme, the address matching signal is modified in a software mode, so that the address matching signal is advanced to the falling edge of the last address pulse signal sent by the host equipment, meanwhile, the interval time between the address matching signal and the DMA request signal is configured according to the requirement, the DMA request of the slave equipment can finish the filling preparation work of the DMA interaction data in the ACK stage of the last address pulse signal to the reply host equipment, the DMA and the slave equipment are mutually handshaked in advance by means of the address matching signal, the fetch margin of the DMA interaction data is improved from 1 SCL to 2.5 SCL which is selectable, therefore, enough data interaction time between the slave equipment and a local DMA controller is ensured, the stability and reliability of the slave equipment for processing the DMA interaction data are improved, the robustness of I2C data communication is further improved, and the data transmission quality between the master equipment and the slave equipment is improved.

In an alternative embodiment of the present invention, if the target interaction indication signal includes the IRQ signal, before initiating a DMA request signal to the local DMA controller in response to the target interaction indication signal, the method may further include: detecting a native device state or software event by a device driver or native operating system kernel; and triggering to generate the IRQ signal under the condition that the state of the local equipment is determined to be the state of the target equipment or the generation of the target software event is determined.

And S120, performing data interaction with the local DMA controller through the DMA request signal to obtain DMA interaction data.

The DMA interaction data may be data obtained after interaction between the slave device and the DMA controller.

S130, sending the DMA interaction data to the host equipment under the condition that the handshake process is completed with the host equipment is determined.

Accordingly, after the slave device initiates a DMA request signal to the local DMA controller, a handshake process with the local DMA controller may be started, and after the handshake process with the local DMA controller is completed, data interacting with the DMA may be obtained. After the slave device acquires the DMA interaction data, the DMA interaction data may be filled into the transmission buffer and a handshake process with the host device needs to be waited. If the slave device determines that the handshake process is completed with the host device, the DMA interaction data stored in the transmit buffer may be transmitted to the host device.

Optionally, the data transmission method can be applied to NFC (Near Field Communication ) products and can be applied to application scenarios of speed-up BootLoader and interface communication.

Example two

Fig. 6 is a flowchart of a data transmission method according to a second embodiment of the present invention, where on the basis of the foregoing embodiment, the embodiment of the present invention specifically describes an overall flow of the data transmission method by taking an IRQ signal as a target interaction indication signal as an example. Accordingly, as shown in fig. 6, the method of this embodiment may include:

s210, detecting a state of a local device or a software event through a device driver or a kernel of a local operating system.

S220, triggering to generate the IRQ signal under the condition that the state of the local equipment is determined to be the state of the target equipment or the generation of the target software event is determined.

The target device state and the target software event can be set according to a specific application scenario or service requirement of the data transmission system based on the I2C. For example, when a slave device is used to monitor temperature, the target software event may be the monitored temperature reaching an early warning temperature value. When the slave device detects that the local memory is about to be full, the state of the local memory about to overflow can be used as the state of the target device.

The present scheme of using the address matching signal as the target interaction indication signal is only suitable for application scenarios in which the slave device passively feeds back data to the host device when the host device sends a data request to the slave device, and the application field range is limited. In many application scenarios, such as a monitoring scenario, a detection scenario, or a safety protection scenario, the slave device often needs to report to the host device in real time according to the collected information, so that the host device immediately makes a corresponding decision according to the information reported in real time. For example, when the slave device monitors that the current temperature reaches the early warning temperature value, the slave device needs to report the alarm information to the host device in real time, or when the slave device detects malicious attack data, the slave device reports the alarm information to the host device in real time, and the like.

In the application scenario that the host device needs to report information in real time, if the address matching signal is used as the target interaction indication signal, the slave device can only wait for the falling edge of the last address pulse signal sent by the host device to trigger the address matching signal, which causes a certain delay problem and cannot guarantee the instantaneity of reporting information. In order to solve the problem and expand the application field range of the data transmission method, the embodiment of the invention newly configures the IRQ signal to the slave device independently, so that when the slave device needs to actively report information to the host device in real time, a target interaction indication signal is generated by triggering the IRQ signal, and a DMA request signal is initiated to a local DMA controller in response to the target interaction indication signal generated by triggering in real time.

In the embodiment of the invention, the target interaction indication signal can be generated for the slave device in a mode of triggering the IRQ signal by hardware. Optionally, in a scenario that the slave device actively reports data to the host device in real time, an IRQ pin may be added to the slave device configuration, and the slave device monitors the state of the slave device in real time through an internal device driver or a local operating system kernel, and if the slave device detects that the current state of the slave device is the target device state through the internal device driver or the local operating system kernel, or detects that the slave device generates a target software event, the slave device may actively trigger a hardware interrupt through the internal device driver or the local operating system kernel, so as to generate an IRQ signal. When the slave device detects the IRQ signal, the IRQ signal can be used as a target interaction indication signal, the trigger time of the IRQ signal is used as a reference, a DMA request signal is triggered and generated according to a default time sequence, the DMA request signal is sent to the local DMA controller, and a handshake process is started to be executed with the local DMA controller.

Fig. 7 is a schematic diagram of the matching effect between an I2C bus interface and a DMA of a slave device according to a second embodiment of the present invention. As shown in fig. 7, when the slave device needs to actively report data to the host device, the slave device may trigger a hardware interrupt, and the new IRQ signal records the current time when the slave device requests the host device to receive the data. When the slave device detects the newly added IRQ signal, a DMA request signal may be initiated to the local DMA controller according to a default time sequence, i.e. a Config stage shown in fig. 7, so that the DMA request may acquire interactive data of the local DMA controller and fill a transmission buffer before the address pulse signal of the host device is transmitted after the rising edge of the IRQ, so as to be ready for transmission to the host device.

S230, responding to the IRQ signal, and initiating a DMA request signal to the local DMA controller.

S240, performing data interaction with the local DMA controller through the DMA request signal to obtain DMA interaction data.

S250, sending the DMA interaction data to the host device under the condition that the handshake process is completed with the host device.

Accordingly, after the slave device initiates a DMA request signal to the local DMA controller, a handshake process with the local DMA controller may be started, and after the handshake process with the local DMA controller is completed, data interacting with the DMA may be obtained. After the slave device acquires the DMA interaction data, the DMA interaction data may be filled into the transmission buffer and a handshake process with the host device needs to be waited. If the slave device determines that the handshake process is completed with the host device, the DMA interaction data stored in the transmission buffer may be transmitted to the host device in real time.

Optionally, the data transmission method can be applied to NFC series products and can be applied to application scenes of acceleration BootLoader and interface communication.

According to the technical scheme, the IRQ signal is newly added in a hardware mode, so that the DMA request of the slave device can complete the filling preparation work of the DMA interaction data in the period from the address pulse signal sending to the reply of the ACK of the host device, the DMA and the slave device are mutually handshaking in real time by means of the customized signal, and under the 7-bit address mode of I2C, the fetch margin of the DMA interaction data can be improved from 1 SCL to 9 SCL. In the case of the 10-bit address mode of I2C, the fetch margin of the DMA transaction data may be increased from 1 SCL to 18 SCL. Therefore, the method can ensure enough data interaction time between the slave device and the local DMA controller in a mode of adding the IRQ signal by hardware, improve the instantaneity, stability and reliability of the slave device for processing the DMA interaction data, further improve the robustness of I2C data communication, and improve the data transmission quality and instantaneity of data transmission between the master device and the slave device.

According to the embodiment of the invention, the slave device in Clk No strech Mode responds to the target interaction indication signal of the IRQ signal type, initiates a DMA request signal to the local DMA controller, so that data interaction is carried out between the local DMA controller and the DMA request signal to obtain DMA interaction data, and the obtained DMA interaction data is sent to the host device after the handshake process with the host device is determined. The IRQ signal can be triggered at any time according to the data interaction requirement of the slave machine, and is not limited by the triggering limitation of the address matching signal. Therefore, the speed of acquiring DMA interactive data by the slave device can be improved by triggering the target interactive indication signal in advance, so that the problem of poor data communication quality between the master device and the slave device in Clk No strech Mode state in the existing I2C-based data transmission system is solved, the robustness of I2C data communication can be improved, and the data transmission quality and the real-time performance of data transmission between the master device and the slave device in the I2C-based data transmission system are further improved.

Example III

Fig. 8 is a schematic diagram of a data transmission apparatus according to a third embodiment of the present invention, where the apparatus is configured in a slave device in an I2C-based data transmission system, and the slave device is located in Clk No strech Mode, as shown in fig. 8, and the apparatus includes: a DMA request signal initiation module 310, a DMA interactive data acquisition module 320, and a DMA interactive data transmission module 330, wherein:

a DMA request signal initiation module 310, configured to initiate a DMA request signal to a local DMA controller in response to a target interaction indication signal; wherein the target interaction indication signal comprises an address matching signal or an IRQ signal; the address matching signal is triggered at the time of the falling edge of the last address pulse signal sent by the host equipment in the I2C communication system;

the DMA interaction data acquisition module 320 is configured to perform data interaction with the local DMA controller through the DMA request signal, so as to obtain DMA interaction data;

and the DMA interaction data sending module 330 is configured to send the DMA interaction data to the host device if it is determined that the handshake process is completed with the host device.

Optionally, if the target interaction indication signal includes the address matching signal, the data transmission device may further include an address matching signal generating module, configured to: detecting the moment when the last address pulse signal sent by the host equipment is converted from a high-level signal to a low-level signal; and triggering to generate the address matching signal when detecting that the last address pulse signal sent by the host equipment is converted from a high-level signal to a low-level signal.

Optionally, if the target interaction indication signal includes the address matching signal, the DMA request signal initiation module 310 is specifically configured to: reading internal configuration information to obtain a preset signal trigger interval duration between the address matching signal and the DMA request signal; determining a trigger time of a rising edge of the address matching signal in response to the address matching signal; calculating the current trigger time length of the address matching signal by taking the trigger time of the rising edge of the address matching signal as a reference; and under the condition that the current trigger time length of the address matching signal reaches the trigger interval time length of the preset signal, initiating the DMA request signal to the local DMA controller.

Optionally, if the target interaction indication signal includes the IRQ signal, the data transmission apparatus may further include an IRQ signal generating module configured to: detecting a native device state or software event by a device driver or native operating system kernel; and triggering to generate the IRQ signal under the condition that the state of the local equipment is determined to be the state of the target equipment or the generation of the target software event is determined.

The data transmission device can execute the data transmission method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment may be referred to the data transmission method provided in any embodiment of the present invention.

Since the data transmission device described above is a device capable of executing the data transmission method in the embodiment of the present invention, based on the data transmission method described in the embodiment of the present invention, those skilled in the art can understand the specific implementation of the data transmission device in the embodiment of the present invention and various modifications thereof, so how the data transmission device implements the data transmission method in the embodiment of the present invention will not be described in detail herein. The apparatus used to implement the data transmission method in the embodiments of the present invention falls within the scope of protection intended by the present application.

Example IV

Fig. 9 is a schematic structural diagram of a data transmission system according to a fourth embodiment of the present invention, and as shown in fig. 9, the structure of the data transmission system includes: a master device 410, a slave device 420, and an I2C bus 430; the master device 410 is communicatively coupled to the slave device 420 via the I2C bus 430, the slave device 420 being at Clk No strech Mode; wherein:

the host device 410 is configured to: the slave device address signal is sent to the slave device 420 to perform a handshake procedure with the slave device 420 via the slave device address signal.

The slave device address signal may be an address pulse signal.

The slave device 420 is configured to initiate a DMA request signal to the local DMA controller in response to the target interaction indication signal; wherein the target interaction indication signal comprises an address matching signal or an IRQ signal; the address matching signal is triggered at the time of the falling edge of the last address pulse signal sent by the host equipment in the I2C communication system; performing data interaction with the local DMA controller through the DMA request signal to obtain DMA interaction data; in the event that it is determined that the handshake process is completed with the host device 410, the DMA interaction data is sent to the host device 410 over the I2C bus 430.

Optionally, if the target interaction indication signal includes the address matching signal, the slave device 410 may be further configured to: detecting the moment when the last address pulse signal sent by the host equipment is converted from a high-level signal to a low-level signal; and triggering to generate the address matching signal when detecting that the last address pulse signal sent by the host equipment is converted from a high-level signal to a low-level signal.

Optionally, if the target interaction indication signal includes the address matching signal, the slave device 410 may be further configured to: reading internal configuration information to obtain a preset signal trigger interval duration between the address matching signal and the DMA request signal; determining a trigger time of a rising edge of the address matching signal in response to the address matching signal; calculating the current trigger time length of the address matching signal by taking the trigger time of the rising edge of the address matching signal as a reference; and under the condition that the current trigger time length of the address matching signal reaches the trigger interval time length of the preset signal, initiating the DMA request signal to the local DMA controller.

Optionally, if the target interaction indication signal includes the IRQ signal, the slave device 410 may be further configured to: detecting a native device state or software event by a device driver or native operating system kernel; and triggering to generate the IRQ signal under the condition that the state of the local equipment is determined to be the state of the target equipment or the generation of the target software event is determined.

In the embodiment of the invention, a data transmission system is formed by a host device, a slave device and an I2C bus, wherein the host device and the slave device are in communication connection through the I2C bus, and the slave device is in Clk No strech Mode. Correspondingly, the slave device in Clk No strech Mode responds to the address matching signal or the IRQ signal and other types of target interaction indicating signals, initiates a DMA request signal to the local DMA controller, so that data interaction is carried out between the DMA request signal and the local DMA controller to obtain DMA interaction data, and further, after the handshake process with the host device is confirmed, the obtained DMA interaction data is sent to the host device, the problem that the data communication quality between the master device and the slave device in Clk No strech Mode states in the existing I2C-based data transmission system is poor is solved, the robustness of I2C data communication can be improved, and the data transmission quality between the master device and the slave device in the I2C-based data transmission system is improved.

The slave device in the data transmission system can execute the data transmission method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment may be referred to the data transmission method provided in any embodiment of the present invention.

Since the slave device in the above-described data transmission system is a device capable of executing the data transmission method in the embodiment of the present invention, based on the data transmission method described in the embodiment of the present invention, those skilled in the art can understand the specific implementation of the data transmission system in the embodiment of the present invention and various modifications thereof, so how the slave device in the data transmission system implements the data transmission method in the embodiment of the present invention will not be described in detail herein. As long as those skilled in the art implement the slave devices in the data transmission system used in the data transmission method in the embodiment of the present invention, all slave devices are within the scope of protection intended in the present application.

It should be noted that any permutation and combination of the technical features in the above embodiments also belong to the protection scope of the present invention.

Example five

Fig. 10 shows a schematic diagram of a slave device 10 that may be used to implement an embodiment of the present invention. Slave devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The slave device may also represent various forms of mobile apparatus, such as personal digital processing, cellular telephones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 10, the slave device 10 includes at least one processor 11, and a memory such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the slave device 10 can also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

The various components in the slave device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the slave device 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the data transmission method.

Optionally, the data transmission method is applied to a slave device in the I2C-based data transmission system, where the slave device is in a clock non-extended mode Clk No strech Mode; the method comprises the following steps:

responding to the target interaction indication signal, and initiating a DMA request signal to a local DMA controller; wherein the target interaction indication signal comprises an address matching signal or an interrupt request IRQ signal; the address matching signal is triggered at the time of the falling edge of the last address pulse signal sent by the host equipment in the I2C communication system;

In some embodiments, the data transmission method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the slave device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the data transmission method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the data transmission method in any other suitable way (e.g. by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a slave device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or a trackball) by which a user can provide input to the slave device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

Claims

1. A data transmission method, characterized in that the method is applied to a slave device in an I2C-based data transmission system, the slave device is in a clock non-expansion mode Clk No strech Mode; the method comprises the following steps:

2. The method of claim 1, wherein if the target-interaction-indication signal comprises the address-match signal, prior to initiating a DMA request signal to a local DMA controller in response to the target-interaction-indication signal, further comprising:

detecting the moment when the last address pulse signal sent by the host equipment is converted from a high-level signal to a low-level signal;

and triggering to generate the address matching signal when detecting that the last address pulse signal sent by the host equipment is converted from a high-level signal to a low-level signal.

3. The method according to claim 1 or 2, wherein if the target-interaction-indication signal comprises the address-matching signal, the initiating a DMA-request signal to a local DMA controller in response to the target-interaction-indication signal comprises:

reading internal configuration information to obtain a preset signal trigger interval duration between the address matching signal and the DMA request signal;

determining a trigger time of a rising edge of the address matching signal in response to the address matching signal;

Calculating the current trigger time length of the address matching signal by taking the trigger time of the rising edge of the address matching signal as a reference;

and under the condition that the current trigger time length of the address matching signal reaches the trigger interval time length of the preset signal, initiating the DMA request signal to the local DMA controller.

4. The method of claim 1, wherein if the target-interaction-indication signal comprises the IRQ signal, prior to initiating a DMA request signal to a local DMA controller in response to the target-interaction-indication signal, further comprising:

detecting a native device state or software event by a device driver or native operating system kernel;

and triggering to generate the IRQ signal under the condition that the state of the local equipment is determined to be the state of the target equipment or the generation of the target software event is determined.

5. A data transmission apparatus, characterized by a slave device configured in an I2C-based data transmission system, the slave device being at Clk No strech Mode; the device comprises:

6. A slave device, the slave device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the data transmission method of any one of claims 1-4.

7. A data transmission system, comprising a master device, a slave device and an I2C bus; the host device is in communication connection with the slave device through the I2C bus, and the slave device is in Clk No strech Mode; wherein: the host device is configured to:

8. The system of claim 7, wherein if the target interaction indication signal comprises the address match signal, the slave device is further configured to:

9. The system of claim 7 or 8, wherein if the target interaction indication signal comprises the address match signal, the slave device is further configured to:

10. A computer readable storage medium storing computer instructions for causing a processor to perform the data transmission of any one of claims 1-4 when executed.