CN219574798U - BIOS chip and BMC chip data exchange device, mainboard and server - Google Patents
BIOS chip and BMC chip data exchange device, mainboard and server Download PDFInfo
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- CN219574798U CN219574798U CN202321229147.9U CN202321229147U CN219574798U CN 219574798 U CN219574798 U CN 219574798U CN 202321229147 U CN202321229147 U CN 202321229147U CN 219574798 U CN219574798 U CN 219574798U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model belongs to the technical field of BIOS chips and BMC chips, and particularly provides a data exchange device of the BIOS chips and the BMC chips, a main board and a server, wherein the device comprises a host and the BMC chips, and the host is respectively connected with the BIOS chips and an intermediate Flash through a first selection switch; the intermediate Flash comprises a BIOS data storage area and a BMC data storage area, wherein the BIOS chip and the BMC chip are connected through IPMI communication, and the BMC chip and the intermediate Flash are connected through SPI signal lines. And directly taking the intermediate Flash as a Dynamic area of the BIOS chip to store configuration, and recovering the configuration through the area at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
Description
Technical Field
The utility model relates to the technical field of BIOS chips and BMC chips, and particularly provides a device for exchanging data between a BIOS chip and a BMC chip, a mainboard and a server.
Background
BIOS is an abbreviation of Basic Input Output System, meaning a basic input output system, which is a chip used for initializing and detecting various hardware devices during a computer booting process, and the BIOS chip mostly adopts a package in a DIP (dual in-line) form. Some of them use packaging in the form of PLCCs for space saving. The BIOS on notebook computers mostly adopts SOJ packaging. And the BIOS chip is convenient to replace.
BMC (Baseboard management controller) the remote management controller of the execution server is a baseboard management controller, is a small operating system independent of the server system, is a chip integrated on the main board, and also has a product which is inserted on the main board in a PCIE (peripheral component interconnect express) mode, is only a standard RJ45 network port in external expression mode, and has a firmware system of independent IP (Internet protocol). Server clusters typically use BMC instructions for large-scale unattended operations, including remote management, monitoring, installation, restarting, etc. of servers. IPMI is an on-board component which can independently run outside the CPU, BIOS/UEFI and OS of the host system, and the core component is BMC. Alternatively, BMC interaction with other components, such as BIOS/UEFI, CPU, etc., is accomplished via IPMI. With the help of IPMI, a user can remotely start, reload, mount an ISO mirror and the like on a closed server.
The existing data communication between the BIOS chip and the BMC chip of the server is mostly based on an IPMI protocol, the host BIOS chip and the BMC chip are communicated by using an interactive interface of the BMC chip, the data transmission speed of the communication mode is slow, and the transceiving communication mode has a certain interference on decoupling of the BIOS chip and the BMC chip.
Disclosure of Invention
The existing data communication between the BIOS chip and the BMC chip of the server is mostly based on an IPMI protocol, the host BIOS chip and the BMC chip are communicated by using an interactive interface of the BMC chip, the data transmission speed of the communication mode is slow, and the transceiving communication mode has a certain interference on decoupling of the BIOS chip and the BMC chip. The utility model provides a BIOS chip and BMC chip data exchange device, a mainboard and a server.
In a first aspect, the utility model provides a device for exchanging data between a BIOS chip and a BMC chip, comprising a host and the BMC chip, wherein the host is respectively connected with the BIOS chip and an intermediate Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
As the preference of the utility model, the BMC chip is connected with the intermediate Flash through an SPI signal line.
Preferably, the intermediate Flash comprises a BIOS data storage area and a BMC data storage area.
Preferably, the BIOS chip and the BMC chip are connected through IPMI communication.
Preferably, the first selection switch is an SPI selection chip. And directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
The utility model provides a mainboard for realizing data exchange between a BIOS chip and a BMC chip, which comprises a mainboard body, wherein a host and the BMC chip are arranged on the mainboard body, and the host is respectively connected with the BIOS chip and an intermediate Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
As the preference of the utility model, the BMC chip is connected with the intermediate Flash through an SPI signal line.
Preferably, the intermediate Flash comprises a BIOS data storage area and a BMC data storage area.
Preferably, the BIOS chip and the BMC chip are connected through IPMI communication.
Preferably, the first selection switch is an SPI selection chip.
As the optimization of the utility model, the main board body is also provided with a CPLD chip and a PCH chip which are connected with the BMC chip; the BMC chip is also connected with a second selection switch through the expansion board, and the second selection switch is connected with the PCH chip;
the second selection switch is also connected with a first BIOS Flash and a second BIOS Flash. And directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
The utility model provides a server for realizing data exchange between a BIOS chip and a BMC chip, which comprises a main board body, wherein a host and the BMC chip are arranged on the main board body, and the host is respectively connected with the BIOS chip and an intermediate Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
As the preference of the utility model, the BMC chip is connected with the intermediate Flash through an SPI signal line.
Preferably, the intermediate Flash comprises a BIOS data storage area and a BMC data storage area.
Preferably, the BIOS chip and the BMC chip are connected through IPMI communication.
Preferably, the first selection switch is an SPI selection chip.
As the optimization of the utility model, the main board body is also provided with a CPLD chip and a PCH chip which are connected with the BMC chip; the BMC chip is also connected with a second selection switch through the expansion board, and the second selection switch is connected with the PCH chip;
the second selection switch is also connected with a first BIOS Flash and a second BIOS Flash. And directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
From the above technical scheme, the utility model has the following advantages: and directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
In addition, the utility model has reliable design principle, simple structure and very wide application prospect.
It can be seen that the present utility model has outstanding substantial features and significant advances over the prior art, as well as its practical advantages.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic block diagram of an apparatus of one embodiment of the utility model.
Detailed Description
The existing data communication between the BIOS chip and the BMC chip of the server is mostly based on an IPMI protocol, the host BIOS chip and the BMC chip are communicated by using an interactive interface of the BMC chip, the data transmission speed of the communication mode is slow, and the transceiving communication mode has a certain interference on decoupling of the BIOS chip and the BMC chip.
In order to make the technical solution of the present utility model better understood by those skilled in the art, the technical solution of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.
As shown in fig. 1, an embodiment of the present utility model provides a device for exchanging data between a BIOS chip and a BMC chip, including a host and a BMC chip, where the host is connected to the BIOS chip and an intermediate Flash through a first selection switch respectively;
the intermediate Flash is connected with the BMC chip.
And directly taking the intermediate Flash as a Dynamic area of the BIOS chip to store configuration, and recovering the configuration through the area at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced. It should be noted that, in the embodiment of the present utility model, the host is a CPU.
The embodiment of the utility model provides a device for exchanging data between a BIOS chip and a BMC chip, which comprises a host and the BMC chip, wherein the host is respectively connected with the BIOS chip and an intermediary Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
The BMC chip is connected with the intermediate Flash through an SPI signal line.
The intermediate Flash comprises a BIOS data storage area and a BMC data storage area.
The BIOS chip and the BMC chip are connected through IPMI communication.
An intermediary Flash is added on the main board, and the host is connected with the BIOS chip and the intermediary Flash through a first selection switch; the BMC chip is also connected with the intermediate Flash through SPI, and respectively stores data which need to be synchronized into the intermediate Flash through a data format protocol regulated between the BIOS chip and the BMC chip, when the data need to be read, the BIOS chip and the BMC chip respectively read the needed content from different areas of the intermediate Flash, and the BIOS chip and the BMC chip confirm whether the other party uses the intermediate Flash or not through IPMI interaction mode.
The first selection switch is an SPI selection chip. And directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
The utility model provides a main board for realizing data exchange between a BIOS chip and a BMC chip, which comprises a main board body, wherein a host and the BMC chip are arranged on the main board body, and the host is respectively connected with the BIOS chip and an intermediate Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
The BMC chip is connected with the intermediate Flash through an SPI signal line.
The intermediate Flash comprises a BIOS data storage area and a BMC data storage area.
The BIOS chip and the BMC chip are connected through IPMI communication.
An intermediary Flash is added on the main board, and the host is connected with the BIOS chip and the intermediary Flash through a first selection switch; the BMC chip is also connected with the intermediate Flash through SPI, and respectively stores data which need to be synchronized into the intermediate Flash through a data format protocol regulated between the BIOS chip and the BMC chip, when the data need to be read, the BIOS chip and the BMC chip respectively read the needed content from different areas of the intermediate Flash, and the BIOS chip and the BMC chip confirm whether the other party uses the intermediate Flash or not through IPMI interaction mode. And directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
The utility model provides a main board for realizing data exchange between a BIOS chip and a BMC chip, which comprises a main board body, wherein a host and the BMC chip are arranged on the main board body, and the host is respectively connected with the BIOS chip and an intermediate Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
The BMC chip is connected with the intermediate Flash through an SPI signal line.
The intermediate Flash comprises a BIOS data storage area and a BMC data storage area.
The BIOS chip and the BMC chip are connected through IPMI communication.
An intermediary Flash is added on the main board, and the host is connected with the BIOS chip and the intermediary Flash through a first selection switch; the BMC chip is also connected with the intermediate Flash through SPI, and respectively stores data which need to be synchronized into the intermediate Flash through a data format protocol regulated between the BIOS chip and the BMC chip, when the data need to be read, the BIOS chip and the BMC chip respectively read the needed content from different areas of the intermediate Flash, and the BIOS chip and the BMC chip confirm whether the other party uses the intermediate Flash or not through IPMI interaction mode.
The main board body is also provided with a CPLD chip and a PCH chip which are connected with the BMC chip; the BMC chip is also connected with a second selection switch through the expansion board, and the second selection switch is connected with the PCH chip;
the second selection switch is also connected with a first BIOS Flash and a second BIOS Flash. And directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
The utility model provides a server for realizing data exchange between a BIOS chip and a BMC chip, which comprises a main board body, wherein a host and the BMC chip are arranged on the main board body, and the host is respectively connected with the BIOS chip and an intermediate Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
The BMC chip is connected with the intermediate Flash through an SPI signal line.
The intermediate Flash comprises a BIOS data storage area and a BMC data storage area.
The BIOS chip and the BMC chip are connected through IPMI communication.
An intermediary Flash is added on the main board, and the host is connected with the BIOS chip and the intermediary Flash through a first selection switch; the BMC chip is also connected with the intermediate Flash through SPI, and respectively stores data which need to be synchronized into the intermediate Flash through a data format protocol regulated between the BIOS chip and the BMC chip, when the data need to be read, the BIOS chip and the BMC chip respectively read the needed content from different areas of the intermediate Flash, and the BIOS chip and the BMC chip confirm whether the other party uses the intermediate Flash or not through IPMI interaction mode. And directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
The utility model provides a server for realizing data exchange between a BIOS chip and a BMC chip, which comprises a main board body, wherein a host and the BMC chip are arranged on the main board body, and the host is respectively connected with the BIOS chip and an intermediate Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
The BMC chip is connected with the intermediate Flash through an SPI signal line.
The intermediate Flash comprises a BIOS data storage area and a BMC data storage area.
The BIOS chip and the BMC chip are connected through IPMI communication.
An intermediary Flash is added on the main board, and the host is connected with the BIOS chip and the intermediary Flash through a first selection switch; the BMC chip is also connected with the intermediate Flash through SPI, and respectively stores data which need to be synchronized into the intermediate Flash through a data format protocol regulated between the BIOS chip and the BMC chip, when the data need to be read, the BIOS chip and the BMC chip respectively read the needed content from different areas of the intermediate Flash, and the BIOS chip and the BMC chip confirm whether the other party uses the intermediate Flash or not through IPMI interaction mode.
The main board body is also provided with a CPLD chip and a PCH chip which are connected with the BMC chip; the BMC chip is also connected with a second selection switch through the expansion board, and the second selection switch is connected with the PCH chip;
the second selection switch is also connected with a first BIOS Flash and a second BIOS Flash. And directly taking the intermediate Flash as a dynamic region of the BIOS chip to store configuration, and recovering the configuration through the region at any time. For the non-instant communication content, the method can avoid the problem that the BIOS chip and the BMC chip are interactively coupled, namely the BIOS chip and the BMC chip are fetched immediately, and the problem caused by interaction is greatly reduced.
Although the present utility model has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present utility model is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present utility model by those skilled in the art without departing from the spirit and scope of the present utility model, and it is intended that all such modifications and substitutions be within the scope of the present utility model/be within the scope of the present utility model as defined by the appended claims. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the claims.
Claims (8)
1. The device is characterized by comprising a host and a BMC chip, wherein the host is respectively connected with the BIOS chip and an intermediate Flash through a first selection switch;
the intermediate Flash is connected with the BMC chip.
2. The device for exchanging data between a BIOS chip and a BMC chip of claim 1 wherein the BMC chip is connected to the intermediate Flash via SPI signal lines.
3. The BIOS chip and BMC chip data exchange device of claim 2, wherein the intermediary Flash comprises a BIOS data storage area and a BMC data storage area.
4. The device for exchanging data between a BIOS chip and a BMC chip of claim 3 wherein the BIOS chip and the BMC chip are communicatively coupled by IPMI.
5. The device of claim 4, wherein the first selector switch is an SPI selector chip.
6. A motherboard for implementing data exchange between a BIOS chip and a BMC chip, comprising a motherboard body, wherein the motherboard body is provided with the data exchange device for the BIOS chip and the BMC chip according to any one of claims 1 to 4.
7. The motherboard for implementing data exchange between the BIOS chip and the BMC chip according to claim 6, wherein the motherboard body is further provided with a CPLD chip and a PCH chip connected with the BMC chip; the BMC chip is also connected with a second selection switch through the expansion board, and the second selection switch is connected with the PCH chip;
the second selection switch is also connected with a first BIOS Flash and a second BIOS Flash.
8. A server for implementing data exchange between a BIOS chip and a BMC chip, comprising a motherboard according to any of claims 6-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321229147.9U CN219574798U (en) | 2023-05-19 | 2023-05-19 | BIOS chip and BMC chip data exchange device, mainboard and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321229147.9U CN219574798U (en) | 2023-05-19 | 2023-05-19 | BIOS chip and BMC chip data exchange device, mainboard and server |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219574798U true CN219574798U (en) | 2023-08-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321229147.9U Active CN219574798U (en) | 2023-05-19 | 2023-05-19 | BIOS chip and BMC chip data exchange device, mainboard and server |
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| Country | Link |
|---|---|
| CN (1) | CN219574798U (en) |
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2023
- 2023-05-19 CN CN202321229147.9U patent/CN219574798U/en active Active
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