CN109933418B - Timestamp synchronization method, electronic equipment and heterogeneous equipment - Google Patents
Timestamp synchronization method, electronic equipment and heterogeneous equipment Download PDFInfo
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- CN109933418B CN109933418B CN201910227902.1A CN201910227902A CN109933418B CN 109933418 B CN109933418 B CN 109933418B CN 201910227902 A CN201910227902 A CN 201910227902A CN 109933418 B CN109933418 B CN 109933418B
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Abstract
The application discloses a timestamp synchronization method, electronic equipment and heterogeneous equipment, wherein the method comprises the following steps: the method comprises the steps that a first processor responds to a synchronization instruction of a second processor and records a current first moment of the first processor, wherein data are transmitted between the first processor and the second processor through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than a threshold value; the first processor obtains a second moment sent by the second processor, wherein the second moment is a moment recorded when the second processor triggers the synchronous instruction; and after receiving the task data transmitted by the second processor, the first processor performs data processing on the task data based on the first time, the second time and the data time in the task data.
Description
Technical Field
The present application relates to the field of heterogeneous computing technologies, and in particular, to a timestamp synchronization method, an electronic device, and a heterogeneous device.
Background
In the heterogeneous device, the coprocessor sends data to the main processor for data processing.
However, since the coprocessor and the main processor are in different systems, there is a difference between the timestamps of the coprocessor and the main processor, which may cause inaccuracy or even failure of the main processor in data processing.
Disclosure of Invention
In view of this, the present application provides a timestamp synchronization method, an electronic device, and a heterogeneous device, so as to solve the technical problem in the prior art that a main coprocessor has inaccurate data processing.
The application provides a timestamp synchronization method, which comprises the following steps:
the method comprises the steps that a first processor responds to a synchronization instruction of a second processor and records a current first moment of the first processor, wherein data are transmitted between the first processor and the second processor through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than a threshold value;
the first processor obtains a second moment sent by the second processor, wherein the second moment is a moment recorded by the second processor when the synchronous instruction is triggered;
and after receiving the task data transmitted by the second processor, the first processor performs data processing on the task data based on the first time, the second time and the data time in the task data.
In the above method, preferably, the first processor performs data processing on the task data based on the first time and the second time and a data time in the task data, and the method includes:
the first processor determines the corresponding relation of the first processor and the second processor for the time stamp based on the first time and the second time;
and the first processor performs data processing on the task data based on the corresponding relation of the timestamps and the data time in the task data.
Preferably, in the method, the data processing of the task data by the first processor based on the correspondence between the timestamps and the data time in the task data includes:
the first processor converts the time corresponding to the timestamp of the second processor in the task data into the time corresponding to the timestamp of the first processor based on the corresponding relation of the timestamps;
and the first processor performs data processing on the task data subjected to the time stamp conversion.
In the above method, preferably, the correspondence relationship between the timestamps includes: a time offset between the first time and the second time.
In the method, preferably, the synchronous instruction is a processor input/output interrupt instruction.
The present application further provides an electronic device, including:
the memory is used for storing an application program and data generated by the operation of the application program;
the processor is used for responding to a synchronization instruction of a processor of other equipment and recording the current first moment of the processor of the electronic equipment, wherein data are transmitted between the processor of the electronic equipment and the processor of the other equipment through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than a threshold value;
the processor of the electronic device is further configured to obtain a second time sent by the processor of the other device, where the second time is a time recorded by the processor of the other device when the synchronization instruction is triggered; and after receiving the task data transmitted by the processor of the other device, processing the task data based on the first time, the second time and the data time in the task data.
The present application also provides another timestamp synchronization method, including:
the method comprises the steps that a second processor triggers a synchronization instruction to a first processor and records a current second moment, data are transmitted between the first processor and the second processor through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than a threshold value, wherein the first processor records the current first moment of the first processor in response to the synchronization instruction of the second processor;
and the second processor sends the second time to the first processor, so that the first processor performs data processing on the task data based on the first time, the second time and the data time in the task data after receiving the task data transmitted by the second processor.
In the above method, preferably, the second processor transmits task data, including:
after marking the current data time of the task data to be transmitted by the second processor, transmitting the task data to the first processor, so that the first processor determines the corresponding relation of the first processor and the second processor for the time stamp based on the first time and the second time, and performs data processing on the task data based on the corresponding relation of the time stamp and the data time in the task data.
The present application further provides another electronic device, comprising:
the memory is used for storing an application program and data generated by the operation of the application program;
the processor is used for triggering a synchronization instruction to the processors of other devices and recording a current second moment, data are transmitted between the processors of the other devices and the processor of the electronic device through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than a threshold value, wherein the processors of the other devices respond to the synchronization instruction of the processors of the electronic device and record a current first moment of the processors of the other devices;
wherein the processor of the electronic device is further configured to: and sending the second time to the processors of the other devices, so that the processors of the other devices perform data processing on the task data based on the first time, the second time and the data time in the task data after receiving the task data transmitted by the processors of the electronic devices.
The present application further provides a heterogeneous device, comprising a first processor and a second processor, wherein:
the second processor triggers a synchronization instruction to the first processor and records the current second moment;
the first processor responds to a synchronization instruction of the second processor and records a current first moment of the first processor, wherein data are transmitted between the first processor and the second processor through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than a threshold value;
the second processor sends the second time to the first processor;
the first processor obtains a second moment sent by the second processor;
and after receiving the task data transmitted by the second processor, the first processor performs data processing on the task data based on the first time, the second time and the data time in the task data.
According to the technical scheme, the timestamp synchronization method, the electronic equipment and the heterogeneous equipment disclosed by the application can be used for simultaneously recording respective moments by quickly transmitting the synchronization instruction with negligible transmission delay between the main coprocessors, so that the task data are processed based on the corresponding relation between the two moments recorded by the two processors at the same time and the data moments of the task data. Therefore, the time stamp synchronization can be carried out on the main coprocessor in the heterogeneous equipment, and accurate data processing is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a timestamp synchronization method according to an embodiment of the present application;
FIG. 2 is a diagram illustrating an example of an application of an embodiment of the present application;
FIG. 3 is a partial flow chart of a first embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to a second embodiment of the present application;
fig. 5 is a flowchart of a timestamp synchronization method according to a third embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present application;
fig. 7 is a schematic structural diagram of a heterogeneous device according to a fifth embodiment of the present application;
fig. 8 is a diagram illustrating another exemplary application of the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Referring to fig. 1, a flowchart of an implementation of a timestamp synchronization method according to a first embodiment of the present application is shown, where the timestamp synchronization method is applied to a first processor, i.e., a main processor, in a heterogeneous device. There is also a second processor, a co-processor, in the heterogeneous device. The method in this embodiment is mainly used for synchronizing the time stamps of the second processor in the first processor.
In this embodiment, the method may include the steps of:
step 101: and responding to a synchronization instruction of the second processor, and recording the current first time of the first processor.
The first processor and the second processor transmit data through a hardware transmission line, such as a hardware circuit, and the transmission rate of the hardware transmission line is higher than a threshold value, that is, the delay of the synchronization instruction transmitted from the second processor to the first processor is very small and negligible.
It should be noted that the second processor triggers the synchronization instruction, transmits the synchronization instruction to the first processor, the first processor responds to the synchronization instruction, and so on, and the delay caused by these is very small based on the hardware transmission line in the present embodiment, and therefore, in the present embodiment, the current first time recorded by the first processor may be considered to be the same time as the time when the second processor triggers the synchronization instruction.
Step 102: a second time instant sent by the second processor is obtained.
The second time is a time recorded by the second processor when the synchronization instruction is triggered, that is, the second processor records the second time while triggering the synchronization instruction, and the first processor records the first time in response to the synchronization instruction triggered by the second processor, where the first time and the second time may be considered as times recorded by the first processor and the second processor respectively at the same time.
It should be noted that, in this embodiment, there may be one or more second processors, and therefore, there may be one or more second times obtained in the first processor, and correspondingly, there may also be one or more first times recorded by the first processor, where there is a second time corresponding to the first time recorded in the first processor, as shown in fig. 2, that is, for each second processor that sends a synchronization instruction, the first processor records a first time, and the second time corresponding to the second time sent by the second processor corresponds to the first time.
Step 103: and receiving the task data transmitted by the second processor.
The task data transmitted by the second processor may be the task data that the second processor needs to perform data processing and send to the first processor after the first processor obtains the second time to send to the second processor.
Step 104: and processing the task data based on the first time and the second time and the data time in the task data.
That is to say, in this embodiment, the timestamps between the first processor and the second processor are synchronized based on the first time and the second time, so that the data times in the task data can be unified to one timestamp to perform corresponding data processing, and thus, a processing error caused by asynchronous timestamps does not occur.
According to the above solution, in the timestamp synchronization method provided in the first embodiment of the present application, the respective times are recorded simultaneously by quickly transmitting the synchronization instruction with negligible transmission delay between the main coprocessors, so that the task data is processed based on the correspondence between the two times recorded by the two processors at the same time and the data time of the task data. Therefore, in the embodiment, the timestamp synchronization can be performed on the main coprocessor in the heterogeneous device, so that accurate data processing is realized.
In one implementation manner, when the first processor performs data processing on the task data based on the first time and the second time and the data time in the task data, the following may be specifically implemented, as shown in fig. 3:
step 301: and determining the corresponding relation between the first processor and the first processor for the time stamp based on the first time and the second time.
For example, under a synchronization instruction, the first processor records a first time, the second processor records a second time, the first time and the second time are times under timestamps followed by different processors under the same world clock, and the first processor determines a corresponding relationship between the first processor and the second processor for respective timestamps for a scale relationship between a front-back phase difference between the first time and the second time, e.g., if the first time is later than the second time by a first time, the first processor may determine a corresponding relationship that the timestamp of the first processor is later than the timestamp of the second processor by the first time.
Step 302: and processing the task data based on the corresponding relation of the timestamps and the data time in the task data.
In this embodiment, the first processor processes the task data based on the corresponding relationship of the timestamps and the data time in the task data, and in the processing process, when the timestamps corresponding to the data time in the task data are not uniform, the data time in the task data is uniform based on the corresponding relationship of the timestamps of the first processor and the second processor, so that error-free data processing is realized.
For example, when the first processor performs data processing on the task data based on the corresponding relationship of the timestamps and the data time in the task data, the following specific implementation may be implemented:
first, the first processor converts the time corresponding to the timestamp of the second processor in the task data into the time corresponding to the timestamp of the first processor based on the corresponding relation of the timestamps, and then the first processor performs data processing on the task data subjected to the timestamp conversion.
That is, the task data is sent by the second processor to the first processor, the data time instant in the task data is based on the timestamp of the second processor, and there is a time offset between the timestamp of the second processor and the timestamp of the first processor, and the time offset corresponds to the time difference between the first time instant and the second time instant, i.e.: the timestamp correspondence between the first processor and the second processor is represented as: a time offset between the first time and the second time. Thus, in this embodiment, after receiving the task data sent by the second processor, the first processor determines the correspondence between the timestamps, such as the time offset between the timestamps, between the first processor and the second processor based on the time offset between the first time and the second time, and then, based on the correspondence between the timestamps, the first processor performs time conversion on the data time corresponding to the timestamp of the second processor in the task data to convert the data time into the data time corresponding to the timestamp of the first processor.
In an implementation manner, the synchronization instruction responded by the first processor may be an input/output interrupt instruction of the second processor, for example, when the coprocessor needs to perform timestamp synchronization or the main processor needs to perform timestamp synchronization, the coprocessor operates an input/output IO (input/output) to generate an interrupt, so as to generate a processor input/output interrupt instruction, and sends the interrupt instruction to the main processor while recording the current time of the coprocessor, and the main processor responds to the interrupt instruction and records the current time, so as to perform a subsequent timestamp synchronization process.
Referring to fig. 4, a schematic structural diagram of an electronic device according to a second embodiment of the present disclosure is provided, where the electronic device may be a main processing device in a heterogeneous device, and the main processing device may have the following structure to implement timestamp synchronization in the heterogeneous device:
the memory 401 is used for storing the application programs and the data generated by the operation of the application programs.
A processor 402, configured to record a current first time of a processor of the electronic device in response to a synchronization instruction of the processor of the other device, where data is transmitted between the processor 402 of the electronic device and the processor of the other device through a hardware transmission line 403, and a transmission rate of the hardware transmission line 403 is higher than a threshold;
the processor 402 of the electronic device is further configured to obtain a second time sent by the processor of the other device, where the second time is a time recorded by the processor of the other device when the synchronization instruction is triggered; and after receiving the task data transmitted by the processors of the other devices, performing data processing on the task data based on the first time, the second time and the data time in the task data.
It should be noted that, the processor 402 is a main processor in the foregoing heterogeneous device, and processors of other devices are coprocessors in the foregoing heterogeneous device, and in a specific application, reference may be made to the foregoing description for implementation of the processor 402, and no further description is provided herein.
It can be known from the foregoing solutions that, in the electronic device provided in the second embodiment of the present application, the respective times are recorded simultaneously by quickly transmitting the synchronization instruction with negligible transmission delay between the main coprocessors, so that the task data is processed based on the correspondence between the two times recorded by the two processors at the same time and the data time of the task data. Therefore, in the embodiment, the timestamp synchronization can be performed on the main coprocessor in the heterogeneous device, so that accurate data processing is realized.
Referring to fig. 5, a flowchart of a timestamp synchronization method provided in a third embodiment of the present application is applicable to a second processor, i.e., a coprocessor, in a heterogeneous device. There is also a first processor, a host processor, in the heterogeneous device. The method in this embodiment is mainly used for synchronizing the timestamp of the second processor with the timestamp of the first processor in the second processor.
In this embodiment, the method may include the steps of:
step 501: the second processor triggers a synchronization instruction to the first processor and records the current second time.
The data is transmitted between the first processor and the second processor through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than the threshold value, that is, the delay of the synchronization instruction transmitted to the first processor by the second processor is very small and can be ignored.
It should be noted that, after the second processor triggers the synchronization instruction to the first processor, the first processor records the current first time of the first processor in response to the synchronization instruction of the second processor.
Step 502: and the second processor sends the second time to the first processor, so that the first processor performs data processing on the task data based on the first time, the second time and the data time in the task data after receiving the task data transmitted by the second processor.
The second time is a time recorded by the second processor when the synchronization instruction is triggered, that is, the second processor records the second time while triggering the synchronization instruction to the first processor, and the first processor records the first time in response to the synchronization instruction triggered by the second processor, where the first time and the second time may be considered as times recorded by the first processor and the second processor, respectively, at the same time.
Correspondingly, after the first processor receives the second time, the corresponding relation between the first processor and the second processor for the time stamp can be determined based on the first time and the second time, and then the first processor can process the task data based on the corresponding relation of the time stamp after receiving the task data sent by the second processor, so that data processing errors caused by non-uniform time stamps are avoided.
According to the timestamp synchronization method provided by the third embodiment of the present application, the respective times are recorded simultaneously by quickly transmitting the synchronization instruction with negligible transmission delay between the main coprocessors, so that the task data is processed based on the correspondence between the two times recorded by the two processors at the same time and the data time of the task data. Therefore, in the embodiment, the timestamp synchronization can be performed on the main coprocessor in the heterogeneous device, so that accurate data processing is realized.
In an implementation manner, the task data transmitted by the second processor may specifically be:
after marking the current data time of the task data to be transmitted by the second processor, transmitting the task data to the first processor, so that the first processor determines the corresponding relation of the first processor and the second processor for the time stamp based on the first time and the second time, and performs data processing on the task data based on the corresponding relation of the time stamp and the data time in the task data.
That is to say, the second processor marks its own time for the task data to be transmitted, where the time is the time corresponding to the timestamp of the second processor, so that after the first processor receives the task data transmitted by the second processor, and determines the timestamp correspondence based on the first time and the second time, the first processor can perform time conversion on the data time in the task data based on the timestamp correspondence, convert the time corresponding to the timestamp of the second processor into the time corresponding to the timestamp of the first processor, and perform data processing on the task data after the time conversion, thereby avoiding data processing errors.
Referring to fig. 6, a schematic structural diagram of an electronic device according to a fourth embodiment of the present disclosure is provided, where the electronic device may be a co-processing device in a heterogeneous structure, and the co-processing device may have the following structure to implement timestamp synchronization in the heterogeneous device:
a memory 601 for storing application programs and data generated by the application programs;
the processor 602 is configured to trigger a synchronization instruction to a processor of another device and record a current second time, where data is transmitted between the processor of the other device and the processor 602 of the electronic device through a hardware transmission line 603, and a transmission rate of the hardware transmission line 603 is higher than a threshold, where the processor of the other device records a current first time of the processor of the other device in response to the synchronization instruction of the processor 602 of the electronic device;
wherein the processor 602 of the electronic device is further configured to: and sending the second time to the processor of the other device, so that after receiving the task data transmitted by the processor 602 of the electronic device, the processor of the other device performs data processing on the task data based on the first time, the second time and the data time in the task data.
It should be noted that the processor 602 is a coprocessor in the foregoing heterogeneous device, and processors of other devices are main processors in the foregoing heterogeneous device, and in a specific application, reference may be made to the foregoing description for specific implementation of the processor 602, and details are not described herein.
Referring to fig. 7, a schematic structural diagram of a heterogeneous device according to a fifth embodiment of the present application is shown, where the heterogeneous device includes a first processor 701 and a second processor 702, the first processor 701 may be a main processor, and the second processor 702 may be a coprocessor, where:
the second processor 702 triggers a synchronization instruction to the first processor 701 and records a current second moment;
the first processor 701, in response to a synchronization instruction of the second processor 702, records a current first time of the first processor 701, wherein data is transmitted between the first processor 701 and the second processor 702 through a hardware transmission line, and a transmission rate of the hardware transmission line is higher than a threshold value;
the second processor 702 sends the second time to the first processor 701;
the first processor 701 obtains a second time sent by the second processor 702;
after receiving the task data transmitted by the second processor 702, the first processor 701 performs data processing on the task data based on the first time and the second time and the data time in the task data.
It should be noted that, for specific implementation manners of the first processor 701 and the second processor 702, reference may be made to the corresponding contents in the foregoing, and details are not described here again.
According to the above scheme, in the heterogeneous device provided in the fifth embodiment of the present application, the synchronization instruction with negligible transmission delay is quickly transmitted between the main coprocessors, and respective time is recorded at the same time, so that the task data is processed based on the correspondence between the two time recorded by the two processors at the same time and the data time of the task data. Therefore, in the embodiment, the timestamp synchronization can be performed on the main coprocessor in the heterogeneous device, so that accurate data processing is realized.
The following takes an Augmented Reality AR (Augmented Reality) heterogeneous device with a movidia coprocessor and a Qualcomm main processor as an example to illustrate the technical solution in the above embodiment:
in connection with the process flow diagram shown in fig. 8, starting with heterogeneous device startup, the following is:
firstly, a Qualcomm main processor is electrified and started, an operating system is loaded, and firmware data of a Movidius coprocessor is read from a memory;
secondly, the Qualcomm main processor guides the Movidius coprocessor to be powered on and started, firmware data of the Movidius coprocessor is transmitted through an inter-chip data bus, and the Movidius coprocessor is started and loads the firmware data;
after the Movidius coprocessor is started, operating an inter-chip interrupt IO (input/output) to guide Qualcomm to generate interrupt, recording a current Movidius coprocessor timestamp, and transmitting the timestamp to a Qualcomm main processor through a Serial Peripheral Interface (SPI);
after the Qualcomm main processor is interrupted, recording the timestamp of the current operating system, and obtaining the difference of the timestamps between the two processors after receiving the timestamp of the Movidius main processor transmitted by the SPI;
and finally, each time the data packet transmitted to the Qualcomm main processor by the Movidius coprocessor is provided with a time stamp, and the Qualcomm main processor converts the time stamp of the data packet of the Movidius coprocessor into the time stamp of the Qualcomm main processor operating system according to the relation of the time stamps to finish time synchronization.
It should be noted that there is a hardware circuit level triggering mechanism between the Movidius coprocessor and the Qualcomm main processor. The triggering mechanism of the hardware circuit level meets certain conditions as follows:
the trigger signal of the movidia coprocessor has to be short in time from sending to validation, and needs to be lower than 500ns;
the response time of the Qualcomm main processor receiving the trigger signal must be short and must be less than 500ns;
the time from the sending of the trigger signal by the Movidius coprocessor to the validation of the trigger signal is short and is less than 500ns;
the generation of the trigger signal of the Movidius coprocessor uses hardware level interrupt;
the response of the Qualcomm main processor to the trigger signal should use a hardware level interrupt;
therefore, the Qualcomm main processor transmits the image sent by the Movidius coprocessor after the timestamp synchronization, the Inertial Measurement Unit (IMU) data and other task data to the processor ARM so as to complete the back-end algorithm processing.
Therefore, the problem of synchronization of the data timestamps of the master processor and the slave processor in heterogeneous computing can be solved, and the method is good in instantaneity, low in power consumption and advantageous in computing performance and system endurance.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A time stamp synchronization method is applied to heterogeneous devices, and comprises the following steps:
the method comprises the steps that a first processor responds to a synchronization instruction of a second processor and records a current first moment of the first processor, wherein data are transmitted between the first processor and the second processor through a hardware transmission line, the transmission rate of the hardware transmission line is higher than a threshold value so that the delay of the transmission of the synchronization instruction of the second processor to the first processor can be ignored, the first processor is a main processor of the heterogeneous device, and the second processor is a sub-processor of the heterogeneous device;
the first processor obtains a second moment sent by the second processor, wherein the second moment is a moment recorded by the second processor when the synchronous instruction is triggered;
after receiving the task data transmitted by the second processor, the first processor performs data processing on the task data based on the first time, the second time and the data time in the task data;
the first processor performs data processing on the task data based on the first time and the second time and the data time in the task data, and the data processing includes: the first processor determines the corresponding relation of the first processor and the second processor for the time stamp based on the first time and the second time; the first processor performs data processing on the task data based on the corresponding relation of the timestamps and the data time in the task data; wherein determining a correspondence of the first processor to the second processor for a timestamp comprises: the first processor determines the corresponding relation of the first processor and the second processor aiming at respective timestamps for the scale relation of the front-back phase difference between the first time and the second time;
the first processor performs data processing on the task data based on the corresponding relation of the timestamps and the data time in the task data, and the data processing includes: the first processor converts the time corresponding to the second processor timestamp in the task data into the time corresponding to the first processor timestamp based on the corresponding relation of the timestamps; and the first processor performs data processing on the task data subjected to the time stamp conversion.
2. The method of claim 1, the correspondence of timestamps comprising: a time offset between the first time and the second time.
3. The method of claim 2, the synchronization instruction being a processor input output interrupt instruction.
4. An electronic device that is a primary processing device of heterogeneous devices, the electronic device comprising:
the memory is used for storing an application program and data generated by the running of the application program;
the processor is used for responding to a synchronization instruction of a processor of other equipment and recording the current first moment of the processor of the electronic equipment, wherein data are transmitted between the processor of the electronic equipment and the processor of the other equipment through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than a threshold value so that the delay of the synchronization instruction of a second processor to be transmitted to a first processor can be ignored;
the processor of the electronic device is further configured to obtain a second time sent by the processor of the other device, where the second time is a time recorded when the processor of the other device triggers the synchronization instruction; after receiving task data transmitted by the processors of the other devices, performing data processing on the task data based on the first time, the second time and data time in the task data;
the data processing method includes that a processor of the electronic device performs data processing on the task data based on the first time and the second time and data time in the task data, and includes: the processor of the electronic device determines the corresponding relation of the processor of the electronic device and the processors of the other devices for the time stamps based on the first time and the second time; the processor of the electronic equipment performs data processing on the task data based on the corresponding relation of the timestamps and the data time in the task data; wherein determining a correspondence of the processor of the electronic device to the processors of the other devices for the time stamps comprises: the processor of the electronic equipment determines the corresponding relation of the processor of the electronic equipment and the processors of other equipment aiming at respective timestamps for the scale relation of the front-back phase difference between the first moment and the second moment;
the processor of the electronic device performs data processing on the task data based on the corresponding relation of the timestamps and the data time in the task data, and the data processing method includes: the processor of the electronic equipment converts the time corresponding to the processor time stamps of the other equipment in the task data into the time corresponding to the processor time stamps of the electronic equipment based on the corresponding relation of the time stamps; and the processor of the electronic equipment performs data processing on the task data subjected to the timestamp conversion.
5. A time stamp synchronization method is applied to heterogeneous devices, and comprises the following steps:
the method comprises the steps that a second processor triggers a synchronization instruction to a first processor and records a current second moment, data are transmitted between the first processor and the second processor through a hardware transmission line, the transmission rate of the hardware transmission line is higher than a threshold value, so that the delay of the synchronization instruction of the second processor transmitted to the first processor can be ignored, wherein the first processor responds to the synchronization instruction of the second processor and records the current first moment of the first processor, the first processor is a main processor of the heterogeneous device, and the second processor is a slave processor of the heterogeneous device;
the second processor sends the second time to the first processor, so that the first processor performs data processing on the task data based on the first time, the second time and the data time in the task data after receiving the task data transmitted by the second processor;
the second processor transmitting task data, comprising:
after marking the current data time of the task data to be transmitted by the second processor, transmitting the task data to the first processor, so that the first processor determines the corresponding relation of the first processor and the second processor for the timestamp based on the first time and the second time, and performs data processing on the task data based on the corresponding relation of the timestamp and the data time in the task data; wherein determining a correspondence of the first processor to the second processor for a timestamp comprises: and the first processor determines the corresponding relation of the first processor and the second processor aiming at the respective timestamps for the scale relation of the front-back phase difference between the first time and the second time.
6. An electronic device that is a co-processing device in a heterogeneous structure, the electronic device comprising:
the memory is used for storing an application program and data generated by the running of the application program;
the processor is used for triggering a synchronization instruction to the processor of other equipment and recording the current second moment, data is transmitted between the processor of other equipment and the processor of the electronic equipment through a hardware transmission line, the transmission rate of the hardware transmission line is higher than a threshold value so that the delay of the synchronization instruction of the second processor to be transmitted to the first processor can be ignored, and the processor of other equipment is used for responding to the synchronization instruction of the processor of the electronic equipment and recording the current first moment of the processor of other equipment;
wherein the processor of the electronic device is further configured to: sending the second time to the processors of the other devices, so that the processors of the other devices perform data processing on the task data based on the first time, the second time and the data time in the task data after receiving the task data transmitted by the processors of the electronic devices;
the processor of the electronic device transmits task data, comprising:
after marking the current data time for the task data to be transmitted by the processor of the electronic device, transmitting the task data to the processors of the other devices, so that the processors of the other devices determine the corresponding relation between the processors of the other devices and the processors of the electronic device for the time stamps based on the first time and the second time, and perform data processing on the task data based on the corresponding relation of the time stamps and the data time in the task data; wherein determining a correspondence of the processor of the electronic device to the processors of the other devices for the time stamps comprises: and the processor of the electronic equipment determines the corresponding relation of the processor of the electronic equipment and the processors of other equipment aiming at respective timestamps according to the scale relation of the front-back phase difference between the first moment and the second moment.
7. A heterogeneous device comprising a first processor and a second processor, the first processor being a master processor of the heterogeneous device and the second processor being a slave processor of the heterogeneous device, wherein:
the second processor triggers a synchronization instruction to the first processor and records the current second moment;
the first processor records a current first moment of the first processor in response to a synchronization instruction of the second processor, wherein data are transmitted between the first processor and the second processor through a hardware transmission line, and the transmission rate of the hardware transmission line is higher than a threshold value so that the delay of the synchronization instruction of the second processor to the first processor can be ignored;
the second processor sends the second time to the first processor;
the first processor obtains a second moment sent by the second processor;
after receiving the task data transmitted by the second processor, the first processor performs data processing on the task data based on the first time, the second time and the data time in the task data;
the first processor performs data processing on the task data based on the first time and the second time and the data time in the task data, and the data processing includes: the first processor determines the corresponding relation of the first processor and the second processor for the time stamp based on the first time and the second time; the first processor performs data processing on the task data based on the corresponding relation of the timestamps and the data time in the task data; wherein determining a correspondence of the first processor to the second processor for a timestamp comprises: the first processor determines the corresponding relation of the first processor and the second processor aiming at respective timestamps for the scale relation of the front-back phase difference between the first time and the second time;
the first processor performs data processing on the task data based on the corresponding relation of the timestamps and the data time in the task data, and the data processing includes: the first processor converts the time corresponding to the timestamp of the second processor in the task data into the time corresponding to the timestamp of the first processor based on the corresponding relation of the timestamps; and the first processor performs data processing on the task data subjected to the time stamp conversion.
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| CN101515831B (en) * | 2008-02-22 | 2013-08-28 | 杭州华三通信技术有限公司 | Method, system and device for time synchronous transfer |
| US20110035511A1 (en) * | 2009-08-07 | 2011-02-10 | Cisco Technology, Inc. | Remote Hardware Timestamp-Based Clock Synchronization |
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