CN117639536A - Inverter pulse width modulation control method and device, electronic equipment and storage medium - Google Patents
Inverter pulse width modulation control method and device, electronic equipment and storage medium Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
- H02P27/085—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation wherein the PWM mode is adapted on the running conditions of the motor, e.g. the switching frequency
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Abstract
The invention discloses an inverter pulse width modulation control method, an inverter pulse width modulation control device, electronic equipment and a storage medium. The method comprises the following steps: the output channel counter of each phase of the inverter is controlled to periodically output a count value, and the output channel counters among different phases are mutually independent; detecting the count value of an output channel counter of each phase of the inverter; and controlling the pulse width modulation signal of the output channel of the corresponding phase of the output channel counter according to the count value of the output channel counter of each phase. The invention controls the pulse width modulation signals output by each bridge of each phase through the independent output channel counter, thereby greatly improving the flexibility of the inverter pulse width modulation output driving scheme and being suitable for wider application occasions.
Description
Technical Field
The invention relates to the technical field related to electrical equipment, in particular to an inverter pulse width modulation control method, an inverter pulse width modulation control device, electronic equipment and a storage medium.
Background
In an electro-drive system, the inverter typically operates in an in-phase pulse width modulation (Pulse Width Modulation, PWM) output mode. Taking a three-phase inverter as an example, when the three-phase inverter works in an in-phase pulse width modulation output mode, the starting moments of the six three-phase bridge arm driving signal periods completely coincide.
As shown in fig. 1, taking a three-phase inverter as an example, the three phases include a U-phase, a W-phase, and a V-phase, and each phase includes an upper bridge arm (abbreviated as an upper bridge) and a lower bridge arm (abbreviated as a lower bridge). When the three-phase pulse width modulation output system works in the in-phase pulse width modulation output mode, the three-phase six bridge arms have synchronous output channel count values, and the starting moments of the three-phase six bridge arm driving signal periods are completely overlapped. The phase position between the pulse width modulation outputs of each phase is not adjustable, and the pulse width modulation outputs cannot be suitable for wider application occasions.
Therefore, the phase of the pulse width modulation output of the same phase of the existing inverter is not adjustable, the flexibility is poor, and the inverter cannot be suitable for wider application occasions.
Disclosure of Invention
Based on this, it is necessary to provide an inverter pulse width modulation control method, an inverter pulse width modulation control device, an electronic device and a storage medium, which solve the technical problems that the in-phase pulse width modulation output of the inverter in the prior art is poor in flexibility and cannot be applied to wider application occasions.
The invention provides an inverter pulse width modulation control method, which comprises the following steps:
the method comprises the steps of controlling an output channel counter of each phase of an inverter to periodically output a count value, wherein the output channel counters of different phases are mutually independent;
Detecting the count value of an output channel counter of each phase of the inverter;
and controlling the pulse width modulation signal of the output channel of the corresponding phase of the output channel counter according to the count value of the output channel counter of each phase.
Further, the start time of the period of the output channel counter of each phase is adjustable.
Further, each phase of the inverter includes a first bridge arm and a second bridge arm, and the output channel counter for controlling each phase of the inverter periodically outputs a count value, specifically including:
selecting an output channel counter of a first bridge arm or an output channel counter of a second bridge arm as a main output channel counter of the phase, and selecting an output channel counter of the other bridge arm of the phase as a slave output channel counter of the phase;
the method comprises the steps of controlling a main output channel counter of each phase of an inverter to periodically output a count value, and controlling a slave output channel counter of each phase to follow the output count value of the main output channel counter.
Further, each phase of the inverter includes a first leg and a second leg;
the output channel counter for controlling each phase of the inverter periodically outputs a count value, and specifically includes:
for each phase:
controlling the count value of the output channel counter of each phase to be increased, and controlling the count value of the output channel counter of the phase to be zeroed if the count value of the output channel counter of the phase is equal to the preset pulse width modulation period count value;
According to the count value of the output channel counter of each phase, the pulse width modulation signal output by the first bridge arm and the pulse width modulation signal output by the second bridge arm of the phase corresponding to the output channel counter are controlled, and the method specifically comprises the following steps:
for each phase:
if the count value of the output channel counter of the phase is equal to a preset first turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase and the level turnover of the pulse width modulation signal output by the second bridge arm of the phase;
and if the count value of the output channel counter of the phase is equal to the preset pulse width modulation period count value, controlling the pulse width modulation signal level output by the first bridge arm of the phase to overturn, and controlling the pulse width modulation signal level output by the second bridge arm of the phase to overturn, wherein the first overturn value is smaller than the pulse width modulation period count value.
Still further, the method further comprises:
in each pulse width modulation signal period of each phase, current sampling is carried out on a first delay time point preset after the midpoint of a high level or a low level of a pulse width modulation signal output by a first bridge arm of the phase to obtain sampling current of each phase, and the average value of the sampling current of all the phases is calculated; or alternatively
And for each phase, in each pulse width modulation signal period of the phase, carrying out current sampling on a first delay time point preset after the midpoint of the high level or the low level of the pulse width modulation signal output by the second bridge arm of the phase to obtain the sampling current of each phase, and calculating the average value of the sampling currents of all the phases.
Further, each phase of the inverter includes a first leg and a second leg;
the output channel counter for controlling each phase of the inverter periodically outputs a count value, and specifically includes:
for each phase, if the count value of the output channel counter of the phase is equal to zero, the count value of the output channel counter of the phase is controlled to be increased, and if the count value of the output channel counter of the phase is equal to the preset half pulse width modulation period count value, the count value of the output channel counter of the phase is controlled to be decreased;
according to the count value of the output channel counter of each phase, the pulse width modulation signal output by the first bridge arm and the pulse width modulation signal output by the second bridge arm of the phase corresponding to the output channel counter are controlled, and the method specifically comprises the following steps:
for each phase:
and if the count value of the output channel counter of the phase is equal to a preset second turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase, and controlling the level turnover of the pulse width modulation signal output by the second bridge arm of the phase, wherein the second turnover value is smaller than the half pulse width modulation period count value.
Still further, the method further comprises:
carrying out current sampling on each phase at a preset second delay time point of each pulse width modulation signal period of the phase to obtain sampling current of each phase, and calculating average value of the sampling currents of all phases; or alternatively
And carrying out current sampling on each phase at a preset second delay time point of the midpoint of each pulse width modulation signal period of the phase to obtain the sampling current of each phase, and calculating the average value of the sampling currents of all the phases.
Still further, the start time of the period of the output channel counter of each phase is adjustable.
The invention provides an inverter pulse width modulation control device, comprising:
the count value detection module is used for controlling the output channel counter of each phase of the inverter to periodically output a count value, and the output channel counters among different phases are mutually independent;
the output control module is used for detecting the count value of the output channel counter of each phase of the inverter and controlling the pulse width modulation signal of the output channel of the corresponding phase of the output channel counter according to the count value of the output channel counter of each phase.
The present invention provides an electronic device including:
At least one processor; the method comprises the steps of,
a memory communicatively coupled to at least one of the processors; wherein,
the memory stores instructions executable by at least one of the processors to enable the at least one processor to perform the inverter pulse width modulation control method as previously described.
The present invention provides a storage medium storing computer instructions that, when executed by a computer, are operable to perform all the steps of an inverter pulse width modulation control method as previously described.
The pulse width modulation signals of the output channels of each phase of the inverter are controlled by the count value of the output channel counter, the output channel counter of each phase of the inverter periodically outputs the count value, and the output channel counters among different phases are mutually independent, so that the pulse width modulation signals output by each bridge of each phase can be independently controlled through the independent output channel counter, thereby greatly improving the flexibility of the pulse width modulation output driving scheme of the inverter and being suitable for wider application occasions.
Drawings
FIG. 1 is a timing diagram of a conventional inverter PWM control method;
FIG. 2 is a flowchart illustrating an inverter PWM control method according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating an inverter PWM control method according to another embodiment of the present invention;
FIG. 4 is a timing diagram of an inverter PWM control method according to an embodiment of the invention;
FIG. 5 is a flowchart illustrating an inverter PWM control method according to yet another embodiment of the present invention;
FIG. 6 is a timing diagram of an inverter PWM control method according to another embodiment of the present invention;
FIG. 7 is a timing diagram of a U-phase output channel of an inverter PWM control method according to another embodiment of the present invention;
FIG. 8 is a schematic diagram of an inverter PWM control device according to the present invention;
fig. 9 is a schematic diagram of a hardware structure of an electronic device according to the present invention.
Detailed Description
Specific embodiments of the present invention will be further described below with reference to the accompanying drawings. Wherein like parts are designated by like reference numerals. It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings, and the words "inner" and "outer" refer to directions toward or away from, respectively, the geometric center of a particular component.
In an electro-drive system, the inverter typically operates in an in-phase pulse width modulated (Pulse Width Modulation, PWM) output and in-phase current sampling mode. As shown in fig. 1, taking a three-phase inverter as an example, the three phases include a U-phase, a W-phase, and a V-phase, and each phase includes an upper bridge arm (abbreviated as an upper bridge) and a lower bridge arm (abbreviated as a lower bridge). When the three-phase pulse width modulation circuit works in an in-phase pulse width modulation output and in-phase current sampling mode, the three-phase six bridge arms have synchronous output channel count values, and the starting moments of the three-phase six bridge arm driving signal periods completely coincide. Correspondingly, as the driving outputs of the bridge arms are in phase, the three-phase actual currents are also in phase, and the three-phase current sampling is triggered at the same moment, so that the average current can be obtained through sampling.
The in-phase pulse width modulation output and in-phase current sampling mode of the inverter have the advantages of simple realization and less occupation of resources of a micro control unit (Micro Controller Unit, MCU).
However, the phase position between pulse width modulation outputs of each phase of the existing inverter is not adjustable, the current sampling triggering time is fixed, the flexibility is poor, and the existing inverter cannot be suitable for wider application occasions, such as a boosting charging scheme taking a motor as a boosting circuit, a multiphase motor control scheme, a specific subharmonic voltage/current elimination scheme and the like.
In order to solve the technical problems, the invention provides an inverter pulse width modulation control method.
Fig. 2 is a flowchart of an inverter pwm control method according to an embodiment of the present invention, including:
step S201, the output channel counter of each phase of the inverter is controlled to periodically output a count value, and the output channel counters of different phases are mutually independent;
step S202, detecting the count value of an output channel counter of each phase of the inverter;
step S203, according to the count value of the output channel counter of each phase, the pulse width modulation signal of the output channel of the corresponding phase of the output channel counter is controlled.
In particular, the invention may be applied on microcontrollers (Micro Controller Unit, MCU). Step S201 is performed to control the output channel counter of each phase of the inverter to periodically output the count value. The output channel counters of different phases are independent of each other. Wherein the output channel counter may be set solely by the microcontroller and the counter periodically outputs the count value at a fixed frequency.
While the output channel counter periodically outputs the count value, step S202 is executed to detect the count value of the output channel counter of each phase of the inverter, and step S203 is executed to control the pulse width modulation signal of the output channel of the phase corresponding to the output channel counter according to the count value of the output channel counter of each phase.
In one embodiment, the inverter is a three-phase bridge inverter.
For inverter phase-shifting pulse width modulation output, a three-phase inverter is taken as an example, and the three-phase inverter comprises a U phase, a W phase and a V phase. The output channel counters of each phase are mutually independent, and by independently changing the count value output by the output channel counter of each phase, the pulse width modulation signal output by each bridge of each phase can be changed, thereby realizing the free adjustment of the phase shifting time (phase).
The pulse width modulation signals of the output channels of each phase of the inverter are controlled by the count value of the output channel counter, the output channel counter of each phase of the inverter periodically outputs the count value, and the output channel counters among different phases are mutually independent, so that the pulse width modulation signals output by each bridge of each phase can be independently controlled through the independent output channel counter, thereby greatly improving the flexibility of the pulse width modulation output driving scheme of the inverter and being suitable for wider application occasions. In this embodiment, with a relatively simple implementation, the moderate microcontroller resource consumption greatly improves the flexibility of the complex driving scheme of pwm output and current sampling, so that the method is suitable for a wider application, such as a boost charging scheme using a motor as a boost circuit, a multiphase motor control scheme, a specific subharmonic voltage/current cancellation scheme, and the like.
Fig. 3 is a flowchart of an inverter pwm control method according to another embodiment of the present invention, where each phase of the inverter includes a first leg and a second leg, and the method includes:
step S301, for each phase: and controlling the count value of the output channel counter of each phase to be increased, and controlling the count value of the output channel counter of the phase to be zeroed if the count value of the output channel counter of the phase is equal to the count value of the preset pulse width modulation period, wherein the output channel counters among different phases are mutually independent, and the starting time of the period of the output channel counter of each phase is adjustable.
In one embodiment, the output channel counter for controlling each phase of the inverter periodically outputs a count value, which specifically includes:
selecting an output channel counter of a first bridge arm or an output channel counter of a second bridge arm as a main output channel counter of the phase, and selecting an output channel counter of the other bridge arm of the phase as a slave output channel counter of the phase;
the method comprises the steps of controlling a main output channel counter of each phase of an inverter to periodically output a count value, and controlling a slave output channel counter of each phase to follow the output count value of the main output channel counter.
Step S302, detecting the count value of an output channel counter of each phase of the inverter;
step S303, for each phase:
if the count value of the output channel counter of the phase is equal to a preset first turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase, and controlling the level turnover of the pulse width modulation signal output by the second bridge arm of the phase, wherein the pulse width modulation signal output by the second bridge arm is opposite to the pulse width modulation signal output by the first bridge arm of the same phase;
if the count value of the output channel counter of the phase is equal to the preset pulse width modulation period count value, controlling the level inversion of the pulse width modulation signal output by the first bridge arm of the phase, controlling the level inversion of the pulse width modulation signal output by the second bridge arm of the phase, wherein the pulse width modulation signal output by the second bridge arm is opposite to the pulse width modulation signal output by the first bridge arm of the same phase, and the first inversion value is smaller than the pulse width modulation period count value;
step S304, for each phase, in each pulse width modulation signal period of the phase, current sampling is performed on a preset first delay time point after a midpoint of a high level or a low level of a pulse width modulation signal output by a first bridge arm of the phase to obtain a sampling current of each phase, and an average value of the sampling currents of all phases is calculated; or alternatively
And for each phase, in each pulse width modulation signal period of the phase, carrying out current sampling on a first delay time point preset after the midpoint of the high level or the low level of the pulse width modulation signal output by the second bridge arm of the phase to obtain the sampling current of each phase, and calculating the average value of the sampling currents of all the phases.
In particular, this example is a specific implementation of phase-shifted pulse width modulated output and phase-shifted average current sampling.
Step S301 is executed, where each output channel operates in a counter single increment mode for each phase, i.e. the count value of the output channel counter of each phase is incremented.
In one embodiment, the output channels of each phase have a count value comparing unit, and when the count value of the corresponding channel counter is equal to the comparison value preset in the count value comparing unit, the level inversion is generated according to the channel working mode, so as to output the preset waveform.
Wherein the count value comparing unit may be provided in a microcontroller, which sets the count value comparing unit for the output channel of each phase.
One of the count value comparing units of the output channel is used for comparing with the output pulse width modulation period count value, thereby outputting a changeable period.
The pulse width modulation period count value is set according to the period time.
In one embodiment, the pwm period count value = pwm period duration/(count value change interval time). The count value change interval time is a change duration of the count value of the output channel counter. The output channel counter outputs a new count value every count value change interval time.
Thus, in step S301, for each phase, if the count value of the output channel counter of the phase is equal to the preset pwm period count value, this indicates that the phase has reached the pwm period duration, and the count value of the output channel counter of the phase is controlled to return to zero, and the incremental count is restarted.
In one embodiment, the start time of the period of the output channel counter of each phase is adjustable.
Aiming at the problem that the phase between the in-phase pulse width modulation output of the inverter and the pulse width modulation output of each phase in the in-phase current sampling scheme is not adjustable, the output channel counter of each phase of the inverter periodically outputs a count value. Since the output channel counters in different phases are independent of each other, the starting time of the period of the output channel counter in each phase is adjustable, so that the starting time of the output period of the multiphase pulse width modulation can be staggered by a certain time (phase), and the phase shifting time (phase) can be adjusted randomly and in real time. Meanwhile, since the initial time of the period of the output channel counter of each phase is adjustable, the embodiment supports real-time switching between the phase shifting mode and the in-phase mode so as to be compatible with and adapt to various application scenes.
In one embodiment, each phase of the inverter includes a first bridge arm and a second bridge arm, and the output channel counter for controlling each phase of the inverter periodically outputs a count value, specifically including:
selecting an output channel counter of a first bridge arm or an output channel counter of a second bridge arm as a main output channel counter of the phase, and selecting an output channel counter of the other bridge arm of the phase as a slave output channel counter of the phase;
the method comprises the steps of controlling a main output channel counter of each phase of an inverter to periodically output a count value, and controlling a slave output channel counter of each phase to follow the output count value of the main output channel counter.
For example, with the first leg output channel of each phase as the master channel, the output channel counter of the master channel as the master output channel counter, and the second leg output channel of that phase as the slave channel, the output channel counter of the slave channel as the slave output channel counter, the period of the output channel counter of the slave channel following the period of the output channel counter of the master channel. The microcontroller controls the main output channel counter to periodically output a count value, so that the main output channel counter is counted up, and when the count value is equal to the pulse width modulation period count value, the count value of the main output channel counter is reset to zero, and the count up is restarted. The slave output channel counter outputs a count value along with the master output channel counter, so that the slave output channel counter also counts up, and when the count value is equal to the pulse width modulation period count value, the count value of the master output channel counter is reset to zero, so that the count value of the slave output channel counter is also reset to zero, and the incremental count is restarted.
In one embodiment, the first bridge arm is an upper bridge arm, and the second bridge arm is a lower bridge arm; or the first bridge arm is a lower bridge arm, and the second bridge arm is an upper bridge arm.
For phase-shifting pulse width modulation output of an inverter, taking a three-phase inverter as an example, a three-phase upper bridge output channel is generally selected as a main channel, and a lower bridge output channel is used as a slave channel, so that the period synchronization of upper and lower bridge driving output of each phase is realized. Meanwhile, the three-phase upper bridge output channel counters should be independent to each other so as to realize the free adjustment of phase shifting time (phase) between each phase.
While the output channel counter periodically outputs the count value, steps S302 to S303 are performed to detect the count value of the output channel counter of each phase of the inverter and control the output of the output channel.
In one embodiment, the output channel has two count value comparison units.
Specifically, the output channel of each bridge arm is provided with two count value comparison units, and when the count value of the corresponding channel counter is equal to the comparison value preset in the count value comparison units, the level inversion is generated according to the channel working mode, so that the preset waveform is output.
And one of the count value comparison units is used for comparing with the output pulse width modulation period count value, and if the count value of the output channel counter of the phase is equal to the preset pulse width modulation period count value, the pulse width modulation signal level inversion output by the first bridge arm of the phase is controlled, the pulse width modulation signal level inversion output by the second bridge arm of the phase is controlled, and the pulse width modulation signal output by the second bridge arm is opposite to the pulse width modulation signal output by the first bridge arm of the same phase.
And controlling the level inversion of the pulse width modulation signal output by the first bridge arm of the phase, namely, if the pulse width modulation signal output by the first bridge arm is high level, the signal is inverted to low level, and if the pulse width modulation signal output by the first bridge arm is low level, the signal is inverted to high level. The pulse width modulation signal output by the second bridge arm is opposite to the pulse width modulation signal output by the first bridge arm of the same phase, namely when the output of the first bridge arm is high level, the output of the second bridge arm is low level, and when the output of the first bridge arm is low level, the output of the second bridge arm is high level. The first bridge arm is an upper bridge arm, the second bridge arm is a lower bridge arm, or the first bridge arm is a lower bridge arm, and the second bridge arm is an upper bridge arm.
The other count value comparison unit of the output channel is used for comparing with the output pulse width modulation level duration count value and adjusting the pulse width modulation duty ratio. The level duration count value is a first flip value, for example, is an upper bridge high level duration count value, that is, a count value corresponding to the upper bridge high level duration. If the count value of the output channel counter of the phase is equal to a preset first turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase, controlling the level turnover of the pulse width modulation signal output by the second bridge arm of the phase, wherein the pulse width modulation signal output by the second bridge arm is opposite to the pulse width modulation signal output by the first bridge arm of the same phase, and the first turnover value is smaller than the count value of the pulse width modulation period.
In one embodiment, the upper bridge high level duration count value = upper bridge high level duration/(count value change interval).
Meanwhile, step S304 is executed, for each phase of average current sampling of the inverter, the current sampling trigger signal of each phase needs to be calculated in real time according to the actual duty ratio of the upper bridge or the lower bridge, and the trigger edge is adjusted to coincide with the vicinity of the high level midpoint or the vicinity of the low level midpoint of the output signal of the upper bridge or the lower bridge. Therefore, the switching moment is avoided as much as possible, interference is reduced, and the sampling result is more accurate. In practical application, a certain delay is inserted after the midpoint of the high level of the lower bridge driving signal, and the delay is used as the practical sampling trigger time.
The initial time of the period of the output channel counter of each phase of the embodiment is adjustable, so that the phase shift time is arbitrary and can be adjusted in real time, and the phase shift time is compatible with and suitable for various application scenes. In the phase shifting mode, the starting moments of the three-phase pulse width modulation output periods can be staggered by any phase between 0 and 360deg, and the phase shifting phase can be adjusted in real time. Meanwhile, each phase selects the output channel counter of one bridge arm as a main output channel counter, and the output channel counter of the other bridge arm is a slave output channel counter following the main output channel counter. So that the two bridge arm periods are synchronous in the same phase, and the phase shifting time (phase) between different phases is freely adjusted. In addition, in the phase shifting mode, three-phase current sampling triggers are adjusted along with the driving output waveform so as to accurately acquire average current in one switching period. Finally, the in-phase mode and the misphase mode can be switched in real time, and unexpected driving output is avoided in the switching process.
Fig. 4 is a timing chart of an inverter pwm control method according to an embodiment of the present invention, wherein the U-phase output channel count value, the V-phase output channel count value, and the W-phase output channel count value are all in a single increment mode, one of the count value comparing units of the upper bridge output channel of each phase is used for comparing with the output pwm period count value, and when the output channel count value reaches the pwm period count value, the output channel count value of the phase is reset to zero, thereby outputting a variable period. And the level of the upper and lower bridge output channels of the phase is flipped. Meanwhile, the lower bridge output channel counter follows the upper bridge output channel counter. As shown in fig. 5, when the output channel count value reaches the pwm period count value, the upper bridge output channel of each phase is turned on, and the output waveform is inverted from low level to high level. While the lower bridge output channel is closed and the output waveform is flipped from high to low.
The other count value comparison unit of the output channel is used for comparing with the output pulse width modulation high-level duration count value and adjusting the pulse width modulation duty ratio. When the count value of the output channel counter of any phase is equal to a preset first turnover value, the level turnover of the pulse width modulation signal output by the upper bridge arm of the phase is controlled, and the level turnover of the pulse width modulation signal output by the lower bridge arm of the phase is controlled. As shown in fig. 5, when the count value of the output channel counter is equal to the preset first inversion value, the upper bridge output channel is turned off, and the output waveform is inverted from the high level to the low level. While the lower bridge output channel is on and the output waveform is flipped from low to high.
Specifically, the existing level inversion mode can be adopted to control the level inversion of the output channel. For example, the switching tube of the output channel is controlled to be opened, so that the output channel is controlled to be opened, a high level is output, and the switching tube of the output channel is controlled to be closed, so that the output channel is controlled to be closed, and a low level is output. When the upper bridge output channel of any phase is turned off, i.e. turned from high level to low level, as shown in fig. 5, the lower bridge output channel is turned on after a certain time delay, and turned from low level to high level. When the lower bridge output channel of any phase is turned off, namely, the lower bridge output channel is turned from a high level to a low level, the upper bridge output channel is turned on after a certain time delay, and the lower bridge output channel is turned from the low level to the high level.
For the three-phase average current sampling of the inverter, the current sampling trigger signals of each phase need to be calculated in real time according to the actual duty ratio of the upper bridge or the lower bridge, and the trigger edges are regulated to coincide with the high-level midpoint or the low-level midpoint of the output signals of the upper bridge or the lower bridge. In practical application, a certain delay is inserted after the high level midpoint or the low level midpoint of the upper bridge or the lower bridge output signal to serve as the practical sampling trigger time. As shown in fig. 5, the trigger edge of the current sampling trigger signal of each phase is delayed after the high level midpoint of the output signal of the lower bridge, and is used as the sampling trigger time. Specifically, a current sample trigger channel counter is set to output a current sample trigger channel count value. The count value employs the same pulse width modulation period as the output channel. And each phase determines a corresponding current sampling trigger comparison value according to the corresponding sampling point, and when the current sampling trigger channel count value is consistent with the current sampling trigger comparison value of the phase, a current sampling trigger signal of the phase is generated.
Fig. 5 is a flowchart illustrating a method for controlling pulse width modulation of an inverter according to still another embodiment of the present invention, where each phase of the inverter includes a first leg and a second leg, the method includes:
step S501, for each phase, if the count value of the output channel counter of the phase is equal to zero, the count value of the output channel counter of the phase is controlled to increment, if the count value of the output channel counter of the phase is equal to the preset half pulse width modulation period count value, the count value of the output channel counter of the phase is controlled to decrement, the output channel counters among different phases are independent from each other, and the start time of the period of the output channel counter of each phase is adjustable.
In one embodiment, the output channel counter for controlling each phase of the inverter periodically outputs a count value, which specifically includes:
selecting an output channel counter of a first bridge arm or an output channel counter of a second bridge arm as a main output channel counter of the phase, and selecting an output channel counter of the other bridge arm of the phase as a slave output channel counter of the phase;
the method comprises the steps of controlling a main output channel counter of each phase of an inverter to periodically output a count value, and controlling a slave output channel counter of each phase to follow the output count value of the main output channel counter.
Step S502, detecting a count value of an output channel counter of each phase of the inverter:
step S503, for each phase:
and if the count value of the output channel counter of the phase is equal to a preset second turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase, and controlling the level turnover of the pulse width modulation signal output by the second bridge arm of the phase, wherein the second turnover value is smaller than the half pulse width modulation period count value.
Step S504, for each phase, current sampling is carried out at a preset second delay time point at which each pulse width modulation signal period of the phase starts to obtain a sampling current of each phase, and an average value of the sampling currents of all phases is calculated; or alternatively
And carrying out current sampling on each phase at a preset second delay time point of the midpoint of each pulse width modulation signal period of the phase to obtain the sampling current of each phase, and calculating the average value of the sampling currents of all the phases.
In particular, this example is a specific implementation of phase-shifted pulse width modulated output and phase-shifted average current sampling. Unlike the previous embodiment, the present embodiment executes step S501, in which each output channel operates in a counter up-down mode for each phase, i.e., for each phase, the count value of the output channel counter of the phase is controlled to be incremented if the count value of the output channel counter of the phase is equal to zero, and the count value of the output channel counter of the phase is controlled to be decremented if the count value of the output channel counter of the phase is equal to a preset half pwm period count value. Wherein the half pwm period count value is half of the pwm period count value.
In one embodiment, the output channels of each phase have a count value comparing unit, and when the count value of the corresponding channel counter is equal to the comparison value preset in the count value comparing unit, the level inversion is generated according to the channel working mode, so as to output the preset waveform.
Wherein the count value comparing unit may be provided in a microcontroller, which sets the count value comparing unit for the output channel of each phase.
One of the count value comparing units of the output channel is used for comparing with the output half pulse width modulation period count value, thereby outputting a variable period.
In one embodiment, the half pwm period count value=1/2×pwm period duration ++count value change interval time. The count value change interval time is a change duration of the count value of the output channel counter. The output channel counter outputs a new count value every count value change interval time.
In one embodiment, the start time of the period of the output channel counter of each phase is adjustable.
Aiming at the problem that the phase between the in-phase pulse width modulation output of the inverter and the pulse width modulation output of each phase in the in-phase current sampling scheme is not adjustable, the output channel counter of each phase of the inverter periodically outputs a count value. Since the output channel counters in different phases are independent of each other, the starting time of the period of the output channel counter in each phase is adjustable, so that the starting time of the output period of the multiphase pulse width modulation can be staggered by a certain time (phase), and the phase shifting time (phase) can be adjusted randomly and in real time. Meanwhile, since the initial time of the period of the output channel counter of each phase is adjustable, the embodiment supports real-time switching between the phase shifting mode and the in-phase mode so as to be compatible with and adapt to various application scenes.
In one embodiment, each phase of the inverter includes a first bridge arm and a second bridge arm, and the output channel counter for controlling each phase of the inverter periodically outputs a count value, specifically including:
selecting an output channel counter of a first bridge arm or an output channel counter of a second bridge arm as a main output channel counter of the phase, and selecting an output channel counter of the other bridge arm of the phase as a slave output channel counter of the phase;
the method comprises the steps of controlling a main output channel counter of each phase of an inverter to periodically output a count value, and controlling a slave output channel counter of each phase to follow the output count value of the main output channel counter.
For inverter phase-shifting pulse width modulation output, taking a three-phase inverter as an example, taking a first bridge arm output channel of each phase as a main channel, taking an output channel counter of the main channel as a main output channel counter, and taking a second bridge arm output channel of the phase as a slave channel, taking an output channel counter of the slave channel as a slave output channel counter. The microcontroller controls the main output channel counter to periodically output a count value, so that the count value of the main output channel counter is equal to zero, the count value of the main output channel counter of the phase is controlled to increment, and the count value of the slave output channel counter is simultaneously controlled to increment along with the count value of the main output channel counter, and if the count value of the main output channel counter of the phase is equal to a preset half pulse width modulation period count value, the count value of the main output channel counter of the phase is controlled to decrement, and the count value of the slave output channel counter is controlled to decrement along with the count value of the main output channel counter.
In one embodiment, the first bridge arm is an upper bridge arm, and the second bridge arm is a lower bridge arm; or the first bridge arm is a lower bridge arm, and the second bridge arm is an upper bridge arm.
Preferably, the upper bridge output channel is also used as a main channel, and the lower bridge output channel is used as a slave channel, so as to realize the period synchronization of the upper and lower bridge driving outputs of each phase.
While the output channel counter periodically outputs the count value, steps S502 to S503 are performed to detect the count value of the output channel counter of each phase of the inverter and control the output of the output channel.
In one embodiment, the output channel has two count value comparison units.
Specifically, the output channel of each bridge arm is provided with two count value comparison units, and when the count value of the corresponding channel counter is equal to the comparison value preset in the count value comparison units, the level inversion is generated according to the channel working mode, so that the preset waveform is output.
One of the count value comparing units of the output channels is used for comparing with the count value of the output half pulse width modulation period, thereby outputting a variable period. I.e. if the count value of the output channel counter of the phase is equal to zero, the count value of the output channel counter of the phase is controlled to increment, and if the count value of the output channel counter of the phase is equal to the preset half pulse width modulation period count value, the count value of the output channel counter of the phase is controlled to decrement.
The other count value comparing unit is used for comparing the level turning moment count value of the bridge arm, namely the second turning value.
And if the count value of the output channel counter of the phase is equal to a preset second turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase, and controlling the level turnover of the pulse width modulation signal output by the second bridge arm of the phase, wherein the second turnover value is smaller than the half pulse width modulation period count value.
Since the rates of counter up-down count are equal, a level inversion event occurs at a time symmetrical about a half cycle, thereby outputting a pulse width modulated signal driving waveform symmetrical about the center of the cycle.
Meanwhile, step S504 is executed, for the three-phase average current sampling of the inverter, since the duty ratio of the pwm output of each phase in the steady state does not change much in the front and rear periods, the embodiment uses this characteristic to set the current sampling trigger edge at the starting time of the pwm period or the midpoint of the pwm signal period, so that the sampling trigger edge is substantially coincident with the high level midpoint or the low level midpoint of the upper and lower bridge driving signals without calculating in real time according to the actual duty ratio of the upper and lower bridges, and adjusting the trigger edge. In practical application, a certain delay is inserted after the starting time of the pulse width modulation signal period or after the midpoint of the pulse width modulation signal period, and the delay is used as the practical sampling trigger time.
The initial time of the period of the output channel counter of each phase of the embodiment is adjustable, so that the phase shift time is arbitrary and can be adjusted in real time, and the phase shift time is compatible with and suitable for various application scenes. In the phase shifting mode, the starting moments of the three-phase pulse width modulation output periods can be staggered by any phase between 0 and 360 degrees, and the phase shifting phase can be adjusted in real time. Meanwhile, each phase selects the output channel counter of one bridge arm as a main output channel counter, and the output channel counter of the other bridge arm is a slave output channel counter following the main output channel counter. So that the two bridge arm periods are synchronous in the same phase, and the phase shifting time (phase) between different phases is freely adjusted. In addition, in the phase shifting mode, three-phase current sampling triggering can accurately acquire average current in one switching period without adjusting along with driving output waveforms. Finally, the in-phase mode and the misphase mode can be switched in real time, and unexpected driving output is avoided in the switching process.
As shown in fig. 6, in a timing chart of a pulse width modulation control method of an inverter according to another embodiment of the present invention, the count value of the U-phase output channel, the count value of the V-phase output channel, and the count value of the W-phase output channel are all in an up-down mode, one of the count value comparing units of the upper bridge output channels of each phase is used for comparing with the output half pulse width modulation period count value, when the count value of the output channel is equal to zero, the count value of the upper bridge output channel counter is incremented, and if the count value of the upper bridge output channel counter of the phase is equal to the preset half pulse width modulation period count value, the count value of the upper bridge output channel counter is controlled to be decremented, thereby outputting a variable period. At the same time, the lower bridge output channel counter of each phase follows the upper bridge output channel counter.
The other count value comparison unit of the output channel is used for comparing with the level inversion moment count value of the bridge arm and adjusting the pulse width modulation duty ratio. When the count value of the output channel counter of any phase is equal to the level inversion time count value, the level inversion of the pulse width modulation signal output by the upper bridge arm of the phase is controlled, and the level inversion of the pulse width modulation signal output by the lower bridge arm of the phase is controlled. As shown in fig. 6, when the count value of the output channel counter is equal to the level inversion time count value, the upper bridge output channel is turned off, the output waveform is inverted from the high level to the low level, and the lower bridge output channel is turned on, and the output waveform is inverted from the low level to the high level. Or the upper bridge output channel is opened, the output waveform is turned from a low level to a high level, and the lower bridge output channel is closed, and the output waveform is turned from a high level to a low level.
As shown in fig. 7, taking the U-phase as an example, the U-phase lower bridge output channel counter follows the change of the U-phase upper bridge output channel count value. At the beginning of the pwm period, the upper bridge of the U-phase is low and the lower bridge of the U-phase is high. The comparison value of the U-phase upper bridge opening time and the comparison value of the U-phase lower bridge opening time are the same as the half pulse width modulation period count value. When the count value of the U-phase upper bridge output channel reaches the comparison value of the U-phase upper bridge opening time for the first time, the U-phase upper bridge is turned from low level to high level. Meanwhile, the count value of the U-phase lower bridge output channel also reaches the comparison value of the U-phase lower bridge opening time for the first time, and the U-phase lower bridge is turned from high level to low level. When the count value of the U-phase upper bridge output channel reaches the comparison value of the U-phase upper bridge opening time for the second time, the U-phase upper bridge is turned from high level to low level. Meanwhile, the count value of the U-phase lower bridge output channel also reaches the comparison value of the U-phase lower bridge opening time for the second time, and the U-phase lower bridge is turned from low level to high level.
Specifically, the existing level inversion mode can be adopted to control the level inversion of the output channel. For example, the switching tube of the output channel is controlled to be opened, so that the output channel is controlled to be opened, a high level is output, and the switching tube of the output channel is controlled to be closed, so that the output channel is controlled to be closed, and a low level is output. When the upper bridge output channel of any phase is turned off, i.e. turned from a high level to a low level, as shown in fig. 6 and 7, the lower bridge output channel is turned on after a certain time delay, and turned from the low level to the high level. When the lower bridge output channel of any phase is turned off, namely, the lower bridge output channel is turned from a high level to a low level, the upper bridge output channel is turned on after a certain time delay, and the lower bridge output channel is turned from the low level to the high level.
As shown in fig. 6, for sampling the three-phase average current of the inverter, since the duty ratio of the pwm output of each phase in the steady state does not change much in the front and rear periods, the embodiment uses this characteristic to set the current sampling trigger edge at the starting time of the pwm period, and the sampling trigger edge and the high level midpoint of the lower bridge driving signal can be substantially overlapped without calculating in real time the actual duty ratio of the upper bridge and the lower bridge, and adjusting the trigger edge. In practical application, a certain delay is inserted after the starting time of the pulse width modulation signal period and is used as the practical sampling trigger time. Specifically, a current sample trigger channel counter is set to output a current sample trigger channel count value. The count value employs the same pulse width modulation period as the output channel. And each phase determines a corresponding current sampling trigger comparison value according to the corresponding sampling point, and when the current sampling trigger channel count value is consistent with the current sampling trigger comparison value of the phase, a current sampling trigger signal of the phase is generated.
Fig. 8 is a schematic diagram of an inverter pwm control device according to the present invention, including:
a count value detection module 801, configured to control an output channel counter of each phase of the inverter to periodically output a count value, where the output channel counters of different phases are independent;
the output control module 802 is configured to detect a count value of an output channel counter of each phase of the inverter, and control a pulse width modulation signal of an output channel of a phase corresponding to the output channel counter according to the count value of the output channel counter of each phase.
In one embodiment, the start time of the period of the output channel counter of each phase is adjustable.
In one embodiment, each phase of the inverter includes a first bridge arm and a second bridge arm, and the output channel counter for controlling each phase of the inverter periodically outputs a count value, specifically including:
selecting an output channel counter of a first bridge arm or an output channel counter of a second bridge arm as a main output channel counter of the phase, and selecting an output channel counter of the other bridge arm of the phase as a slave output channel counter of the phase;
the method comprises the steps of controlling a main output channel counter of each phase of an inverter to periodically output a count value, and controlling a slave output channel counter of each phase to follow the output count value of the main output channel counter.
In one embodiment, each phase of the inverter includes a first leg and a second leg;
the output channel counter for controlling each phase of the inverter periodically outputs a count value, and specifically includes:
for each phase:
controlling the count value of the output channel counter of each phase to be increased, and controlling the count value of the output channel counter of the phase to be zeroed if the count value of the output channel counter of the phase is equal to the preset pulse width modulation period count value;
according to the count value of the output channel counter of each phase, the pulse width modulation signal output by the first bridge arm and the pulse width modulation signal output by the second bridge arm of the phase corresponding to the output channel counter are controlled, and the method specifically comprises the following steps:
for each phase:
if the count value of the output channel counter of the phase is equal to a preset first turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase and the level turnover of the pulse width modulation signal output by the second bridge arm of the phase;
and if the count value of the output channel counter of the phase is equal to the preset pulse width modulation period count value, controlling the pulse width modulation signal level output by the first bridge arm of the phase to overturn, and controlling the pulse width modulation signal level output by the second bridge arm of the phase to overturn, wherein the first overturn value is smaller than the pulse width modulation period count value.
In one embodiment, the method further comprises:
in each pulse width modulation signal period of each phase, current sampling is carried out on a first delay time point preset after the midpoint of a high level or a low level of a pulse width modulation signal output by a first bridge arm of the phase to obtain sampling current of each phase, and the average value of the sampling current of all the phases is calculated; or alternatively
And for each phase, in each pulse width modulation signal period of the phase, carrying out current sampling on a first delay time point preset after the midpoint of the high level or the low level of the pulse width modulation signal output by the second bridge arm of the phase to obtain the sampling current of each phase, and calculating the average value of the sampling currents of all the phases.
In one embodiment, each phase of the inverter includes a first leg and a second leg;
the output channel counter for controlling each phase of the inverter periodically outputs a count value, and specifically includes:
for each phase, if the count value of the output channel counter of the phase is equal to zero, the count value of the output channel counter of the phase is controlled to be increased, and if the count value of the output channel counter of the phase is equal to the preset half pulse width modulation period count value, the count value of the output channel counter of the phase is controlled to be decreased;
According to the count value of the output channel counter of each phase, the pulse width modulation signal output by the first bridge arm and the pulse width modulation signal output by the second bridge arm of the phase corresponding to the output channel counter are controlled, and the method specifically comprises the following steps:
for each phase:
and if the count value of the output channel counter of the phase is equal to a preset second turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase, and controlling the level turnover of the pulse width modulation signal output by the second bridge arm of the phase, wherein the second turnover value is smaller than the half pulse width modulation period count value.
In one embodiment, the method further comprises:
carrying out current sampling on each phase at a preset second delay time point of each pulse width modulation signal period of the phase to obtain sampling current of each phase, and calculating average value of the sampling currents of all phases; or alternatively
And carrying out current sampling on each phase at a preset second delay time point of the midpoint of each pulse width modulation signal period of the phase to obtain the sampling current of each phase, and calculating the average value of the sampling currents of all the phases.
The pulse width modulation signals of the output channels of each phase of the inverter are controlled by the count value of the output channel counter, the output channel counter of each phase of the inverter periodically outputs the count value, and the output channel counters among different phases are mutually independent, so that the pulse width modulation signals output by each bridge of each phase can be independently controlled through the independent output channel counter, thereby greatly improving the flexibility of the pulse width modulation output driving scheme of the inverter and being suitable for wider application occasions.
Fig. 9 is a schematic diagram of a hardware structure of an electronic device according to the present invention, including:
at least one processor 901; the method comprises the steps of,
a memory 902 communicatively coupled to at least one of the processors 901; wherein,
the memory 902 stores instructions executable by at least one of the processors to enable the at least one processor to perform the inverter pulse width modulation control method as previously described.
In fig. 9, a processor 901 is taken as an example.
The electronic device may further include: an input device 903 and a display device 904.
The processor 901, memory 902, input device 903, and display device 904 may be connected by a bus or other means, the connection being illustrated as a bus.
The memory 902 is used as a non-volatile computer readable storage medium, and may be used to store a non-volatile software program, a non-volatile computer executable program, and modules, such as program instructions/modules corresponding to the inverter pwm control method in the embodiments of the present application, for example, the method flow shown in fig. 2. The processor 901 executes various functional applications and data processing by running nonvolatile software programs, instructions, and modules stored in the memory 902, i.e., implements the inverter pulse width modulation control method in the above-described embodiment.
The memory 902 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the inverter pulse width modulation control method, and the like. In addition, the memory 902 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 902 optionally includes memory remotely located relative to the processor 901, which may be connected via a network to a device performing the inverter pulse width modulation control method. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 903 may receive input user clicks and generate signal inputs related to user settings and function control of the inverter pwm control method. The display device 904 may include a display apparatus such as a display screen.
The inverter pulse width modulation control method of any of the method embodiments described above is performed when executed by the one or more processors 901, with the one or more modules stored in the memory 902.
The pulse width modulation signals of the output channels of each phase of the inverter are controlled by the count value of the output channel counter, the output channel counter of each phase of the inverter periodically outputs the count value, and the output channel counters among different phases are mutually independent, so that the pulse width modulation signals output by each bridge of each phase can be independently controlled through the independent output channel counter, thereby greatly improving the flexibility of the pulse width modulation output driving scheme of the inverter and being suitable for wider application occasions.
An embodiment of the invention provides a storage medium storing computer instructions that, when executed by a computer, perform all the steps of an inverter pulse width modulation control method as described above.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. An inverter pulse width modulation control method, comprising:
the method comprises the steps of controlling an output channel counter of each phase of an inverter to periodically output a count value, wherein the output channel counters of different phases are mutually independent;
detecting the count value of an output channel counter of each phase of the inverter;
and controlling the pulse width modulation signal of the output channel of the corresponding phase of the output channel counter according to the count value of the output channel counter of each phase.
2. The inverter pwm control method according to claim 1, wherein a start timing of a period of the output channel counter of each phase is adjustable.
3. The inverter pulse width modulation control method according to claim 1, wherein each phase of the inverter includes a first leg and a second leg, and the output channel counter controlling each phase of the inverter periodically outputs a count value, specifically comprising:
selecting an output channel counter of a first bridge arm or an output channel counter of a second bridge arm as a main output channel counter of the phase, and selecting an output channel counter of the other bridge arm of the phase as a slave output channel counter of the phase;
the method comprises the steps of controlling a main output channel counter of each phase of an inverter to periodically output a count value, and controlling a slave output channel counter of each phase to follow the output count value of the main output channel counter.
4. The inverter pulse width modulation control method of claim 1, wherein each phase of the inverter comprises a first leg and a second leg;
the output channel counter for controlling each phase of the inverter periodically outputs a count value, and specifically includes:
for each phase:
controlling the count value of the output channel counter of each phase to be increased, and controlling the count value of the output channel counter of the phase to be zeroed if the count value of the output channel counter of the phase is equal to the preset pulse width modulation period count value;
according to the count value of the output channel counter of each phase, the pulse width modulation signal output by the first bridge arm and the pulse width modulation signal output by the second bridge arm of the phase corresponding to the output channel counter are controlled, and the method specifically comprises the following steps:
for each phase:
if the count value of the output channel counter of the phase is equal to a preset first turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase and the level turnover of the pulse width modulation signal output by the second bridge arm of the phase;
and if the count value of the output channel counter of the phase is equal to the preset pulse width modulation period count value, controlling the pulse width modulation signal level output by the first bridge arm of the phase to overturn, and controlling the pulse width modulation signal level output by the second bridge arm of the phase to overturn, wherein the first overturn value is smaller than the pulse width modulation period count value.
5. The inverter pulse width modulation control method of claim 4, further comprising:
in each pulse width modulation signal period of each phase, current sampling is carried out on a first delay time point preset after the midpoint of a high level or a low level of a pulse width modulation signal output by a first bridge arm of the phase to obtain sampling current of each phase, and the average value of the sampling current of all the phases is calculated; or alternatively
And for each phase, in each pulse width modulation signal period of the phase, carrying out current sampling on a first delay time point preset after the midpoint of the high level or the low level of the pulse width modulation signal output by the second bridge arm of the phase to obtain the sampling current of each phase, and calculating the average value of the sampling currents of all the phases.
6. The inverter pulse width modulation control method of claim 1, wherein each phase of the inverter comprises a first leg and a second leg;
the output channel counter for controlling each phase of the inverter periodically outputs a count value, and specifically includes:
for each phase, if the count value of the output channel counter of the phase is equal to zero, the count value of the output channel counter of the phase is controlled to be increased, and if the count value of the output channel counter of the phase is equal to the preset half pulse width modulation period count value, the count value of the output channel counter of the phase is controlled to be decreased;
According to the count value of the output channel counter of each phase, the pulse width modulation signal output by the first bridge arm and the pulse width modulation signal output by the second bridge arm of the phase corresponding to the output channel counter are controlled, and the method specifically comprises the following steps:
for each phase:
and if the count value of the output channel counter of the phase is equal to a preset second turnover value, controlling the level turnover of the pulse width modulation signal output by the first bridge arm of the phase, and controlling the level turnover of the pulse width modulation signal output by the second bridge arm of the phase, wherein the second turnover value is smaller than the half pulse width modulation period count value.
7. The inverter pulse width modulation control method of claim 6, further comprising:
carrying out current sampling on each phase at a preset second delay time point of each pulse width modulation signal period of the phase to obtain sampling current of each phase, and calculating average value of the sampling currents of all phases; or alternatively
And carrying out current sampling on each phase at a preset second delay time point of the midpoint of each pulse width modulation signal period of the phase to obtain the sampling current of each phase, and calculating the average value of the sampling currents of all the phases.
8. An inverter pulse width modulation control device, comprising:
the count value detection module is used for controlling the output channel counter of each phase of the inverter to periodically output a count value, and the output channel counters among different phases are mutually independent;
the output control module is used for detecting the count value of the output channel counter of each phase of the inverter and controlling the pulse width modulation signal of the output channel of the corresponding phase of the output channel counter according to the count value of the output channel counter of each phase.
9. An electronic device, comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to at least one of the processors; wherein,
the memory stores instructions executable by at least one of the processors to enable the at least one of the processors to perform the inverter pulse width modulation control method of any one of claims 1 to 7.
10. A storage medium storing computer instructions which, when executed by a computer, are adapted to carry out all the steps of the inverter pulse width modulation control method according to any one of claims 1 to 7.
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2022
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