CN113965053A

CN113965053A - PWM narrow pulse eliminating method and single-phase and three-phase PWM narrow pulse eliminating device

Info

Publication number: CN113965053A
Application number: CN202111257962.1A
Authority: CN
Inventors: 付厚; 刘嘉明; 吴立建; 方杭杭; 田超; 李爽; 张鲁华
Original assignee: Zhejiang University ZJU; Shanghai Electric Wind Power Group Co Ltd
Current assignee: Zhejiang University ZJU; Shanghai Electric Wind Power Group Co Ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2022-01-21

Abstract

The application provides a PWM narrow pulse elimination method and a single-phase and three-phase PWM narrow pulse elimination device, wherein the method comprises the following steps: s11, acquiring carrier data; s12, processing the carrier data based on the triangular wave periodic signal and the dead time of the upper power tube and the lower power tube to obtain PWM data of the upper power tube and the lower power tube; s13, respectively determining whether narrow pulses with pulse widths smaller than the minimum pulse width exist in the PWM data of the upper power tube and/or the lower power tube according to the PWM data of the upper power tube and the lower power tube; and S14, if the narrow pulse exists, deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal. The method compensates the influence of eliminating the narrow pulse, reduces the influence of eliminating the narrow pulse on the control performance, reduces the control error caused by eliminating the narrow pulse, and reduces the output ripple.

Description

PWM narrow pulse eliminating method and single-phase and three-phase PWM narrow pulse eliminating device

Technical Field

The application relates to the technical field of wind power, in particular to a PWM (pulse-width modulation) narrow pulse eliminating method and a single-phase and three-phase PWM narrow pulse eliminating device.

Background

In a converter of a wind generating set, PWM driving of a power device is directly related to energy conversion and transmission, for example, a narrow pulse in a PWM signal cannot completely turn on or off an IGBT (Insulated Gate Bipolar Transistor) of the converter, so that a peak voltage is too high when the IGBT is turned off, and meanwhile, switching loss is increased, which directly affects service life and loss of the power device.

By deleting the narrow pulse with the pulse width smaller than the set value, the influence of incomplete switching-on and switching-off on the power device can be well reduced. But the accuracy and the smoothness performance of the control are affected while the narrow pulses are deleted.

Disclosure of Invention

The application provides a PWM narrow pulse elimination method and a single-phase and three-phase PWM narrow pulse elimination device.

Specifically, the method is realized through the following technical scheme:

in a first aspect of the embodiments of the present application, a PWM narrow pulse cancellation method is provided, where the PWM narrow pulse cancellation method is used to control an upper power transistor and a lower power transistor, and the method includes: acquiring carrier data; processing the carrier data based on a triangular wave periodic signal and the dead time of the upper power tube and the lower power tube to obtain PWM data of the upper power tube and the lower power tube; respectively determining whether narrow pulses with pulse widths smaller than the minimum pulse width exist in the PWM data of the upper power tube and/or the lower power tube according to the PWM data of the upper power tube and the lower power tube; and if the narrow pulse exists, deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal.

In a second aspect of the embodiments of the present application, there is provided a single-phase PWM narrow pulse cancellation apparatus, including one or more processors, configured to implement the PWM narrow pulse cancellation method according to the first aspect.

In a third aspect of the embodiments of the present application, there is provided a three-phase PWM narrow pulse cancellation apparatus applied to a converter of a wind turbine generator system, where the converter includes an a-phase upper power transistor, an a-phase lower power transistor, a B-phase upper power transistor, a B-phase lower power transistor, and a C-phase upper power transistor, and the C-phase PWM narrow pulse cancellation apparatus includes the a-phase PWM narrow pulse cancellation apparatus, the B-phase PWM narrow pulse cancellation apparatus, and the C-phase PWM narrow pulse cancellation apparatus includes the single-phase PWM narrow pulse cancellation apparatus according to the second aspect.

According to the technical scheme provided by the embodiment of the application, the narrow pulse is deleted or the pulse width of the narrow pulse is compensated by combining the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal, so that the aim of eliminating the narrow pulse is fulfilled, the loss of the power tube is reduced, the service life of the power tube is prolonged, and the work of the power tube can be well ensured; meanwhile, the influence of eliminating the narrow pulse is compensated, the influence of eliminating the narrow pulse on the control performance is reduced while the utilization rate and the linear adjustment range of the direct-current busbar voltage are ensured, the control error caused by eliminating the narrow pulse is reduced, and the output ripple is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow chart diagram illustrating a PWM narrow pulse cancellation method according to an exemplary embodiment of the present application;

fig. 2 is a schematic waveform diagram of upper power tube PWM data and lower power tube PWM data generated according to an exemplary embodiment of the present application;

FIG. 3 is a detailed diagram of waveforms of a generated upper power tube PWM data and a generated lower power tube PWM data according to an exemplary embodiment of the present application;

FIG. 4 is a PWM waveform diagram of the upper and lower power transistors without a narrow pulse condition according to an exemplary embodiment of the present application;

fig. 5 is a diagram illustrating PWM data of an upper power transistor having conducting narrow pulses and narrow pulse compensation in the first half of the current operating time period T2 according to an exemplary embodiment of the present application;

fig. 6 is a diagram illustrating PWM data of an upper power transistor having conducting narrow pulses and narrow pulse compensation in the second half of the current duty cycle T2 according to an exemplary embodiment of the present application;

fig. 7 is a graph illustrating the existence of a narrow pulse and the deletion of the narrow pulse in the second half of the current on-time period T2 of PWM data of an upper power transistor according to an exemplary embodiment of the present application;

fig. 8 is a diagram illustrating PWM data of an upper power transistor with a narrow off pulse and a narrow pulse deletion (narrow pulse of a lower power transistor follows the deletion) in the middle of the current operating time period T2 according to an exemplary embodiment of the present application;

fig. 9 is a graph illustrating the presence of a narrow pulse and a narrow pulse compensation in the first half period of the current on-time period T2 for PWM data of a lower power transistor according to an exemplary embodiment of the present application;

fig. 10 is a diagram illustrating the narrow pulse and the narrow pulse deletion (the narrow pulse of the upper power tube follows the deletion) of the PWM data of the lower power tube in the second half of the current on-time period T2 according to an exemplary embodiment of the present application;

fig. 11 is a diagram illustrating PWM data of a lower power transistor with a narrow off pulse and a narrow pulse deleting diagram in the middle of the current duty cycle T2 according to an exemplary embodiment of the present application;

fig. 12 is a schematic structural diagram of a PWM narrow pulse elimination apparatus according to an exemplary embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

The PWM narrow pulse elimination method and the single-phase and three-phase PWM narrow pulse elimination apparatus according to the present application will be described in detail below with reference to the accompanying drawings. The features of the following examples and embodiments may be combined with each other without conflict.

It should be noted that the PWM narrow pulse cancellation method according to the embodiment of the present application may be used to control an upper power transistor and a lower power transistor, for example, to control an upper power transistor and a lower power transistor of the same bridge arm in a converter of a wind turbine generator system.

FIG. 1 is a schematic flow chart diagram illustrating a PWM narrow pulse cancellation method according to an exemplary embodiment of the present application; as shown in fig. 1, the PWM narrow pulse elimination method provided in the embodiment of the present application may include steps S11 to S16.

In S11, carrier data is acquired.

In S12, carrier data is processed based on the triangular wave periodic signal and the dead time of the upper power tube and the lower power tube, and PWM data of the upper power tube and the lower power tube is obtained.

In the step, carrier data can be modulated by utilizing a triangular wave periodic signal to generate PWM data of an upper power tube and a lower power tube, dead zone time is added into the PWM data to obtain the PWM data after the dead zone is added, so that the dead zone of the upper power tube and the dead zone of the lower power tube are normal, and the upper power tube and the lower power tube of the same bridge arm are prevented from being conducted at the same time to form short circuit.

The triangular wave signal may be generated based on the synchronization signal, and the generation process of the triangular wave periodic signal may include: when the rising edge of the synchronization signal comes, the counter is set to 1, then each working clock counter is started to add 1, and when the counting is half of the period value of the working clock period, the counter starts to count down until 1 stops counting down and waits for the synchronization signal to start the next period counting. If the sync signal counts down to 1 prior to the counter, the counter is directly set to 1 and the next cycle count is started. The up count of the counter is represented as the first half period, the down count is represented as the second half period, and the high and low levels are used to represent the first half period, for example, the low level 0 represents the first half period, and the high level 1 represents the second half period. A working clock period consists of a first half period and a second half period, and the real-time count value of the triangular wave periodic signal is increased progressively in the first half period and decreased progressively in the second half period. Hereinafter, the operating clock PERIOD of the triangular wave periodic signal may be denoted by MOD _ PERIOD.

The clock frequency corresponding to the duty clock period may be 50MHZ, but is not limited to 50MHZ, and other clock frequencies may be used.

In one possible embodiment, the relevant data is stored and represented by the lower register, the carrier data is represented by sin _ data _ reg, the upper power tube comparison register value of the first half period (i.e., PWM data of the upper power tube of the first half period) is represented by sin _ data _ calc _ up, the lower power tube comparison register value of the first half period (i.e., PWM data of the lower power tube of the first half period) is represented by sin _ data _ calc _ down, the upper power tube comparison register value of the second half period (i.e., PWM data of the upper power tube of the second half period) is represented by sin _ data _ calc _ up _ sec, the lower power tube comparison register value of the second half period (i.e., PWM data of the lower power tube of the second half period) is represented by sin _ data _ calc _ down _ sec, and the dead time (i.e., dead zone width) is represented by IGBT _ DT.

In this step, sin _ data _ calc _ up ═ sin _ data _ reg;

sin_data_calc_down＝sin_data_reg+IGBT_DT；

sin_data_calc_up_sec＝sin_data_reg-IGBT_DT；

sin_data_calc_down_sec＝sin_data_reg。

in one embodiment, the PWM data generation method may include the steps of:

(1) and receiving an external synchronization signal.

(2) And outputting the synchronous signal according to the working clock period generated by the PWM signal based on the external synchronous signal in the step (1).

(3) And generating a half-cycle signal of the triangular wave and a triangular wave real-time count value tb _ ctr _ reg based on the synchronous signal output in the step (2).

(4) And processing the carrier data based on the working clock period, the dead time of the upper power tube and the lower power tube, and (3) the output half-period signal to obtain processed carrier data, as shown in fig. 2.

Specifically, carrier data is adjusted based on a working clock period and dead time to obtain adjusted carrier data; adding the dead zone time into the adjusted carrier data to obtain carrier data after the dead zone is added; and updating the carrier data after the dead zone is added based on the half-cycle signal to obtain updated carrier data, wherein the processed carrier data comprises the updated carrier data.

In order to prevent the upper power tube and the lower power tube of the same bridge arm from being conducted at the same time to form a short circuit, the dead zone of the upper power tube and the lower power tube can be controlled, and the conduction time point of the upper power tube and the lower power tube can be controlled by adopting a control strategy of immediately turning off and delaying conduction.

In some embodiments, referring to fig. 3, adjusting the carrier data based on the duty cycle and the dead time to obtain the adjusted carrier data specifically may include: comparing the carrier data sin _ data _ reg with a difference value between a half-PERIOD value MOD _ PERIOD/2 of the triangular wave and a dead time IGBT _ DT and the dead time IGBT _ DT respectively, wherein the half-PERIOD value MOD _ PERIOD/2 of the triangular wave is half of the working clock PERIOD; and adjusting the carrier data based on the comparison result of the carrier data sin _ data _ reg with the difference value (MOD _ PERIOD/2-IGBT _ DT) and the dead time IGBT _ DT respectively. When the carrier data sin _ data _ reg is larger than the difference between the half-PERIOD value MOD _ PERIOD/2 of the triangular wave and the dead time IGBT _ DT, namely sin _ data _ reg > (MOD _ PERIOD/2-IGBT _ DT), the carrier data sin _ data _ reg is reassigned to the difference MOD _ PERIOD/2-IGBT _ DT, namely sin _ data _ reg1 (MOD _ PERIOD/2-IGBT _ DT); when the carrier data sin _ data _ reg is smaller than the dead time IGBT _ DT, the carrier data sin _ data _ reg is reassigned to the dead time IGBT _ DT, namely sin _ data _ reg1 is equal to IGBT _ DT; otherwise, no adjustment is made to the carrier data sin _ data _ reg, i.e., sin _ data _ reg1 is equal to sin _ data _ reg. Therefore, the dead zone of the upper power tube and the lower power tube can be ensured to be normal.

Adding the dead zone time to the adjusted carrier data to obtain the dead zone added carrier data may specifically include: and calculating edge time points of an upper power tube and a lower power tube based on the dead time IGBT _ DT and the adjusted carrier data sin _ data _ reg1 to obtain carrier data after dead time is added. The carrier data after the dead zone is added comprises a power tube comparison register value sin _ data _ calc _ up on the first half period, a power tube comparison register value sin _ data _ calc _ down on the first half period, a power tube comparison register value sin _ data _ calc _ up _ sec on the second half period and a power tube comparison register value sin _ data _ calc _ down _ sec on the second half period. The power tube comparison register value on the first half period is equal to the adjusted carrier data, namely sin _ data _ calc _ up which is sin _ data _ reg 1; the comparison register value of the power tube under the first half period is equal to the adjusted carrier data plus dead time, namely sin _ data _ calc _ down (sin _ data _ reg1+ IGBT _ DT); the value of the power tube comparison register on the second half period is equal to the adjusted carrier data minus dead time, namely sin _ data _ calc _ up _ sec is sin _ data _ reg 1-IGBT _ DT; and the power tube compare register value is equal to the adjusted carrier data in the second half cycle, i.e. sin _ data _ calc _ down _ sec is sin _ data _ reg 1.

Updating the carrier data after the dead zone is added based on the half-cycle signal to obtain updated carrier data specifically may include: and respectively setting a power tube comparison register value on the first half period, a power tube comparison register value under the first half period, a power tube comparison register value on the second half period and a power tube comparison register value under the second half period at the level switching position of the half period signal to obtain updated carrier data. The updated carrier data includes the upper power tube comparison register current value sin _ data _ calc _ up _ current and the lower power tube comparison register current value sin _ data _ calc _ down _ current when the half cycle signal switches from the first level to the second level position, and the upper power tube comparison register current value sin _ data _ calc _ up _ current and the lower power tube comparison register current value sin _ data _ calc _ down _ current when the half cycle signal switches from the second level to the first level position. The current values sin _ data _ calc _ up _ current and sin _ data _ calc _ up _ current of the upper power tube comparison register when the half-period signal is switched from the first level to the second level position are respectively equal to the values sin _ data _ calc _ up and sin _ data _ calc _ down of the upper power tube comparison register in the first half period, and the current values sin _ data _ calc _ up _ current and sin _ data _ calc _ up _ current of the lower power tube comparison register when the half-period signal is switched from the second level to the first level position are respectively equal to the values sin _ data _ calc _ up _ current and sin _ data _ calc _ up _ current of the upper power tube comparison register in the second period and sin _ data _ calc _ up _ current of the lower power tube comparison register in the second period.

(5) And comparing the carrier wave data processed in the step (4) with the triangular wave real-time count value tb _ ctr _ reg output in the step (3) every working clock period to generate upper power tube PWM data and lower power tube PWM data.

Specifically, in each working clock cycle, the current values sin _ data _ calc _ up _ current of the upper power tube comparison register and the current values sin _ data _ calc _ down _ current of the lower power tube comparison register are respectively compared with a triangular wave real-time count value tb _ ctr _ reg; and generating an upper power tube PWM signal and a lower power tube PWM signal based on the comparison result of the current values sin _ data _ calc _ up _ current of the upper power tube comparison register and the current values sin _ data _ calc _ down _ current of the lower power tube comparison register and the triangular wave real-time count value tb _ ctr _ reg. For example, if the current value sin _ data _ calc _ up _ current of the comparison register of the upper power tube is smaller than the triangular wave real-time count value tb _ ctr _ reg, the upper power tube outputs a low level; otherwise, the upper power tube outputs a high level. If the current value sin _ data _ calc _ down _ current of the comparison register of the lower power tube is greater than the triangular wave real-time count value tb _ ct r _ reg, the lower power tube outputs a low level; otherwise, the lower power tube outputs high level.

In S13, it is determined whether there is a narrow pulse having a pulse width smaller than the minimum pulse width in the PWM data of the upper power tube and/or the lower power tube, respectively, according to the PWM data of the upper power tube and the lower power tube.

The pulse width of each pulse in the current working clock period of the upper power tube and the lower power tube can be determined by adopting a counter calculation mode. The minimum narrow PULSE width may be represented by MIN _ PULSE, and in this step, if the PULSE width is less than the minimum narrow PULSE width MIN _ PULSE, it is indicated that the corresponding PULSE is a narrow PULSE.

In this embodiment, the pulse includes two types of on pulse (controlling the corresponding power transistor to be turned on) and off pulse (controlling the corresponding power transistor to be turned off).

In S14, if any, the narrow pulse is deleted or the pulse width of the narrow pulse is compensated for according to the position of the narrow pulse in the current operation clock cycle of the triangular wave periodic signal.

Determining the position of the narrow pulse in the current working clock cycle needs to determine whether the narrow pulse is located at the start time of the first half cycle of the current working clock cycle, or located at the end time of the second half cycle of the current working clock cycle, or located in the middle of the working clock cycle (i.e. the peak region of the triangular wave periodic signal).

In addition, if the upper power tube and the lower power tube do not have the narrow pulse with the pulse width smaller than the minimum pulse width in the current working clock period, the narrow pulse elimination processing of the PWM data of the upper power tube and the lower power tube in the current working period is not needed. As shown in fig. 4, the PULSE width D1 is greater than the minimum narrow PULSE width MIN _ PULSE, and the PULSE width D2 is also greater than the minimum narrow PULSE width MIN _ PULSE, so that the narrow PULSE cancellation processing for the PWM data of the upper power tube and the lower power tube in the current duty cycle is not required.

In fig. 4, T1 and T2 are both one duty clock cycle of the triangular wave PERIOD information, and T1 is T2 is MOD _ PERIOD.

The implementation manner of deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal in S14 may include various ways.

The following describes the elimination of the narrow pulses in the PWM data of the upper power transistor and the elimination of the narrow pulses in the PWM data of the lower power transistor, respectively. In fig. 4 to 11, the broken line indicates PWM data before the narrow pulse in the PWM data is eliminated.

1. And eliminating the narrow pulse in the PWM data of the upper power tube.

In some embodiments, the pulse width of the narrow pulse is compensated when the narrow pulse is at the beginning of the first half-cycle of the current operating clock cycle. Specifically, when the narrow pulse exists in the PWM data of the upper power tube at the starting moment of the first half period of the current working clock cycle and is a conducting pulse, the falling edge of the narrow pulse is moved backwards until the pulse width of the narrow pulse is equal to the minimum pulse width; and the rising edge of the turn-off pulse corresponding to the narrow pulse on the PWM data of the lower power tube is followed and moved backwards.

As shown in fig. 5, since the PULSE width D3 is smaller than the minimum narrow PULSE width MIN _ PULSE, the corresponding PULSE (the PULSE of the upper power transistor directly facing the position D3 in fig. 5) is a narrow PULSE, the PULSE width of the narrow PULSE can be compensated, the compensation width value is the difference between the minimum narrow PULSE width MIN _ PULSE and the PULSE width D3, that is, the compensation width value (MIN _ PULSE-D3), and the rising edge of the off PULSE corresponding to the narrow PULSE on the PWM data of the lower power transistor is shifted backward by the compensation width value (MIN _ PULSE-D3) to eliminate the narrow PULSE. Meanwhile, the rising edge of the turn-off pulse corresponding to the narrow pulse on the PWM data of the lower power tube moves backwards along with the turn-off pulse, so that the dead zone of the upper power tube and the dead zone of the lower power tube are normal. Thus, the comparison register values of the upper power tube and the lower power tube after the adjustment of the previous half period are obtained:

sin_data_calc_up＝MIN_PULSE-sin_data_calc_up_current；

sin_data_calc_down＝MIN_PULSE-sin_data_calc_up_current+IGBT_DT。

in other embodiments, when the narrow pulse is at the end of the second half of the current working clock cycle, the narrow pulse is deleted or the pulse width of the narrow pulse is compensated according to the power tube to which the narrow pulse belongs. For the upper power tube, namely when the PWM data of the upper power tube has a narrow pulse at the end time of the latter half period of the current working clock period and the narrow pulse is a conduction pulse, determining the conduction time of the conduction pulse positioned at the start time of the former half period of the current working clock period in the PWM data of the upper power tube; the narrow pulse is deleted or the pulse width of the narrow pulse is compensated according to the on-time.

When the difference value between the conduction time and the first difference value is larger than or equal to the minimum pulse width, the rising edge of the narrow pulse is moved forward until the width of the pulse section of the last half period of the narrow pulse is equal to half of the minimum pulse width; and according to the first difference, the falling edge of the conducting pulse positioned at the starting moment of the first half period of the current working clock period in the PWM data of the upper power tube is moved forward. Wherein the first difference is the difference between half of the minimum pulse width and the width of the pulse segment of the narrow pulse in the latter half period. As shown in fig. 6, the width D4 of the PULSE segment is less than half of the minimum narrow PULSE width MIN _ PULSE, i.e. D4< MIN _ PULSE/2, so that the corresponding PULSE (the PULSE of the upper power tube directly opposite to D4 in fig. 6) is a narrow PULSE, the difference t1 between the conduction time of the conduction PULSE at the start time of the first half period of the current working clock period and the first difference in the PWM data of the upper power tube needs to be further determined, t1 shown in fig. 6 is greater than or equal to the minimum narrow PULSE width MIN _ PULSE, so that the width of the PULSE segment of the narrow PULSE can be compensated, the compensation width value is the difference between half of the minimum narrow PULSE width MIN _ PULSE and the width D4 of the PULSE segment of the narrow PULSE, i.e. the compensation width value (MIN _ PULSE/2-D4), and the compensation width value of the conduction PULSE at the start time of the first half period of the current working clock period in the PWM data of the upper power tube is shifted forward by the compensation width MIN _ PULSE (PULSE/2) D4) Compared with a mode of directly deleting the narrow pulse, the method compensates the pulse width of the narrow pulse, can reduce the influence of the narrow pulse on the control performance, reduces the control error caused by the elimination of the narrow pulse, and reduces the output ripple wave. That is, for the narrow PULSE of the PWM data of the upper power transistor at the end time of the latter half period, if the on-time of the on-PULSE of the PWM data of the upper power transistor at the start time of the former half period of the current operating clock cycle is sufficiently long, the on-time of the on-PULSE at the start time of the former half period of the current operating clock cycle is reduced, and the reduced time is added to the latter half period, so that the on-PULSE at the end time of the latter half period is guaranteed to be equal to the half minimum narrow PULSE width MIN _ PULSE/2 without changing the on-time of the entire operating clock cycle.

Further, according to the first difference, the falling edge of the turn-off pulse corresponding to the position of the narrow pulse in the PWM data of the lower power tube is moved forward; and according to the first difference, the rising edge of the turn-off pulse corresponding to the position of the turn-on pulse positioned at the starting moment of the first half period of the current working clock period in the PWM data of the lower power tube and the position of the turn-on pulse positioned at the starting moment of the first half period of the current working clock period in the PWM data of the upper power tube is moved forward. Namely, the corresponding turn-off pulse of the PWM data of the lower power tube follows the compensation, and the dead zone of the upper power tube and the lower power tube is ensured to be normal. Referring again to fig. 6, the falling edge of the off PULSE corresponding to the position of the narrow PULSE in the PWM data of the lower power transistor is advanced by the magnitude of (MIN _ PULSE/2-D4), and the rising edge of the off PULSE corresponding to the position of the on PULSE at the start time of the first half period of the current operation clock cycle in the PWM data of the upper power transistor is advanced by the magnitude of (MIN _ PULSE/2-D4). The values of the upper and lower power tube comparison registers after the adjustment of the front and the back half periods are as follows:

sin_data_calc_up＝sin_data_calc_up-(MIN_PULSE/2-sin_data_calc_up_sec)；

sin_data_calc_down＝sin_data_calc_up-(MIN_PULSE/2-sin_data_calc_up_sec)+IGBT_DT；

sin_data_calc_up_sec＝MIN_PULSE/2；

sin_data_calc_down_sec＝MIN_PULSE/2+IGBT_DT。

and deleting the narrow pulse when the difference between the conduction time and the first difference is smaller than the minimum pulse width conduction. As shown in fig. 7, the PULSE width D5 is less than half of the minimum narrow PULSE width MIN _ PULSE, so the corresponding PULSE (the PULSE of the upper power transistor directly opposite to the position D5 in fig. 7) is a narrow PULSE, and the on-time t2 of the on-PULSE at the beginning of the first half period of the current operating clock cycle in the PWM data of the upper power transistor in fig. 7 is equal to the minimum narrow PULSE width MIN _ PULSE, so the difference between the on-time t2 of the on-PULSE at the beginning of the first half period of the current operating clock cycle in the PWM data of the upper power transistor is less than the first difference, so the narrow PULSE is eliminated by deleting the PULSE segment of the upper power transistor directly opposite to the position D5. In addition, since the width D6 of the off PULSE section corresponding to the position D5 in the PWM data of the lower power transistor is greater than (MIN _ PULSE-IGBT _ DT)/2, the off PULSE section may not be processed. The register values of the upper power tube and the lower power tube in the second half period after adjustment are as follows:

sin_data_calc_up_sec＝0；

sin_data_calc_down_sec＝sin_data_calc_down_sec。

in still other embodiments, the narrow pulse is deleted when the upper power transistor has a narrow pulse in the middle of the current operating clock cycle. As shown in fig. 8, the PULSE width D7 is less than the minimum narrow PULSE width MIN _ PULSE, so the corresponding PULSE (the PULSE of the upper power transistor directly opposite to the position D7 in fig. 8) is a narrow PULSE in the middle of the current operating clock cycle, and thus can be eliminated by deleting the narrow PULSE. The values of the upper and lower power tube comparison registers after the adjustment of the front and the back half periods are as follows:

sin_data_calc_up＝MOD_PERIOD/2；

sin_data_calc_down＝MOD_PERIOD/2；

sin_data_calc_up_sec＝MOD_PERIOD/2；

sin_data_calc_down_sec＝MOD_PERIOD/2。

2. and eliminating the narrow pulse in the PWM data of the lower power tube.

In some embodiments, when the PWM data of the lower power transistor has a narrow pulse at the beginning of the first half period of the current working clock cycle, and the narrow pulse is an off pulse, the rising edge of the off pulse of the narrow pulse is shifted backward until the pulse width of the narrow pulse is equal to the minimum pulse width. As shown in fig. 9, since the PULSE width D8 is smaller than the minimum narrow PULSE width MIN _ PULSE, the corresponding PULSE (the PULSE of the lower power transistor directly facing the position D8 in fig. 9) is a narrow PULSE, and the PULSE width of the narrow PULSE can be compensated, and the magnitude of the compensation width value is the difference between the minimum narrow PULSE width MIN _ PULSE and the PULSE width D8 of the narrow PULSE, that is, the compensation width value (MIN _ PULSE-D8), so as to eliminate the narrow PULSE, the compensation of the PULSE width of the narrow PULSE can reduce the influence of the narrow PULSE on the control performance, reduce the control error caused by the elimination of the narrow PULSE, and reduce the output ripple, compared with the method of directly deleting the narrow PULSE. The comparison register values of the upper power tube and the lower power tube after the adjustment of the first half period are as follows:

sin_data_calc_up＝MIN_PULSE-sin_data_calc_down_current；

sin_data_calc_down＝MIN_PULSE-sin_data_calc_down_current+IGBT_DT。

in other embodiments, when the narrow pulse exists in the PWM data of the lower power tube at the end time of the second half period of the current working clock period, the narrow pulse is an off pulse, and the width of the pulse segment of the narrow pulse in the second half period is less than half of the difference between the minimum pulse width and the dead time, the narrow pulse is deleted. As shown in fig. 10, D9 is less than half of the difference between the minimum narrow PULSE width MIN _ PULSE and the dead time IGBT _ DT, i.e., D9< (MIN _ PULSE-IGBT _ DT)/2, so the corresponding PULSE (the PULSE of the lower power transistor directly opposite to the position of D9 in fig. 10) is a narrow PULSE, and the narrow PULSE needs to be deleted to eliminate the narrow PULSE. The values of the comparison registers of the upper power tube and the lower power tube after the adjustment of the second half period are as follows:

sin_data_calc_up_sec＝0；

sin_data_calc_down_sec＝0。

in still other embodiments, the narrow pulses are deleted when the PWM data of the lower power transistor has a narrow pulse in the middle of the current operating clock cycle. As shown in fig. 11, the PULSE width D10 is less than the minimum narrow PULSE width MIN _ PULSE, so the corresponding PULSE (the PULSE of the upper power transistor directly opposite to the position D7 in fig. 11) is a narrow PULSE in the middle of the current operating clock cycle, and thus can be eliminated by deleting the narrow PULSE. The comparison register value of the lower power tube after the adjustment of the front half period and the back half period is as follows:

sin_data_calc_down＝MOD_PERIOD/2；

sin_data_calc_down_sec＝MOD_PERIOD/2。

in the above embodiments, the narrow pulse is erased, that is, the edge of the narrow pulse is erased.

In addition, in the above embodiment, the method of eliminating the narrow pulse in the PWM data of the upper power transistor and the method of eliminating the narrow pulse in the PWM data of the lower power transistor may be combined, and the method of eliminating the narrow pulse in the PWM data of different upper power transistors and the method of eliminating the narrow pulse in the PWM data of different lower power transistors may also be combined.

The PWM narrow pulse elimination method according to the embodiment of the present application may further include: when the deleted narrow pulse is at the end time of the second half period of the current working clock period, deleting the pulse section of the narrow pulse in the next working clock period of the current working clock period, reducing the influence of the narrow pulse on the control performance, reducing the control error caused by narrow pulse elimination, and reducing the output ripple.

According to the PWM narrow pulse eliminating method, the narrow pulse is deleted or the pulse width of the narrow pulse is compensated by combining the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal, so that the purpose of eliminating the narrow pulse is achieved, the loss of the power tube is reduced, the service life of the power tube is prolonged, and the work of the power tube can be well guaranteed; meanwhile, the influence of eliminating the narrow pulse is compensated, the influence of eliminating the narrow pulse on the control performance is reduced while the utilization rate and the linear adjustment range of the direct-current busbar voltage are ensured, the control error caused by eliminating the narrow pulse is reduced, and the output ripple is reduced. After PWM generation optimization, the control is closer to the switching point which needs to be controlled actually, and the inventor can measure that the harmonic wave of the product is reduced in an actual operation test.

The PWM narrow pulse elimination method can be realized by an FPGA (Field Programmable Gate Array), the protection of a power device is very quick, once a fault occurs, the fault protection can be realized in a nanosecond level, and the speed is higher than that of an original DSP (Digital Signal Processing) scheme.

Referring to fig. 12, an embodiment of the present application further provides a single-phase PWM narrow pulse cancellation apparatus, which includes one or more processors, and is configured to implement the PWM narrow pulse cancellation method in the foregoing embodiment.

The embodiment of the single-phase PWM narrow pulse eliminating device can be applied to a wind generating set converter. The device embodiments may be implemented by software, or by hardware, or by a combination of hardware and software. The device is formed by reading corresponding computer program instructions in the nonvolatile memory into the memory for operation through a processor of the wind generating set converter where the device is located. From a hardware aspect, as shown in fig. 12, the present application is a hardware structure diagram of a wind turbine generator converter in which the single-phase PWM narrow pulse cancellation apparatus is located, except for the processor, the internal bus, the memory, the network interface, and the nonvolatile memory shown in fig. 12, the wind turbine generator converter in which the apparatus is located in the embodiment may also include other hardware according to an actual function of the wind turbine generator converter, which is not described again.

The embodiment of the present application further provides a computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, the method for eliminating the PWM narrow pulse in the foregoing embodiment is implemented.

The computer readable storage medium may be an internal storage unit, such as a hard disk or a memory, of the wind turbine converter according to any of the embodiments described above. The computer readable storage medium may also be an external storage device of the wind turbine, such as a plug-in hard disk, a Smart Media Card (SMC), an SD Card, a Flash memory Card (Flash Card), and the like, provided on the device. Further, the computer readable storage medium may also comprise both an internal storage unit of the wind park converter and an external storage device. The computer-readable storage medium is used for storing the computer program and other programs and data required by the wind park converter and may also be used for temporarily storing data that has been or will be output.

The embodiment of the application also provides a three-phase PWM narrow pulse eliminating device, which is applied to a converter of a wind generating set, wherein the converter comprises an A-phase upper power tube, an A-phase lower power tube, a B-phase upper power tube, a B-phase lower power tube, a C-phase upper power tube and a C-phase lower power tube, the three-phase PWM narrow pulse eliminating device comprises the A-phase PWM narrow pulse eliminating device, the B-phase PWM narrow pulse eliminating device and the C-phase PWM narrow pulse eliminating device, and the A-phase PWM narrow pulse eliminating device, the B-phase PWM narrow pulse eliminating device and the C-phase PWM narrow pulse eliminating device all comprise the single-phase PWM narrow pulse eliminating device in the embodiment.

Namely, the A-phase PWM narrow pulse eliminating device, the B-phase PWM narrow pulse eliminating device and the C-phase PWM narrow pulse eliminating device eliminate the PWM narrow pulses in the same way.

It should be noted that the a-phase PWM narrow pulse cancellation device, the B-phase PWM narrow pulse cancellation device, and the C-phase PWM narrow pulse cancellation device are three independent modules.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A PWM narrow pulse elimination method is used for controlling an upper power tube and a lower power tube, and is characterized by comprising the following steps:

acquiring carrier data;

processing the carrier data based on a triangular wave periodic signal and the dead time of the upper power tube and the lower power tube to obtain PWM data of the upper power tube and the lower power tube;

respectively determining whether narrow pulses with pulse widths smaller than the minimum pulse width exist in the PWM data of the upper power tube and/or the lower power tube according to the PWM data of the upper power tube and the lower power tube;

and if the narrow pulse exists, deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal.

2. The PWM narrow pulse cancellation method according to claim 1, wherein the deleting or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal comprises:

and when the narrow pulse is at the starting time of the first half period of the current working clock period, compensating the pulse width of the narrow pulse, wherein the real-time counting value of the triangular wave periodic signal is increased progressively in the first half period.

3. The PWM narrow pulse cancellation method according to claim 2, wherein said compensating for the pulse width of said narrow pulse comprises:

when the narrow pulse exists in the PWM data of the upper power tube and is a conducting pulse, moving the falling edge of the narrow pulse backwards until the pulse width of the narrow pulse is equal to the minimum pulse width; and

and the rising edge of the turn-off pulse corresponding to the narrow pulse on the PWM data of the lower power tube is followed by backward movement.

4. The PWM narrow pulse cancellation method according to claim 2, wherein said compensating for the pulse width of said narrow pulse comprises:

when the narrow pulse exists in the PWM data of the lower power tube and is an off pulse, the rising edge of the off pulse of the narrow pulse is moved backwards until the pulse width of the narrow pulse is equal to the minimum pulse width.

5. The PWM narrow pulse cancellation method according to claim 1, wherein the deleting or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal comprises:

and when the narrow pulse is at the end time of the second half period of the current working clock period, deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the power tube to which the narrow pulse belongs, wherein the real-time count value of the triangular wave periodic signal is decreased progressively in the second half period.

6. The PWM narrow pulse elimination method according to claim 5, wherein the deleting or compensating the pulse width of the narrow pulse according to the power tube to which the narrow pulse belongs comprises:

when the narrow pulse exists in the PWM data of the upper power tube and is a conduction pulse, determining the conduction time of the conduction pulse which is positioned at the starting moment of the first half period of the current working clock period in the PWM data of the upper power tube;

and deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the on-time.

7. The PWM narrow pulse elimination method according to claim 6, wherein the deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the on-time comprises:

when the difference between the on-time and a first difference is larger than or equal to the minimum pulse width, advancing the rising edge of the narrow pulse until the width of the pulse segment of the narrow pulse in the second half period is equal to half of the minimum pulse width, wherein the first difference is the difference between half of the minimum pulse width and the width of the pulse segment of the narrow pulse in the second half period; and

and according to the first difference, advancing the falling edge of the conducting pulse positioned at the starting moment of the first half period of the current working clock period in the PWM data of the upper power tube.

8. The PWM narrow pulse cancellation method according to claim 7, further comprising:

according to the first difference value, the falling edge of a turn-off pulse corresponding to the position of the narrow pulse in the PWM data of the lower power tube is moved forward; and

and according to the first difference, the rising edge of the turn-off pulse corresponding to the position of the turn-on pulse at the starting moment of the first half period of the current working clock cycle in the PWM data of the lower power tube and the position of the turn-on pulse in the PWM data of the upper power tube is moved forward.

9. The PWM narrow pulse elimination method according to claim 6, wherein the deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the on-time comprises:

and deleting the narrow pulse when the difference between the conduction time and a first difference is smaller than the minimum pulse width, wherein the first difference is the difference between half of the minimum pulse width and the width of a pulse section of the narrow pulse in the second half period.

10. The PWM narrow pulse elimination method according to claim 5, wherein the deleting or compensating the pulse width of the narrow pulse according to the power tube to which the narrow pulse belongs comprises:

and deleting the narrow pulse when the narrow pulse exists in the PWM data of the lower power tube, the narrow pulse is an off pulse, and the width of the pulse section of the narrow pulse in the second half period is less than half of the difference value between the minimum pulse width and the dead time.

11. The PWM narrow pulse cancellation method according to claim 1, wherein the deleting or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal comprises:

and deleting the narrow pulse when the narrow pulse is in the middle of the current working clock period, wherein the real-time count value of the triangular wave periodic signal is increased progressively in the first half period of the current working clock period and decreased progressively in the second half period of the current working clock period.

12. The PWM narrow pulse cancellation method according to claim 1, further comprising:

and when the deleted narrow pulse is at the end time of the second half period of the current working clock period, deleting the pulse segment of the narrow pulse in the next working clock period of the current working clock period.

13. A single-phase PWM narrow pulse cancellation apparatus, comprising one or more processors configured to implement the PWM narrow pulse cancellation method according to any one of claims 1 to 12.

14. A three-phase PWM narrow pulse eliminating device is applied to a current transformer of a wind generating set, the current transformer comprises an A-phase upper power tube and an A-phase lower power tube, a B-phase upper power tube and a B-phase lower power tube, and a C-phase upper power tube and a C-phase lower power tube, and the three-phase PWM narrow pulse eliminating device comprises the A-phase PWM narrow pulse eliminating device, the B-phase PWM narrow pulse eliminating device and the C-phase PWM narrow pulse eliminating device, wherein the A-phase PWM narrow pulse eliminating device, the B-phase PWM narrow pulse eliminating device and the C-phase PWM narrow pulse eliminating device comprise the single-phase PWM narrow pulse eliminating device according to claim 13.