CN113655266B

CN113655266B - Single bus current detection method and device, motor controller and storage medium

Info

Publication number: CN113655266B
Application number: CN202111130264.5A
Authority: CN
Inventors: 陈俊桦; 洪伟鸿; 王豪浩; 周超; 钟明胜
Original assignee: GD Midea Heating and Ventilating Equipment Co Ltd; Hefei Midea Heating and Ventilating Equipment Co Ltd
Current assignee: GD Midea Heating and Ventilating Equipment Co Ltd; Hefei Midea Heating and Ventilating Equipment Co Ltd
Priority date: 2021-09-26
Filing date: 2021-09-26
Publication date: 2024-01-26
Anticipated expiration: 2041-09-26
Also published as: CN113655266A

Abstract

The utility model is suitable for the motor technical field, a single busbar current detection method, a device, a motor controller and a storage medium are provided, in half carrier period, based on the abc comparison value, according to the current direction of uvw phase current at the moment of uvw comparison value, the minimum sampling moment and the minimum effective vector duration of busbar current are determined, the busbar current is sampled at the minimum sampling moment and the minimum effective vector duration is sustained, when single busbar current detection is carried out, the influence of current direction and dead zone effect on busbar current change is considered, and then the minimum sampling moment and the minimum effective vector duration of busbar current are calculated in an optimized mode, the minimum effective vector duration can be optimized dynamically on the basis of ensuring busbar current sampling accuracy, and current harmonics are reduced.

Description

Single bus current detection method and device, motor controller and storage medium

Technical Field

The application belongs to the technical field of motors, and particularly relates to a single bus current detection method, a single bus current detection device, a motor controller and a storage medium.

Background

The single bus current detection technique is a technique that reduces the cost of the current sensor. The single bus current detection is only carried out by detecting the bus current on a direct current bus in a motor controller, and determining the correlation between the bus current and the phase current of the motor according to the switching state of a switching tube of a three-phase bridge arm of an inverter, so as to estimate the phase current of the motor. The single bus current detection method only needs one current sensor, and the cost is greatly reduced, so that the method is widely applied to cost sensitive industries such as compressors of air conditioners, fans, motors of washing machines and the like.

The single bus current detection method has an inherent disadvantage in that the current on the bus can be correlated with the phase current of the motor only when the voltage vector applied to the motor is an effective voltage vector. In the reconstruction process of the motor phase current, the bus current needs to be continuously collected twice to be converted into two-phase current and the third phase current is calculated. In the space vector pulse width modulation (Space Vector Pulse Width Modulation, SVPWM) method, bus current detection may be sampled over the duration of two effective voltage vectors of SVPWM to further infer the phase current magnitude within the current carrier period.

The switching between the different voltage vectors determines the variation of the switching action of the switching tube. The bus current will oscillate for a period of time during the voltage vector switching phase due to the spurious parameters of the hardware circuit. If the bus current detection occurs during oscillation, the accuracy of the bus current detection will be affected. In order to improve the accuracy of bus current detection, a period of time needs to be delayed after the switching action occurs, and the bus current sampling action is performed after the current oscillation disappears. The delay operation required for bus current sampling places demands on the duration of the effective vector. The duration of the effective voltage vector may be less than the delay time required for bus current sampling during motor operation, which is typically defined as a sampling dead zone.

In the prior art, the effective voltage vector is not lower than the minimum effective vector duration by adjusting the duty ratio or the comparison value of the PWM signals used for driving the switching tubes of the three-phase bridge arm. The comparison value adjustment introduced to meet the sampling requirement will introduce additional voltage harmonics, thereby causing additional current harmonics.

In addition to the current oscillation time, dead zone effects of the inverter are also one of the important factors affecting the minimum effective vector duration. The setting of the minimum effective vector duration typically requires consideration of dead zone effects, in that the minimum effective vector duration requires superposition of dead times. However, in the prior art, only the influence of the waveform of the PWM signal on the dead zone effect is considered, other factors are ignored, and the accuracy of single bus current detection is affected.

Disclosure of Invention

The embodiment of the application provides a single bus current detection method, a single bus current detection device, a motor controller and a storage medium, and aims to solve the problems that in the prior art, only the influence of the waveform of a PWM signal on a dead zone effect is considered, other factors are ignored, and the accuracy of single bus current detection is influenced.

A first aspect of an embodiment of the present application provides a method for detecting a single bus current, including:

in a half-carrier period, determining the minimum sampling time and the minimum effective vector duration of the bus current according to the flow direction of the uvw phase current at the moment of the uvw comparison value, wherein the uvw comparison value is obtained by the abc comparison value according to the descending order of the values;

the bus current is sampled at the minimum sampling instant and for the minimum effective vector duration.

A second aspect of the embodiments of the present application provides a single bus current detection device, including:

the time determining unit is used for determining the minimum sampling time and the minimum effective vector duration of the bus current according to the flow direction of the uvw phase current at the moment of the uvw comparison value in the half-carrier period, and the uvw comparison value is obtained by the abc comparison value in descending order of the values;

and the current sampling unit is used for sampling the bus current at the minimum sampling time and lasting the minimum effective vector duration.

A third aspect of the embodiments of the present application provides a motor controller, including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the single bus current detection method of the first aspect of the embodiments of the present application when the computer program is executed by the processor.

A fourth aspect of the embodiments of the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the single busbar current detection method as described in the first aspect of the embodiments of the present application.

According to the single bus current detection method provided by the first aspect of the embodiment of the application, in a half-carrier period, a uvw comparison value is obtained after the abc comparison value is reduced according to a numerical value, the minimum sampling time and the minimum effective vector duration of bus current are determined according to the flow direction of uvw phase current at the moment of the uvw comparison value, the bus current is sampled at the minimum sampling time and the minimum effective vector duration is sustained, and when single bus current detection is carried out, the influence of the flow direction and dead zone effect of current on the bus current change is considered, and then the minimum sampling time and the minimum effective vector duration of the bus current are calculated in an optimized mode, so that the minimum effective vector duration can be dynamically optimized on the basis of ensuring the sampling accuracy of the bus current, and current harmonics are reduced.

It will be appreciated that the advantages of the second to fourth aspects may be found in the relevant description of the first aspect and are not repeated here.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a motor controller according to an embodiment of the present application;

FIG. 2 is a calculation formula table of three-phase comparison values of target voltage vectors in six sectors of a space vector plane according to the embodiment of the present application;

fig. 3 is a schematic diagram of a triangular carrier, PWM waveform of PWM signal and bus current in a half carrier period provided in an embodiment of the present application;

fig. 4 is a phase sequence mapping method applied to a single bus current detection method according to an embodiment of the present application;

FIG. 5 is a schematic diagram of triangular carrier, waveform of PWM signal and bus current in half carrier period after redefining abc phase sequence provided in the embodiments of the present application;

FIG. 6 is a schematic diagram of a variation of bus current provided by an embodiment of the present application;

fig. 7 is a schematic diagram of a first dead zone generation mode of a carrier falling edge period according to an embodiment of the present application;

fig. 8 is a schematic diagram of a second dead zone generation mode of a carrier falling edge period according to an embodiment of the present application;

fig. 9 is a schematic diagram of a change situation of a bus current in a first dead zone generating manner provided in an embodiment of the present application;

fig. 10 is a schematic diagram of a first flow of a single bus current detection method according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram of a second flow of a single bus current detection method according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a single bus current detection device according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a motor controller according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The embodiment of the application provides a single bus current detection method which can be executed by a processor of a motor controller when a corresponding computer program is run, and is used for considering the influence of current flow direction and dead zone effect on bus current change when single bus current detection is carried out, so that the minimum sampling time and the minimum effective vector duration of bus current are optimized and calculated, the minimum effective vector duration can be dynamically optimized on the basis of ensuring the accuracy of bus current sampling, and current harmonics are reduced.

In application, the motor controller can be an air conditioner, a fan and a washing machine, and is used for driving and controlling the motors of the air conditioner, the fan and the washing machine, and the motor controller can be a frequency converter.

As shown in fig. 1, a schematic diagram of a motor controller is exemplarily shown;

the motor controller comprises a processor, a current sensor and an inverter;

the current sensor is electrically connected with the negative electrode of the direct current bus and is used for detecting bus current on the direct current bus, and the current sensor is exemplarily shown in fig. 1 to be realized through a sampling resistor connected in series with the negative electrode of the direct current bus;

the first input end of the inverter is electrically connected with the positive electrode of the direct current bus, the second input end of the inverter is electrically connected with the negative electrode of the direct current bus, six controlled ends of the inverter are electrically connected with the processor, three output ends of the inverter are respectively electrically connected with three phase current and phase voltage input ends of the motor, the inverter shown in an exemplary mode in fig. 1 comprises three-phase bridge arms (a-phase bridge arm, b-phase bridge arm and c-phase bridge arm), each phase bridge arm comprises two switching tubes (an upper switching tube and a lower switching tube), the input ends of the upper switching tubes of the three-phase bridge arms are commonly connected to form the first input end of the inverter, the output ends of the lower switching tubes of the three-phase bridge arms are commonly connected to form the second input end of the inverter 3, the controlled ends of each switching tube form one controlled end of the inverter, and the output ends of the upper switching tube and the input ends of the lower switching tube of each phase bridge arm are commonly connected to form one output end of the inverter;

The processor is used for:

acquiring target phase voltages (a-phase voltage, b-phase voltage and c-phase voltage) required to be applied to the stator according to target rotor speed required to be achieved by the motor so as to generate corresponding target phase currents (a-phase current ia, b-phase current ib and c-phase current ic) in the stator;

and a SVPWM method is adopted, a target voltage vector is determined according to the rotor angle and the target phase voltage, a three-phase comparison value is obtained through a comparison value calculation method based on the SVPWM method according to the target voltage vector amplitude and the phase angle, then a triangular carrier wave is adopted to compare with the calculated three-phase comparison value, a generated pulse width modulation (Pulse Width Modulation, PWM) signal for driving a switching tube of a corresponding phase is generated, and the on-off states of six switching tubes of a three-phase bridge arm of an inverter are controlled, so that the three-phase voltage is output to a motor.

The on-off states of six switching tubes of a three-phase bridge arm of the inverter are controlled according to the PWM signals, so that the actual voltage of the bus voltage acting on the stator is equivalent to the target phase voltage, correspondingly, the actual current of the bus current acting on the stator is equivalent to the target phase current, and further, the stator generates a corresponding magnetic field to drive the rotor to rotate at the target rotor speed;

In order to improve motor control accuracy, the bus current on the direct current bus needs to be acquired through a current sensor, the magnitude of the bus current on the direct current bus is obtained, the magnitude of actual phase current applied to a stator can be estimated according to the magnitude of the bus current, the target phase current can be adjusted according to deviation between the actual phase current and the target phase current by comparing the actual phase current with the target phase current, the adjusted target phase voltage can be obtained based on the adjusted target phase current, an adjusted target voltage vector can be determined by combining a space vector pulse width modulation method, an adjusted pulse width modulation signal is generated according to the adjusted target voltage vector, the on-off states of six switching tubes of a three-phase bridge arm of an inverter are controlled according to the adjusted pulse width modulation signal, and finally feedback control of the motor is achieved.

In application, the switch tube has the function of conducting or stopping under the triggering of an electric signal (PWM signal) and is used for playing the role of an electronic switch, and can be specifically an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), a triode (Bipolar Junction Transistor, BJT), a field effect transistor (Field Effect Transistor, FET), a Thyristor (Thyristor) and the like, wherein the insulated gate bipolar transistor is a composite fully-controlled voltage-driven power semiconductor device consisting of a bipolar transistor and an insulated gate field effect transistor, and has the advantages of high input impedance of the insulated gate field effect transistor and low conduction voltage drop of the bipolar transistor, and the field effect transistor can be specifically a Metal-oxide semiconductor field effect transistor (Metal-Oxide Semiconductor FET, MOS-FET for short).

In application, a comparison value calculating method based on the SVPWM method is described in detail below:

if the amplitude of the target voltage vector is Ur and the phase angle is θ1, the method for calculating the modulation factor m1 is as follows:

wherein Udc is the bus voltage;

if θ 1>0 and θ1 is less than or equal to 1/3 pi, the target voltage vector is located in the first sector of the space vector plane, and the angle θm=θ1 relative to the first sector;

if θ 1>1/3 is pi and θ1 is less than or equal to 2/3 pi, the target voltage vector is located in the second sector of the space vector plane, and the angle θm=θ1-1/3 pi is relative to the second sector;

if θ 1>2/3 is pi and θ1 is less than or equal to 3/3 pi, the target voltage vector is located in a third sector of the space vector plane, and the angle θm=θ1-2/3 pi is relative to the third sector;

if θ 1>3/3 is pi and θ1 is less than or equal to 4/3 pi, the target voltage vector is located in the fourth sector of the space vector plane, and the angle θm=θ1-3/3 pi is relative to the fourth sector;

if θ 1>4/3 is pi and θ1 is less than or equal to 5/3 pi, the target voltage vector is located in the fifth sector of the space vector plane, and the angle θm=θ1-4/3 pi is relative to the fifth sector;

if θ 1>5/3 is pi and θ1 is less than or equal to 2 pi, the target voltage vector is located in the sixth sector of the space vector plane, and the angle θm=θ1-5/3 pi is relative to the sixth sector;

The duration duty ratios Tm1 and Tm2 of the two effective vectors in the carrier period are calculated based on m1 and θm:

wherein Tm is the maximum value of the carrier counter, i.e., the maximum carrier cycle count value;

the duration ratio Tm0 of the zero vector is calculated by:

Tm0＝0.5*(1-Tm1-Tm2)*Tm

as shown in fig. 2, a calculation formula table showing three-phase comparison values of the target voltage vector in six sectors of the space vector plane is exemplarily shown; the comparison value of the phase a at the carrier falling edge is DDA0, and the comparison value of the phase a at the carrier rising edge is DUA0; the comparison value of the b phase at the carrier falling edge is DDB0, and the comparison value of the carrier rising edge is DUB0; the comparison value of the c phase at the carrier falling edge is DDC0, and the comparison value of the c phase at the carrier rising edge is DUC0. In the symmetrical sampling mode, the comparison value of the carrier falling edge is the same as the comparison value of the carrier rising edge, that is, dda0=dua0, ddb0=dub0, ddc0=duc0.

In application, in a single bus current sampling mode based on SVPWM, in a half-carrier period, the voltage output by the inverter is divided into four sections, and when the half-carrier period is a carrier falling edge period, the four sections of voltages output by the inverter are respectively: first zero vector→first effective vector→second zero vector; when the half carrier period is the carrier rising edge period, the four sections of voltages output by the inverter are respectively: second zero vector→second effective vector→first zero vector.

As shown in fig. 3, a schematic diagram illustrating a triangular carrier in a half carrier period, PWM waveforms of PWM signals, and bus current is exemplarily shown; wherein Ta, tb, and Tc are abc comparison values (i.e., a comparison value Ta, b comparison value Tb, and c comparison value Tc are included), tsh is a half-carrier period, a-phase, b-phase, and c-phase waveforms are waveforms of PWM signals output to three-phase bridge arms of the inverter, idc is a bus current, T1 is a duration of the first effective vector, T2 is a duration of the second effective vector, and Tad1 and Tad2 are two bus current sampling timings, respectively.

In application, the single-bus current sampling technique is used to estimate the corresponding motor phase currents by sampling bus currents for the duration of two adjacent active vectors (i.e., the first active vector and the second active vector) respectively. The relationship between bus current sampling and phase current and space voltage vectors is:

if the output voltage at the bus current sampling moment is the space voltage vector 100, the bus current idc is equal to the a-phase current ia;

if the output voltage at the bus current sampling time is the space voltage vector 110, the bus current idc is equal to the negative c-phase current-ic;

if the output voltage at the bus current sampling moment is the space voltage vector 101, the bus current idc is equal to the negative b-phase current-ib;

If the output voltage at the bus current sampling moment is a space voltage vector 010, the bus current idc is equal to the b-phase current ib;

if the output voltage at the bus current sampling moment is the space voltage vector 011, the bus current idc is equal to the negative a-phase current-ia;

if the output voltage at the bus current sampling time is the space voltage vector 001, the bus current idc is equal to the c-phase current ic.

As shown in fig. 4, an embodiment of the present application provides a phase sequence mapping method applied to a Shan Muxian current detection method, including the following steps S401 to S406:

in step S401, in the half-carrier period, according to the amplitude and the phase angle of the target voltage vector, an abc comparison value is obtained.

In an application, the abc comparison values include an a comparison value, a b comparison value, and a c comparison value, which may be obtained through a comparison value calculation method based on the SVPWM method according to the magnitude and phase angle of the target voltage vector.

And step S402, sorting abc comparison values according to a numerical descending order to obtain uvw comparison values.

In application, the uvw comparison values include u comparison value, v comparison value and w comparison value, where the u comparison value, v comparison value and w comparison value are obtained by sorting and renaming the a comparison value, b comparison value and c comparison value in descending order of values (i.e. in descending order of values), for example, if the a comparison value, b comparison value and c comparison value are in descending order of values: a comparison value > b comparison value > c comparison value, then the a comparison value after renaming is u comparison value, b comparison value is v comparison value, c comparison value is w comparison value; if the numerical descending order of the a, b and c comparison values is: c comparison value > b comparison value > a comparison value, then a comparison value after renaming is w comparison value, b comparison value is v comparison value, c comparison value is u comparison value.

Step S403, using the duration between the starting time of the half-carrier period and the u comparison value time as the duration of the first zero vector of the half-carrier period;

step S404, the duration between the u comparison value time and the v comparison value time of the half carrier period is used as the duration of the first effective vector of the half carrier period;

step S405, the duration between the v comparison value time and the w comparison value time of the half-carrier period is used as the duration of the second effective vector of the half-carrier period;

step S406, comparing the duration between the value time and the end time of the w comparison value time of the half-carrier period as the duration of the second zero vector of the half-carrier period.

In application, based on uvw comparison values obtained after numerical descending sorting and renaming of abc comparison values, redefining a first zero vector, a first effective vector, a second effective vector and a second zero vector in a half carrier period is specifically defined as follows:

the first zero vector is the output voltage from the starting time of the half-carrier period to the time before the u comparison value time, and the duration of the first zero vector is the duration between the starting time of the half-carrier period and the u comparison value time;

The first effective vector is the output voltage from the u comparison value time to the v comparison value time, and the duration of the first effective vector is the duration between the u comparison value time and the v comparison value time;

the second effective vector is the output voltage from the v comparison value time to the w comparison value time, and the duration of the second effective vector is the duration between the v comparison value time and the w comparison value time;

the second zero vector is the output voltage during the w-comparison value time and the end time of the half-carrier period, and the duration of the second zero vector is the duration between the w-comparison value time and the end time of the half-carrier period.

As shown in fig. 5, a schematic waveform diagram of the triangular carrier, PWM signal and bus current in the half carrier period after redefining the abc phase sequence is exemplarily shown; where Tu, tv, and Tw are uvw comparison values (i.e., include u comparison values Tu, v comparison values Tv, and w comparison values Tw), tsh is a half-carrier period, u-phase, v-phase, and w-phase waveforms are waveforms of PWM signals output to three-phase bridge arms of the inverter, idc is a bus current, T1 is a duration of the first effective vector, and T2 is a duration of the second effective vector, respectively.

It should be understood that the triangular carrier wave is adopted in the diagrams of fig. 3 and 5, and only the waveforms of the triangular carrier wave, the PWM signal and the bus current in the carrier wave falling edge period are illustrated, the waveforms in the carrier wave rising edge period may be symmetrical to the waveforms in the carrier wave falling edge period, and may be simply deduced, which is not repeated here. Fig. 3 and 5 show the PWM waveform in an ideal state, ignoring dead zone effects, and the bus current idc is the current flowing through the sampling resistor.

As shown in fig. 6, a schematic diagram illustrating a change in bus current is shown. After the carrier comparison action at the Tu comparison value moment is generated, the delay switching tube after a period of time generates switching action, the delay time of the switching tube after the Tu comparison value moment generates switching action is defined as switching-on delay Ton, and the delay time of the switching action is defined as switching-off delay Toff, and the switching-on delay Ton/off is collectively called. When the switching operation of the switching tube occurs, the bus current changes, and an oscillation waveform is generated on the bus current due to the influence of circuit spurious parameters and the like, and the duration of the oscillation waveform is defined as an oscillation time Tst. When oscillation is completed, the bus current can be accurately sampled, and the time required for the bus current sampling process is defined as sampling process time Th. The bus current sampling moments are defined as sampling moments Tad1 and Tad2 respectively. Therefore, a minimum sampling time calculation method is as follows:

Tad1＝Tu+Ton/off+Tst，Tad2＝Tv+Ton/off+Tst。

In an application, the duration T1 of the first effective vector and the duration T2 of the second effective vector both need to be greater than the minimum effective vector duration Tmin in order to accurately sample the bus current. The minimum effective vector duration Tmin needs to include a switching delay Ton/off, an oscillation time Tst, and a sampling process time Th. If the duration T1 of the first significant vector and the duration T2 of the second significant vector are smaller than the minimum significant vector duration Tmin, then both can be made to meet the requirement of being greater than the minimum significant vector duration Tmin by adjusting the uvw comparison values, i.e., adjusting Tu, tv and Tw to increase the duration T1 of the first significant vector and the duration T2 of the second significant vector.

In application, in order to prevent the bridge arm of the inverter from being directly connected (i.e. two switching tubes connected in series and included in a single-phase bridge arm are simultaneously conducted), the on/off of the upper and lower switching tubes of the single-phase bridge arm needs to be staggered by dead time. Two dead zone generation modes are described below:

as shown in fig. 7, a first dead zone generation mode of the carrier falling edge period is exemplarily shown; the switching-on action of the upper switching tube and the lower switching tube of a certain phase bridge arm is generated at the moment of the comparison value of the corresponding phase, and the switching-off action of the lower switching tube is generated in advance of dead time Tdd before the moment of the comparison value of the corresponding phase;

As shown in fig. 8, a second dead zone generation mode of the carrier falling edge period is exemplarily shown; the switching operation of the lower switching tube is generated at the time of the comparison value of the corresponding phase, and the switching operation of the upper switching tube is generated after the time of the comparison value of the corresponding phase by the delay dead time Tdd.

In application, the u-phase switching action is illustrated in fig. 7 as an example. Defining the flow direction of current: the current flowing from the inverter into the motor is positive, and the current flowing from the motor into the inverter is negative. If the u-phase current flows forward in the carrier falling edge period, the current path of the inverter flows into the motor through the u-phase lower switching tube of the inverter before the u-phase lower switching tube is turned off, and no current passes through the sampling resistor. The process from the turn-off action of the u-phase lower switching tube to the turn-on action of the u-phase upper switching tube is dead time, and no current passes through the sampling resistor because of the follow current function of the follow current diode of the u-phase lower switching tube in the dead time. After the u-phase upper switching tube is turned on, the u-phase current is gradually converted from the follow current of the follow current diode of the u-phase lower switching tube to the conduction current of the u-phase upper switching tube, and the bus current appears at the moment;

If the u-phase current flows in the negative direction in the carrier falling edge period, the current path of the inverter flows into the u-phase lower switching tube of the inverter through the motor before the u-phase lower switching tube is turned off, and no current passes through the sampling resistor. The process from the turn-off action of the u-phase lower switching tube to the turn-on action of the a-phase upper switching tube is dead time, and current is fed into the direct current bus through the freewheeling diode of the u-phase upper switching tube in the dead time, and at the moment, the bus current appears and continues until the u-phase upper switching tube is turned on.

In application, when the half carrier period is the carrier rising edge period, the uvw-phase switching action sequence and the carrier falling edge period are in symmetrical relation, namely, the w-phase switching action is firstly performed, the v-phase switching action is then performed, and the u-phase switching action is finally performed. Therefore, the first bus current change time is affected by the w-phase switching operation time, the second bus current change time is affected by the v-phase switching operation time, and the third bus current change time is affected by the u-phase switching operation.

It should be understood that, fig. 7 and fig. 8 only illustrate waveforms of the dead zone generation mode in the carrier falling edge period, and the waveforms of the dead zone generation mode in the carrier rising edge period are symmetrical to those of the dead zone generation mode in the carrier falling edge period, which can be simply deduced, and are not repeated here;

In a first dead zone generation mode of a carrier rising edge period, for an upper switching tube and a lower switching tube of a certain phase bridge arm, the off action of the upper switching tube is generated at the moment of a corresponding phase comparison value, and the on action of the lower switching tube is generated after the moment of the corresponding phase comparison value and delayed dead zone time Tdd;

in the second dead zone generation mode of the carrier rising edge period, for the upper and lower switching tubes of a certain phase bridge arm, the on operation of the upper switching tube is generated at the comparison value time of the corresponding phase, and the off operation of the lower switching tube is generated in advance of the comparison value time of the corresponding phase by dead zone time Tdd.

In application, the u-phase switching operation is described as an example. Defining the flow direction of current: the current flowing from the inverter into the motor is positive, and the current flowing from the motor into the inverter is negative. If the flow direction of the u-phase current in the carrier falling edge period is positive, after the u-phase upper switching tube is turned off, the current path of the inverter is that the current is freewheeling through the freewheeling diode of the u-phase lower switching tube, and the current on the sampling resistor is changed at the moment;

if the flow direction of the u-phase current in the carrier rising edge period is negative, after the u-phase upper switching tube is turned off, the current path of the inverter is that the current flows through the freewheeling diode of the u-phase upper switching tube, the current on the sampling resistor is unchanged at the moment, and after the u-phase lower switching tube is turned on, the u-phase current flows into the bus through the u-phase lower switching tube, and the current on the sampling resistor is changed at the moment.

It should be understood that the v-phase and w-phase switching operations have the same effect on the bus current as the u-phase, and will not be described here.

In application, the change time of the bus current caused by the switching action of the switching tube of the bridge arm is related to the current flow direction of the dead zone action time, and the sampling time of the bus current are further affected. In the prior art, dead time is only overlapped by waveform of vector voltage, but the influence of current flow direction is not considered, so that the accuracy of bus current sampling is reduced, or the minimum effective vector duration is set to be too large to cause larger current harmonic waves.

As shown in fig. 9, a schematic diagram illustrating a change situation of the bus current in the first dead zone generation mode is shown; in this example, when the u-phase current iu flows in the negative direction, the v-phase current iv flows in the positive direction, and the v-phase current iw flows in the negative direction, the bus current idc changes, tdd is the dead time, and Tu, tv, and Tw are the uvw values.

In the application, the Tu comparison value is generated at the moment, the bus current changes caused by the carrier comparison action, and the dead time Tdd is generated in advance; bus current change caused by carrier comparison action generated at the moment of Tv comparison value is synchronous with the moment of Tv comparison value; bus current change due to carrier comparison operation occurring at the time of Tw comparison value occurs in advance of dead time Tdd. Taking fig. 7 as an example, the duration T1 of the first significant vector is enlarged by Tdd with respect to its initial value Tv-Tu, i.e. t1=tv-tu+tdd, so that the corresponding minimum significant vector duration Tmin within the duration T1 of the first significant vector can be reduced; the duration T2 of the second effective vector is reduced by Tdd with respect to its initial value Tv-Tu, i.e. t2=tv-Tu-Tdd, so that the corresponding minimum effective vector duration Tmin within the duration T2 of the second effective vector needs to be increased; at the same time, the minimum sampling time also needs to be synchronously adjusted by referring to the minimum effective vector duration Tmin.

As shown in fig. 10, based on the redefined uvw phase sequence, the single bus current detection method provided in the embodiment of the present application further includes the following steps S1001 and S1002:

in step S1001, in the half-carrier period, the minimum sampling time and the minimum effective vector duration of the bus current are determined according to the flow direction of the uvw phase current at the uvw comparison value time.

In the application, in a carrier falling edge period or a carrier rising edge period, determining a bus current change time and a minimum sampling delay according to the flow direction of u-phase current iu at a u comparison value Tu time, the flow direction of v-phase current iv at a v comparison value Tv time and the flow direction of w-phase current iw at a w comparison value Tw time, and then determining the minimum sampling time based on the bus current change time and the minimum sampling delay; and finally, determining the minimum effective vector duration according to the minimum sampling delay.

In one embodiment, step S1001 is preceded by:

if the x-phase current at the moment of comparing x flows into the motor from the inverter, determining that the flow direction of the x-phase current is positive;

if the x-phase current at the moment of comparing the x-phase current flows into the inverter from the motor, determining that the flow direction of the x-phase current is negative;

where x=u, v, w.

Step S1002, sampling the bus current at the minimum sampling time and for the minimum effective vector duration.

In application, after determining the minimum sampling time and the minimum effective vector duration, the processor can control the current sensor (i.e. through the sampling resistor) to sample the bus current at the minimum sampling time, so that current reconstruction can be performed according to the bus current obtained by two times of sampling, and the actual phase current output to the motor is obtained.

As shown in fig. 11, in one embodiment, step S1101 includes steps S1101 to S1103 as follows:

step 1101, determining a bus current change time and a minimum sampling delay according to the flow direction of the uvw phase current at the uvw comparison value time;

step 1102, determining the minimum sampling time according to the bus current change time and the minimum sampling delay;

step S1103, determining the minimum effective vector duration according to the minimum sampling delay.

In one embodiment, based on the same principle as the first dead zone generation method shown in fig. 7, when the half carrier period is the carrier falling edge period, if the uvw phase current at uvw comparison value time flows in positive, negative and negative directions (i.e. iu > 0, iv < 0 and iw < 0), respectively, it is determined that the first bus current change time is u comparison value time, the second bus current change time is advanced by dead time relative to v comparison value time, and the third bus current change time is advanced by dead time relative to w comparison value time

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tu+tsd1, tad2=tv-tdd+tsd2;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th+tdd, tmin2=tsd2+th;

if the uvw phase current flows at uvw comparison value time are positive, positive and negative (i.e. iu > 0, iv > 0 and iw < 0), respectively, determining that the first bus current change time is u comparison value time, the second bus current change time is v comparison value time, and the third bus current change time is advanced by dead time relative to w comparison value time

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=ton+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tu+tsd1, tad2=tv+tsd2;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th, tmin2=tsd2+th+tdd;

if the uvw phase current flows at the uvw comparison value time are negative, positive and negative (i.e. iu < 0, iv > 0 and iw is smaller than 0), respectively, determining that the first bus current change time is u comparison value time advanced by dead time relative to u comparison value time, the second bus current change time is v comparison value time, and the third bus current change time is advanced by dead time relative to w comparison value time

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tu-tdd+tsd1, tad2=tv+tsd2;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th-Tdd, tmin2=tsd2+th+tdd;

if the uvw phase current flows at uvw comparison value time are negative, positive and positive (i.e. iu < 0, iv > 0 and iw > 0), respectively, it is determined that the first bus current change time is u comparison value time advanced by dead time relative to u comparison value time, the second bus current change time is v comparison value time, and the third bus current change time is w comparison value time

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th-Tdd, tmin2=tsd2+th;

if the current direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive (i.e. iu < 0, iv < 0 and iw > 0), respectively, determining that the first bus current change moment is u comparison value moment advanced by dead time relative to u comparison value moment, the second bus current change moment is advanced by dead time relative to v comparison value moment, and the third bus current change moment is w comparison value moment

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=toff+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tu-tdd+tsd1, tad2=tv-tdd+tsd2;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th, tmin2=tsd2+th-Tdd;

if the uvw phase current flows at uvw comparison value time are positive, negative and positive (i.e. iu > 0, iv < 0 and iw > 0), respectively, it is determined that the first bus current change time is u comparison value time, the second bus current change time is advanced by dead time relative to v comparison value time, and the third bus current change time is w comparison value time

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th+tdd, tmin2=tsd2+th-Tdd.

In one embodiment, based on the same principle as the second dead zone generation method shown in fig. 8, when the half carrier period is the carrier falling edge period, if the uvw phase current flows at uvw comparison value time are positive, negative and negative, respectively, the dead zone time of the u comparison value time lag behind the first bus current change time is determined, the second bus current change time is the v comparison value time, and the third bus current change time is the w comparison value time

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tu+tdd+tsd1, tad2=tv+tsd2;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, determining dead time of the u comparison value moment lagging behind the first bus current change moment, wherein the second bus current change moment is v comparison value moment lagging behind the v comparison value moment dead time, and the third bus current change moment is w comparison value moment

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=ton+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tu+tdd+tsd1, tad2=tv+tdd+tsd2;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and negative respectively, determining that the first bus current change moment is u comparison value moment, the second bus current change moment lags by the dead time of the v comparison value moment, and the third bus current change moment is w comparison value moment

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tu+tsd1, tad2=tv+tdd+tsd2;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and positive respectively, determining that the first bus current change moment is u comparison value moment, the second bus current change moment lags the v comparison value moment dead time, and the third bus current change moment lags the w comparison value moment dead time

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive respectively, determining that the first bus current change moment is u comparison value moment, the second bus current change moment is v comparison value moment, and the third bus current change moment lags by the dead time of the w comparison value moment

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, negative and positive respectively, determining dead time of the u comparison value moment after the first bus current change moment, wherein the second bus current change moment is v comparison value moment, and the third bus current change moment lags the w comparison value moment dead time

The minimum sampling delay is calculated as: tsd1=ton+tst, tsd2=toff+tst;

the minimum sampling time is calculated as: tad1=tu+tsd1+tdd, tad2=tv+tsd2;

In one embodiment, based on the first dead zone generation mode, when the half carrier period is the carrier rising edge period, if the flow direction of the uvw phase current at the uvw comparison value time is positive, negative and negative, respectively, the dead zone time is determined to lag the first bus current change time relative to the w comparison value time, the dead zone time is lagged to lag the second bus current change time relative to the v comparison value time, and the third bus current change time is the u comparison value time

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=ton+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tw+tdd+tsd1, tad2=tv+tdd+tsd2;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, determining that the first bus current change moment lags behind the w comparison value moment by dead time, the second bus current change moment is v comparison value moment, and the third bus current change moment is u comparison value moment

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tw+tdd+tsd1, tad2=tv+tsd2;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and negative respectively, determining that the first bus current change moment lags the dead time relative to the w comparison value moment, the second bus current change moment is the v comparison value moment, and the third bus current change moment lags the dead time relative to the u comparison value moment

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th+tdd, tmin2=tsd2+th-Tdd;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and positive respectively, determining that the first bus current change moment is w comparison value moment, the second bus current change moment is v comparison value moment, and the third bus current change moment lags behind the u comparison value moment by dead time

the calculation formula of the minimum sampling moment is as follows: tad1=tw+tsd1, tad2=tv+tsd2;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive respectively, determining that the first bus current change moment is w comparison value moment, the second bus current change moment lags behind the v comparison value moment by dead time, and the third bus current change moment lags behind the u comparison value moment by dead time

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tw+tsd1, tad2=tv+tdd+tsd2;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, negative and positive respectively, determining that the first bus current change moment is w comparison value moment, the second bus current change moment lags behind the v comparison value moment by dead time, and the third bus current change moment is u comparison value moment

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th-Tdd, tmin2=tsd2+th+tdd.

In one embodiment, based on the second dead zone generation, when the half carrier period is the carrier rising edge period,

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, negative and negative respectively, determining that the first bus current change moment is w comparison value moment, the second bus current change moment is v comparison value moment, and the third bus current change moment is advanced by dead time relative to the u comparison value moment, then:

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=ton+tst;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, determining that the first bus current change moment is w comparison value moment, advancing the dead time relative to the v comparison value moment by the second bus current change moment, and advancing the dead time relative to the u comparison value moment by the third bus current change moment, then:

the minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tw+tsd1, tad2=tv+tsd2-Tdd;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and negative respectively, determining that the first bus current change moment is w comparison value moment, the second bus current change moment is advanced by dead time relative to the v comparison value moment, and the third bus current change moment is u comparison value moment, then:

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and positive respectively, determining that the first bus current change moment advances by dead time relative to the w comparison value moment, the second bus current change moment advances by dead time relative to the v comparison value moment, and the third bus current change moment is the u comparison value moment, then:

the calculation formula of the minimum sampling moment is as follows: tad1=tw+tsd1-Tdd, tad2=tv+tsd2-Tdd;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive respectively, determining that the first bus current change moment advances by dead time relative to the w comparison value moment, the second bus current change moment is the v comparison value moment, and the third bus current change moment is the u comparison value moment, then:

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

the calculation formula of the minimum sampling moment is as follows: tad1=tw+tsd1-Tdd, tad2=tv+tsd2;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, negative and positive respectively, determining that the first bus current change moment advances by dead time relative to the w comparison value moment, the second bus current change moment is v comparison value moment, and the third bus current change moment advances by dead time relative to the u comparison value moment, then:

the minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

In each of the above-described dead zone generation mode embodiments, tsd1 and Tsd2 represent minimum sampling delays, ton represents an on delay, toff represents an off delay, tst represents an oscillation time, tad1 and Tad2 represent minimum sampling times, tu, tv, and Tw represent uvw comparison value times, tmin1 represents a minimum effective vector duration corresponding to the minimum sampling time Tad1, tmin2 represents a minimum effective vector duration corresponding to the minimum sampling time Tad2, th represents a sampling process time, and Tdd represents a dead zone time.

It should be understood that, the sequence number of each step in the foregoing embodiment does not mean the sequence of execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

The embodiment of the application also provides a single bus current detection device which is applied to the motor controller and is used for executing the steps in the embodiment of the method. The device may be a virtual device (virtual appliance) in the motor controller, run by a processor of the motor controller, or may be the motor controller itself.

As shown in fig. 12, a single bus current detection device 100 provided in an embodiment of the present application includes:

a time determining unit 101, configured to determine, in a half-carrier period, a minimum sampling time and a minimum effective vector duration of the bus current according to a flow direction of a uvw phase current at a uvw comparison value time, where the uvw comparison value is obtained by descending the abc comparison value according to a numerical order;

a current sampling unit 102 for sampling the bus current at a minimum sampling instant for a minimum effective vector duration.

In one embodiment, the single bus current detection device further comprises:

The comparison value acquisition unit is used for acquiring an abc comparison value according to the amplitude and the phase angle of the target voltage vector in the half-carrier period;

the phase sequence mapping unit is used for sequencing the abc comparison values according to the numerical descending order to obtain uvw comparison values;

a first time acquisition unit configured to use a duration between the start time and the u comparison value time as a duration of a first zero vector;

a second time acquisition unit configured to set a duration between the u comparison value time and the v comparison value time as a duration of the first effective vector;

a third time acquisition unit configured to set a duration between the v comparison value time and the w comparison value time as a duration of the second effective vector;

and a fourth time acquisition unit configured to use a duration between the w comparison value time and the end time as a duration of the second zero vector.

In one embodiment, the time determination unit comprises:

the first time determining subunit is used for determining the bus current change time and the minimum sampling delay according to the flow direction of the uvw phase current at the uvw comparison value time;

the second time determining subunit is used for determining the minimum sampling time according to the bus current change time and the minimum sampling delay;

And a third time determining subunit, configured to determine a minimum valid vector duration according to the minimum sampling delay.

In one embodiment, the first time determination subunit is specifically configured to:

when the half carrier period is a carrier falling edge period, if the flow direction of uvw phase current at the uvw comparison value moment is positive, negative and negative respectively, determining that the first bus current change moment is u comparison value moment, advancing dead time relative to v comparison value moment at the second bus current change moment, and advancing dead time relative to w comparison value moment at the third bus current change moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, determining that the first bus current change moment is u comparison value moment, the second bus current change moment is v comparison value moment, and advancing the third bus current change moment by dead time relative to the w comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and negative respectively, determining that the first bus current change moment is the dead time advanced relative to the u comparison value moment, the second bus current change moment is the v comparison value moment, and the third bus current change moment is the dead time advanced relative to the w comparison value moment;

If the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and positive respectively, determining that the first bus current change moment is u comparison value moment advanced by dead time relative to the u comparison value moment, the second bus current change moment is v comparison value moment, and the third bus current change moment is w comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive respectively, determining that the first bus current change moment is u comparison value moment advanced by dead time relative to u comparison value moment, the second bus current change moment is advanced by dead time relative to v comparison value moment, and the third bus current change moment is w comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, negative and positive respectively, determining that the first bus current change moment is u comparison value moment, the second bus current change moment is advanced by dead time relative to the v comparison value moment, and the third bus current change moment is w comparison value moment.

when the half carrier period is a carrier falling edge period, if the flow direction of uvw phase current at the uvw comparison value moment is positive, negative and negative respectively, determining dead time of the u comparison value moment after the first bus current change moment, wherein the second bus current change moment is v comparison value moment, and the third bus current change moment is w comparison value moment;

If the flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, determining dead time of the u comparison value moment lagging behind the first bus current change moment, wherein the second bus current change moment is v comparison value moment lagging behind the v comparison value moment dead time, and the third bus current change moment is w comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and negative respectively, determining that the first bus current change moment is u comparison value moment, the second bus current change moment lags by the dead time of the v comparison value moment, and the third bus current change moment is w comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and positive respectively, determining that the first bus current change moment is u comparison value moment, the second bus current change moment lags the v comparison value moment dead time, and the third bus current change moment lags the w comparison value moment dead time;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive respectively, determining that the first bus current change moment is u comparison value moment, the second bus current change moment is v comparison value moment, and the third bus current change moment lags by the dead time of the w comparison value moment;

If the flow direction of the uvw phase current at the uvw comparison value moment is positive, negative and positive respectively, determining dead time of the u comparison value moment after the first bus current change moment, wherein the second bus current change moment is v comparison value moment, and the third bus current change moment lags by w comparison value moment dead time;

when the half carrier period is a carrier rising edge period, if the flow direction of uvw phase current at the uvw comparison value moment is positive, negative and negative respectively, determining that the first bus current change moment lags the dead time relative to the w comparison value moment, the second bus current change moment lags the dead time relative to the v comparison value moment, and the third bus current change moment is the u comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, determining the dead time of the hysteresis of the first bus current change moment relative to the w comparison value moment, wherein the second bus current change moment is the v comparison value moment, and the third bus current change moment is the u comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and negative respectively, determining the hysteresis dead time of the first bus current change moment relative to the w comparison value moment, wherein the second bus current change moment is the v comparison value moment, and the third bus current change moment is the hysteresis dead time relative to the u comparison value moment;

If the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and positive respectively, determining that the first bus current change moment is w comparison value moment, the second bus current change moment is v comparison value moment, and the third bus current change moment lags by dead time relative to the u comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive respectively, determining that the first bus current change moment is w comparison value moment, wherein the second bus current change moment lags the dead time relative to the v comparison value moment, and the third bus current change moment lags the dead time relative to the u comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is positive, negative and positive respectively, determining that the first bus current change moment is w comparison value moment, the second bus current change moment is delayed by dead time relative to the v comparison value moment, and the third bus current change moment is u comparison value moment.

when the half carrier period is a carrier rising edge period, if the flow direction of uvw phase current at the uvw comparison value moment is positive, negative and negative respectively, determining that the first bus current change moment is w comparison value moment, the second bus current change moment is v comparison value moment, and the third bus current change moment is advanced by dead time relative to the u comparison value moment;

If the flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, determining that the first bus current change moment is w comparison value moment, advancing the dead time relative to the v comparison value moment at the second bus current change moment, and advancing the dead time relative to the u comparison value moment at the third bus current change moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and negative respectively, determining that the first bus current change moment is w comparison value moment, advancing the dead time relative to the v comparison value moment by the second bus current change moment, and determining that the third bus current change moment is u comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, positive and positive respectively, determining that the first bus current change moment advances by dead time relative to the w comparison value moment, the second bus current change moment advances by dead time relative to the v comparison value moment, and the third bus current change moment is the u comparison value moment;

if the flow direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive respectively, determining that the first bus current change moment advances by dead time relative to the w comparison value moment, the second bus current change moment is the v comparison value moment, and the third bus current change moment is the u comparison value moment;

If the flow direction of the uvw phase current at the uvw comparison value moment is positive, negative and positive respectively, the dead time of the first bus current change moment relative to the w comparison value moment is determined, the second bus current change moment is the v comparison value moment, and the dead time of the third bus current change moment relative to the u comparison value moment is determined.

In one embodiment, the single bus current detection device further comprises a current flow direction determination unit for:

where x=u, v, w.

In application, each component in the above device may be a software program unit, or may be implemented by different logic circuits integrated in a processor or separate physical components connected with the processor, or may be implemented by multiple distributed processors.

According to the single bus current detection device, in a half-carrier period, the uvw comparison value is obtained after the abc comparison value is reduced according to the numerical value, the minimum sampling time and the minimum effective vector duration of the bus current are determined according to the flow direction of uvw phase current at the uvw comparison value time, the bus current is sampled at the minimum sampling time and the minimum effective vector duration is sustained, when the single bus current is detected, the influence of the current flow direction and dead zone effect on the bus current change is considered, the minimum sampling time and the minimum effective vector duration of the bus current are calculated in an optimized mode, and the minimum effective vector duration can be optimized dynamically on the basis of ensuring the bus current sampling accuracy, so that current harmonics are reduced.

As shown in fig. 13, the embodiment of the present application further provides a motor controller 200, including: at least one processor 201 (only one processor is shown in fig. 13), a memory 202, and a computer program 203 stored in the memory 202 and executable on the at least one processor 201, the steps of the various method embodiments described above being implemented when the processor 201 executes the computer program 203.

In applications, the motor controller may include, but is not limited to, a processor and a memory, may also include the current sensor and inverter shown in fig. 1, and/or may also include a filter, PWM driver, analog-to-digital converter, and the like. It will be appreciated by those skilled in the art that fig. 13 is merely an example of a motor controller and is not intended to be limiting, and may include more or fewer components than shown, or may combine certain components, or may include different components, for example, input-output devices, network access devices, etc. The input/output device may include the aforementioned human-computer interaction device, and may further include a display screen for displaying operating parameters of the motor controller. The network access device may include a communication module for the motor controller to communicate with the client.

In application, the processor may be a central processing unit (Central Processing Unit, CPU), which may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

In applications, the memory may in some embodiments be an internal storage unit of the motor controller, such as a hard disk or a memory of the motor controller. The memory may also be an external storage device of the motor controller in other embodiments, for example, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash Card (Flash Card) or the like, which are provided on the motor controller. The memory may also include both internal memory units and external memory devices of the motor controller. The memory is used to store an operating system, application programs, boot Loader (Boot Loader), data, and other programs, etc., such as program code for a computer program, etc. The memory may also be used to temporarily store data that has been output or is to be output.

In applications, the display may be a thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD), liquid crystal display (Liquid Crystal Display, LCD), organic electro-laser display (Organic Electroluminesence Display, OLED), quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display, seven-segment or eight-segment nixie tube, or the like.

In application, the communication module can be set as any device capable of directly or indirectly carrying out long-distance wired or wireless communication with the client according to actual needs, so that a user can control the working state of the motor by using the motor controller through operating the client, and further control the working states of equipment such as an air conditioner, a fan, a washing machine and the like applied by the motor. The communication module may provide solutions for communication including wireless local area network (Wireless Localarea Networks, WLAN) (e.g., wi-Fi network), bluetooth, zigbee, mobile communication network, global navigation satellite system (Global Navigation Satellite System, GNSS), frequency modulation (Frequency Modulation, FM), near field wireless communication technology (Near Field Communication, NFC), infrared technology (IR), etc. for application on a network device. The communication module may include an antenna, which may have only one element, or may be an antenna array including a plurality of elements. The communication module can receive electromagnetic waves through the antenna, frequency-modulate and filter the electromagnetic wave signals, and send the processed signals to the processor. The communication module can also receive the signal to be transmitted from the processor, frequency modulate and amplify the signal, and convert the signal into electromagnetic waves through the antenna to radiate.

It should be noted that, because the content of information interaction and execution process between the above devices/modules is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein again.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the above-described functions. The functional modules in the embodiment may be integrated in one processing module, or each module may exist alone physically, or two or more modules may be integrated in one module, where the integrated modules may be implemented in a form of hardware or a form of software functional modules. In addition, the specific names of the functional modules are only for distinguishing from each other, and are not used for limiting the protection scope of the application. The specific working process of the modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

The embodiments of the present application further provide a computer readable storage medium, where a computer program is stored, where the computer program can implement the steps in the above-mentioned method embodiments when executed by a processor.

Embodiments of the present application provide a computer program product enabling a motor controller to carry out the steps of the method embodiments described above when the computer program product is run on the motor controller.

The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, where the computer program may implement the steps of each of the method embodiments described above when executed by a processor. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a motor controller, a recording medium, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a U-disk, removable hard disk, magnetic or optical disk, etc.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or modules, which may be in electrical, mechanical or other forms.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. A single bus current detection method, comprising:

2. The method for detecting single bus current according to claim 1, wherein determining the minimum sampling time and the minimum effective vector duration of the bus current according to the flow direction of the uvw phase current at the uvw comparison value time comprises:

determining the change time of the bus current and the minimum sampling delay according to the flow direction of the uvw phase current at the uvw comparison value time;

determining the minimum sampling time according to the bus current change time and the minimum sampling delay;

the minimum effective vector duration is determined based on the minimum sampling delay.

3. The single busbar current detection method of claim 2, wherein the half carrier period is a falling edge period;

if the current direction of the uvw phase current at the uvw comparison value moment is positive, negative and negative respectively, then

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

if the current flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, then

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=ton+tst;

if the current direction of the uvw phase current at the uvw comparison value moment is negative, positive and negative respectively, then

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

if the current direction of the uvw phase current at the uvw comparison value moment is negative, positive and positive respectively, then

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

if the current direction of the uvw phase current at the uvw comparison value moment is negative, negative and positive respectively, then

if the current directions of the uvw phase currents at the uvw comparison value moment are positive, negative and positive respectively, then

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

where Tsd1 and Tsd2 denote minimum sampling delays, ton denote on delays, toff denote off delays, tst denote oscillation times, tad1 and Tad2 denote minimum sampling times, tu, tv and Tw denote uvw comparison value times, tmin1 denotes a minimum effective vector duration corresponding to the minimum sampling time Tad1, tmin2 denotes a minimum effective vector duration corresponding to the minimum sampling time Tad2, th denotes a sampling process time, and Tdd denotes dead time.

4. The single busbar current detection method of claim 2, wherein the half carrier period is a falling edge period;

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=ton+tst;

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

The minimum sampling delay is calculated as: tsd1=ton+tst, tsd2=toff+tst;

the minimum sampling time is calculated as: tad1=tu+tsd1+tdd, tad2=tv+tsd2;

5. The single busbar current detection method of claim 2, wherein the half carrier period is a rising edge period;

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=ton+tst;

the minimum effective vector duration calculation formula is: tmin1=tsd1+th, tmin2=tsd2+th+tdd; if the current flow direction of the uvw phase current at the uvw comparison value moment is positive, positive and negative respectively, then

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

6. The single busbar current detection method of claim 2, wherein the half carrier period is a rising edge period;

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=ton+tst;

The minimum sampling delay calculation formula is: tsd1=ton+tst, tsd2=toff+tst;

The minimum sampling delay calculation formula is: tsd1=toff+tst, tsd2=ton+tst;

7. The method for detecting single bus current according to any one of claims 1 to 6, wherein before determining the minimum sampling time and the minimum effective vector duration of the bus current according to the flow direction of the uvw phase current at the uvw comparison value time, the method comprises:

where x=u, v, w.

8. A single bus current detection device, comprising:

9. A motor controller comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the single bus current detection method according to any one of claims 1 to 7 when the computer program is executed.

10. A computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the single busbar current detection method of any one of claims 1 to 7.