CN117638482A - Phased array front end architecture based on scalable AiP - Google Patents
Phased array front end architecture based on scalable AiP Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 38
- 230000005540 biological transmission Effects 0.000 claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 238000006243 chemical reaction Methods 0.000 claims abstract description 10
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 10
- 230000006641 stabilisation Effects 0.000 claims abstract description 7
- 238000011105 stabilization Methods 0.000 claims abstract description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 101
- 230000017525 heat dissipation Effects 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 230000003071 parasitic effect Effects 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 8
- 239000004677 Nylon Substances 0.000 claims description 4
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 229920001778 nylon Polymers 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 4
- 230000002194 synthesizing effect Effects 0.000 claims description 4
- 239000011368 organic material Substances 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 3
- 230000010354 integration Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 12
- 230000005855 radiation Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- CJDNEKOMKXLSBN-UHFFFAOYSA-N 1-chloro-3-(4-chlorophenyl)benzene Chemical compound C1=CC(Cl)=CC=C1C1=CC=CC(Cl)=C1 CJDNEKOMKXLSBN-UHFFFAOYSA-N 0.000 description 2
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
The scheme discloses a phased array front-end architecture based on a scalable AiP, which comprises a scalable AiP module, a heat-dissipating cold plate and a comprehensive motherboard, wherein the scalable AiP module comprises a radio-frequency multi-layer PCB (printed circuit board), and each TR (transmitter/receiver) channel of a beam former chip in the radio-frequency multi-layer PCB is respectively connected with one antenna unit of a patch array antenna; the expandable AiP module realizes radio frequency feed wiring, control transmission wiring and DC power supply wiring through the radio frequency multi-layer PCB substrate, and a radio frequency interface, a control interface and a power supply interface are arranged on the bottom layer; the comprehensive motherboard comprises a radio frequency synthesis network module, a control signal generation and driving module, a power supply conversion and voltage stabilization module; the radio frequency interface is connected with the radio frequency synthesis network module through a radio frequency connecting wire; the control interface is connected with the control signal generating and driving module through a control connecting wire; the power supply interface is connected with the power supply conversion and voltage stabilization module through a power supply connecting wire, so that the expandable and reconfigurable characteristic of the array surface is realized.
Description
Technical Field
The invention belongs to the technical field of array packaging antennas, and particularly relates to a phased array front-end architecture based on a scalable AiP.
Background
Phased array radars have been used in recent years for 5G communications, satellite communications, automotive radars. The phased array Lei Dayin has controllable beam pointing and great potential in improving the signal-to-noise ratio of specific user communication and radar target detection tracking. In the Ka band or the millimeter band, in order to meet the condition that a scanning beam has no grating lobe, the space between antenna units is usually smaller than 10mm, the traditional TR module has too large volume to meet the condition of the space between channels, and the multi-TR channel beam former chip adopting the S i-based or S iGe-based technology has obvious advantages in low cost and high integration level, so that a single-board integration scheme of the millimeter wave array antenna and the beam former chip is researched and applied.
Due to the adoption of the patch antenna and the multi-TR channel integrated beam forming device chip, the single-board integrated advantage of the antenna and the beam forming device chip is gradually obvious. The patch antenna and the beam forming device are connected by adopting an in-board microstrip line, a strip line feed network and a vertical pseudo-coaxial structure, and the connector is omitted, so that the integration level is improved, and meanwhile, the cost is reduced.
Millimeter wave phased array AiP can be broadly categorized into three architectural approaches, single board integration, package integration, and wafer integration, depending on the integrated architecture and system morphology of millimeter wave phased array AiP as studied by numerous scholars. The single board integration scheme integrates the antenna, the beam former, the power supply IC and the control IC on one PCB substrate, and the number of required PCB layers is high, so that the number of pressing times in the PCB manufacturing process is high, and the problems of high cost and low yield are solved. The package integration scheme is mostly mounted on an organic multi-layer board or a multi-layer ceramic substrate of the antenna radio frequency integration by adopting a radio frequency die flip-chip technology, and is further electrically connected and structurally fixed to a power supply control motherboard through BGA solder balls, so that the package integration scheme has the characteristic of expandability, but the welding assembly technology is high and conventional production line cannot meet the requirement, and uneven antenna array surface formed by a plurality of packages AiP due to inconsistent melting heights of the BGA solder balls can be generated. The wafer integration scheme is to design a plurality of antenna units, a plurality of TR channels and a radio frequency integrated network on one chip, and has the advantages of highest integration level, but has the problems of low success rate and long development period due to various functional modules.
In order to solve the problems of the three aforementioned architectures, a learner proposes a module integration architecture that requires a compromise between cost and scalable functionality, but no successful and better module integration scheme has been proposed so far.
Disclosure of Invention
Based on the background, the scheme is provided.
The phased array front end architecture based on the expandable AiP sequentially comprises an expandable AiP module, a heat dissipation cold plate and a comprehensive motherboard, wherein the expandable AiP module comprises a radio frequency multi-layer PCB substrate, a patch array antenna is printed on the surface layer of the radio frequency multi-layer PCB substrate, a beam former chip with a plurality of TR channels is arranged on the bottom layer, and each TR channel of the beam former chip is connected with one antenna unit of the patch array antenna through an internal wiring of the radio frequency multi-layer PCB substrate;
the expandable AiP module realizes radio frequency feed wiring, control transmission wiring and DC power supply wiring through internal wiring of the radio frequency multi-layer PCB substrate, and corresponding radio frequency interface, control interface and power supply interface are configured at the bottom layer;
the comprehensive motherboard comprises a radio frequency synthesis network module for providing radio frequency signals, control signals and power supply for the expandable AiP module respectively, a control signal generating and driving module and a power supply converting and voltage stabilizing module;
the radio frequency interface is connected with the radio frequency synthesis network module through a radio frequency connecting wire; the control interface is connected with the control signal generating and driving module through a control connecting wire; the power supply interface is connected with the power supply conversion and voltage stabilization module through a power supply connecting wire.
The radio frequency multi-layer PCB substrate mainly realizes the packaging integration of the array antenna and the beam former chip, and completes the transmission of radio frequency signals, power supply transmission, control signal transmission and structural support of Ka wave band in the PCB substrate.
The integrated motherboard comprises a high-frequency mixed voltage PCB, a power IC and a control IC. The radio frequency synthesis network module is positioned in the high-frequency mixed voltage PCB; the control IC comprises a control signal generation and driving module taking an FPGA as a core device; the power supply IC device power supply conversion and voltage stabilizing module mainly comprises a DCDC voltage conversion device and an LDO voltage stabilizing device. The control signal of the integrated motherboard to the expandable AiP module is 1.8V level standard, and comprises a clock signal CLK_IN, a serial data input SDI, a serial data output SDO, chip select signals CSB 1-4, a radio frequency transmission control signal TX and a radio frequency reception control signal RX.
Through the technical scheme, a plurality of expandable AiP modules can be mounted on the heat dissipation cold plate and the comprehensive motherboard, so that the array surface expandable reconfigurable characteristic is realized. And each expandable AiP module is an active antenna array with independent and complete functional structure, the index of each expandable AiP module can be tested and verified independently, and the rapid and efficient maintenance is realized by replacing the failed AiP module.
In the foregoing phased array front end architecture based on the scalable AiP, the power supply connection wires are power supply copper pillars, and are electrically connected and simultaneously serve as a support structure of the scalable AiP module.
The radio frequency signal is transmitted through the radio frequency connecting wire, the control signal is transmitted through the control connecting wire, and the DC power supply is transmitted through the power supply copper column.
In the foregoing phased array front end architecture based on the scalable AiP, the scalable AiP module is scalable by the following manner:
the expandable AiP module and the power supply copper column are fixedly connected through nylon screws, and the control connecting wire and the radio frequency connecting wire are connected out;
mounting one or more expandable AiP modules to be expanded to the heat dissipation cold plate by adopting metal screws; a plurality of expandable AiP modules are horizontally arranged on the heat-dissipating cold plate;
the power supply copper column, the radio frequency connecting wire and the control connecting wire penetrate through the heat dissipation cold plate to be connected with the integrated motherboard;
and finally, fixing the comprehensive mother board and the heat-dissipation cold board by adopting metal screws, and finally splicing a plurality of expandable AiP modules, the heat-dissipation cold board and the comprehensive mother board into a complete array surface.
When the heat dissipation system is put into use, the number of the required assembled expandable AiP modules is determined according to the required array surface size or channel scale, and the sizes of the heat dissipation cold plates and the comprehensive mother plates are determined according to the number of the required expandable AiP modules in practical application.
In the above-mentioned phased array front-end architecture based on scalable AiP, the bottom layer of the radio frequency multi-layer PCB substrate is provided with a plurality of beamformer chips;
and each beam forming device chip is attached to the bottom layer of the radio frequency multi-layer PCB substrate through an SMT process.
In the phased array front end architecture based on the scalable AiP, the radio frequency interface adopts a surface mount SSMP connector for providing a transmitting radio frequency signal input and a receiving radio frequency signal output;
the power supply interface adopts a PCB surface bonding pad for providing voltage bias and power input required by the operation of the beam former chip;
the control interface adopts an FPC connector and is used for transmitting a receiving and transmitting control signal, a channel amplitude control signal and a channel phase control signal.
The power interface includes a 2.5V voltage bias and a 1.8V voltage bias. The power supply interface is a surface layer bonding pad, and is electrically connected in a crimping mode by adopting a power supply copper column and the bonding pad, and the copper column is used as a structural support to relatively fix the positions of the radio frequency multi-layer PCB substrate and the heat dissipation cold plate.
In the foregoing phased array front end architecture based on the scalable AiP, the scalable AiP module further includes a thermal pad, where one surface of the thermal pad is in contact with the beamformer chip and the other surface of the thermal pad is in contact with the heat sink cold plate.
The beam forming device chip is packaged by LGA based on an S iGe process, and is welded with the radio frequency multi-layer PCB substrate in a SMT mode with low cost and mature process, and the heat conducting pad is arranged on the beam forming device chip packaging shell.
In the foregoing phased array front end architecture based on scalable AiP, the rf multi-layer PCB substrate includes ten metal signal layers laminated by nine layers of organic material layers. The size of the radio frequency multi-layer PCB substrate defines a length, which is an antenna element length dx times the number of length-direction antenna elements, and a width, which is an antenna element width dy times the number of width-direction antenna elements, according to the scalable characteristics. And, the two-dimensional size of a single scalable AiP module is equal to the array antenna caliber, no edge expansion exists, and the reconfigurable characteristics of a plurality of scalable AiP to different scale phased array planes are provided.
In the foregoing phased array front end architecture based on scalable AiP, the ten metal signal layers sequentially include a parasitic patch layer TOP, a radiation patch layer mL1, an antenna ground layer mL2, a transition layer mL3, a power supply and control signal 1 layer mL4, a power supply and control signal 2 layer mL5, a stripline upper reference layer mL6, a stripline equal phase feed network layer mL7, a stripline lower reference ground and microstrip line reference layer mL8, a device, and a radio frequency power division network layer BOT.
In the foregoing scalable AiP-based phased array front end architecture, the radiating antenna elements of the patch array antenna include a parasitic patch antenna element disposed on the parasitic patch layer TOP, a radiating patch element disposed on the radiating patch layer mL1, and an antenna floor element disposed on the antenna floor layer mL2;
the antenna feed structure of the patch array antenna is a pseudo-coaxial feed structure consisting of a vertical metallized radio frequency signal hole connected with one end of a radiating antenna unit and a reference ground hole connected with an antenna floor unit. The surface layer printed with the patch array antenna comprises a parasitic patch layer TOP, a radiation patch layer mL1 and an antenna floor layer mL2; the bottom layer of the surface-mounted beam forming device chip comprises a device and a radio frequency power division network layer BOT, and the rest middle layers are inner layers of the radio frequency multi-layer PCB substrate.
In the phased array front-end architecture based on the scalable AiP, the beamformer chip is used for completing the transmission amplification of radio frequency signals, the transmission amplitude control of multiple channels, the transmission phase control of multiple channels and the distribution of the transmission power of multiple channels in a transmission working state; the method comprises the steps of receiving and amplifying a radio frequency signal in a receiving working state, controlling the receiving amplitude of multiple channels, controlling the receiving phase of multiple channels and synthesizing the receiving power of multiple channels. Taking a 16-channel beam former chip and a Ka wave band as an example, the 16-channel receiving and transmitting beam former chip is used for completing the transmission amplification of radio frequency signals, the transmission amplitude control of the 16 channels, the transmission phase control of the 16 channels and the transmission power distribution of the 16 channels under the transmission working state of the Ka wave band; the method comprises the steps of receiving and amplifying a radio frequency signal in a receiving working state, controlling the receiving amplitude of a 16 channel, controlling the receiving phase of the 16 channel and synthesizing the receiving power of the 16 channel.
The invention has the advantages that:
the expandable AiP-based phased array front end structure reduces connecting cables and connectors, and the distance between an antenna and a TR channel is smaller, so that the transmission loss of radio frequency signals is reduced, and the low receiving noise coefficient and the high transmitting power are realized;
the module integration scheme for assembling a plurality of standardized expandable AiP modules on the heat radiation cold plate and the comprehensive mother plate has the advantages of expandable array surface, reconfigurability, easy replacement and maintenance and the like;
the framework adopted by the invention is more flexible in the aspects of updating and replacing the antenna and the beam former chip, and has a shorter research and development period;
the structure compromise of the scheme considers cost and expandable function, the limited array antenna unit and the wave beam former chip with a plurality of TR channels are integrated into the active AiP subarray module through the PCB substrate, and a plurality of expandable AiP modules are secondarily integrated on the comprehensive motherboard, so that the array surface scale is expandable, and the application requirements of low cost, miniaturization, high integration and expandability of the front end of the millimeter wave band phased array can be met;
the power supply conversion part and the control signal generation and driving part are divided into the comprehensive mother board, so that the number of layers of a single PCB substrate is reduced, the PCB lamination times are reduced, the manufacturing difficulty is reduced, and the yield is improved;
the heat dissipation cold plate is arranged between the AiP module and the comprehensive mother board, so that the Aip module and the comprehensive mother board can be simultaneously subjected to heat dissipation, and the AiP module and the comprehensive mother board have good heat dissipation performance, and the problems of high temperature array surface failure and the like caused by heat accumulation due to overlarge heat consumption in unit volume can be avoided;
the mode that the copper columns are multiplexed to the structure fixing and power supply connection is provided, so that the structure reliability and the integration degree are improved, and the two-dimensional flatness of the array antenna formed by the AiP modules is improved;
the mounting mode of fixing the heat dissipation cold plate through the copper column and the nylon screw can not produce solder ball to melt inconsistent, electrical connection failure, module displacement and other adverse effects to the AiP module around in the replacement fault AiP module process, has better more convenient replaceability and maintainability.
Drawings
Fig. 1 is a schematic diagram of an architecture of the present invention based on a scalable AiP phased array front end architecture.
Fig. 2 is a front view of an antenna array formed of four expandable AiP blocks;
fig. 3 is a block diagram of the scalable AiP module of fig. 1.
Fig. 4 is a laminate of the radio frequency multi-layer PCB substrate of fig. 3.
Fig. 5 is a TOP layer pattern of a radio frequency multi-layer PCB substrate.
Fig. 6 is a mL1 layer pattern of a radio frequency multi-layer PCB substrate.
Fig. 7 is a BOT layer pattern and device of a radio frequency multi-layer PCB substrate.
Fig. 8 is a functional block diagram of the 16-channel beamformer chip interior.
Fig. 9 is a composition diagram of the integrated motherboard of fig. 1.
Fig. 10 is a schematic diagram of a phased array front end architecture connection based on scalable AiP and a schematic diagram of the integrated motherboard internal functions;
fig. 11 is an E-plane beam pointing scan simulation pattern of the scalable AiP.
Fig. 12 is an H-plane beam-pointing scan simulation pattern of the scalable AiP.
Reference numerals: scalable AiP module 1; a heat radiation cold plate 2; a comprehensive motherboard 3; a radio frequency connection line 4; a power supply copper column 5; a control connection line 6; a radio frequency multilayer PCB substrate 7; a beamformer chip 8; a heat conductive pad 9; a radio frequency interface 10; a power supply interface 11; a control interface 12; a high-frequency mixed-voltage PCB 13; a power supply IC14; a control IC15; a parasitic patch antenna element 16; a radiation patch unit 17; an antenna floor unit 18; a vertical metallized radio frequency signal aperture 19; reference ground hole 20.
Detailed Description
The invention will be described in further detail with reference to the drawings and the detailed description.
The scheme provides a phased array front end architecture based on scalable AiP, and this embodiment uses Ka wave band as an example to describe the phased array front end architecture based on scalable AiP suitable for Ka wave band, and as shown in fig. 1, the phased array front end architecture comprises scalable AiP module 1, cooling plate 2, integrated motherboard 3, radio frequency connecting wire 4, power supply copper column 5, and control connecting wire 6. The expandable AiP (Antenna in Package) module 1 integrates an antenna and an active TR channel (or a high-integration TR chip) into a package based on packaging materials and processes, and realizes the receiving and transmitting beam pointing of electromagnetic wave signal energy. Aiming at the difference of indexes such as beam width, EIRP, receiving gain and the like required in different application demands, the phased array AiP is designed into an expandable module and can be assembled to a motherboard for a second time relatively easily, so that the array plane reconfigurable characteristic is realized, meanwhile, as the modularized expandable AiP module 1, the mass production cost is reduced, the fault replacement and easy maintenance characteristics are improved.
In this embodiment, four 16-channel beam former chips 8 are disposed on the expandable AiP module 1, and a total of 64 antenna units of 8×8 are printed on the rf multi-layer PCB substrate 7, where the antenna units are arranged in a rectangular grid, the transverse spacing dx and the longitudinal spacing dy, so that the transverse dimension dx×8 and the longitudinal dimension dy×8 of a single expandable AiP module are respectively. A front view of an antenna array formed of four expandable elements AiP is shown in fig. 2. Each TR channel in each beamformer chip 8 is connected to 1 antenna element by internal cabling of the radio frequency multi-layer PCB substrate 7 and performs amplitude and phase control of radio frequency signals of the connected antenna elements. The described embodiments are only some, but not all embodiments of the invention, and other embodiments within the scope of the claims shall be considered to be within the scope of the invention.
The installation steps of the phased array front end architecture based on the scalable AiP are as follows: the method comprises the steps of firstly connecting and fixing the expandable AiP module and the copper column by adopting nylon screws and connecting out a control connecting wire and a radio frequency connecting wire, then installing a plurality of expandable AiP modules on the heat-radiating cold plate 2 by adopting metal screws, connecting the power supply copper column, the radio frequency connecting wire and the control connecting wire with the comprehensive mother board 3 by penetrating through the heat-radiating cold plate, and fixing the comprehensive mother board with the heat-radiating cold plate by adopting metal screws. And splicing the plurality of expandable AiP modules, the heat-dissipating cold plate and the comprehensive mother board into a complete array surface through the steps. The number of scalable AiP modules required to be assembled is determined by the desired array size or channel size. The dimensions of the heat-dissipating cold plate 2 and the integrated motherboard 3 are determined according to the number of scalable AiP modules required in practical applications.
Fig. 3 is a schematic diagram of a scalable AiP module, which includes a rf multi-layer PCB substrate 7, a beamformer chip 8, a thermal pad 9, a rf interface 10, a power interface 11, and a control interface 12.
The radio frequency multi-layer PCB substrate 7 is made by laminating 9 layers of organic materials and comprises 10 layers of metal signal layers, and the board is a conventional low-cost ROGERS 4350B radio frequency board. The rf multilayer PCB substrate laminate structure is shown in fig. 4, and the use of each metal layer is defined as: the parasitic patch layer TOP of the stacked patch antenna is included from TOP to bottom, the radiation patch layer mL1 of the stacked patch antenna, the antenna floor layer mL2, the transition layer mL3, the power supply and control signal layer mL4, the power supply and control signal layer mL5, the upper reference layer mL6 of the strip line, the phase feed network layer mL7 of the strip line and the like, the lower reference layer mL8 of the strip line and the microstrip line, and the device and radio frequency power division network layer BOT.
The parasitic patch layer TOP of the stacked patch antenna within the rf multilayer PCB substrate 7 is shown in fig. 5; the radiation patch layer mL1 of the stacked patch antenna in the radio frequency multilayer PCB substrate 7 is shown in fig. 6; the devices in the rf multilayer PCB substrate 7 and the rf power division network layer BOT and the devices disposed on the rf multilayer PCB substrate 7 are as shown in fig. 7, and the devices disposed on the rf multilayer PCB substrate 7BOT layer include: four beamformer chips 8, a radio frequency interface 10, a power interface 11, a control interface 12, and the necessary resistance and capacitance in various embodiments.
Further, the radio frequency interface 10 adopts a surface mount SSMP connector for providing a transmit radio frequency signal input and a receive radio frequency signal output; the power supply interface 11 adopts a PCB surface bonding pad for providing voltage bias and power input required by the operation of the beam former chip; the control interface 12 adopts an FPC connector for transmitting the transceiving control signal, the channel amplitude control signal and the channel phase control signal. The surface-mounted SSMP connector and the FPC connector can be welded in an SMT mode with mature technology.
Further, the beamformer chip 8 is packaged by LGA based on the sige process, and is soldered with the radio frequency multi-layer PCB substrate 7 by SMT with low cost and mature process. The internal functional block diagram of the beamformer chip 8 adopted in the embodiment is shown in fig. 8, and has 16 TR channels for completing the transmission amplification of the radio frequency signal in the transmission working state, the transmission amplitude control of the 16 channels, the transmission phase control of the 16 channels, and the transmission power distribution of the 16 channels; the method comprises the steps of receiving and amplifying a radio frequency signal in a receiving working state, controlling the receiving amplitude of a 16 channel, controlling the receiving phase of the 16 channel and synthesizing the receiving power of the 16 channel.
Further, as shown in fig. 3, the expandable AiP module 1 includes a thermal pad 9, one surface of the thermal pad 9 is in contact with the beamformer chip, and the other surface is in contact with the heat sink, so as to realize an excellent heat conduction path of the beamformer chip to the heat sink. The heat dissipation cold plate adopts a high heat conductivity coefficient metal material to provide heat dissipation for a plurality of expandable AiP modules and the integrated motherboard.
As shown in fig. 9, the integrated motherboard 3 includes a high-frequency mixed-voltage PCB 13, a power IC14, and a control IC15, and the size and power supply control capability of the integrated motherboard are designed according to the number of the most required scalable AiP modules in practical applications. As shown in fig. 10, which is a schematic diagram of a phased array front end architecture connection based on a scalable AiP and a schematic diagram of an internal function of an integrated motherboard, the diagram describes that the integrated motherboard 3 provides power, control signals, radio frequency signals for four scalable AiP modules 1 and realizes a split synthesis of the radio frequency signals on the integrated motherboard, and meanwhile, three functional modules are provided inside the integrated motherboard: the system comprises a radio frequency synthesis network module, a control signal generation and driving module, a power supply conversion and voltage stabilization module.
In the invention, each expandable AiP module is an active antenna array with independent and complete functional structure, as shown in fig. 11 and 12, an E-plane and H-plane beam pointing scanning simulation direction diagram of an expandable AiP with an antenna scale of 8 x 8 is shown, and as can be seen from the figure, each expandable AiP module can perform independent beam scanning according to an amplitude-phase control signal, and a single expandable AiP module can realize independent power supply, independent amplitude-phase control and independent transceiving control according to application requirements, can perform independent test verification on indexes of each expandable AiP module, and can realize rapid and efficient maintenance by replacing a failed AiP module.
Taking the four scalable AiP modules as an example, the workflow of the scalable AiP-based phased array front end architecture is described as follows:
firstly, an external power supply is input to an integrated motherboard 3, and the integrated motherboard 3 provides voltage bias and power input required by normal operation for four expandable AiP modules 1 after power supply conversion and power supply voltage stabilization;
the comprehensive mother board 3 generates a control signal according to the transmission or reception pattern wave beam required by the system and issues a control instruction to the expandable AiP module 1;
the beam former chip 8 of the expandable AiP module 1 receives the control command and responds to the control command, and the amplitude and the phase of each TR channel are set according to the control command;
further, the antenna array of the scalable AiP module 1 generates a corresponding transmitting pattern or receiving pattern according to the amplitude and phase relationship of each array element.
The specific embodiments described in this application are merely illustrative of the spirit of the invention. Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.
Claims (10)
1. The phased array front-end architecture based on the expandable AiP is characterized by sequentially comprising an expandable AiP module (1), a heat-dissipation cold plate (2) and a comprehensive mother board (3), wherein the expandable AiP module (1) comprises a radio-frequency multi-layer PCB (printed circuit board) (7), a patch array antenna is printed on the surface layer of the radio-frequency multi-layer PCB (7), a beam former chip (8) with a plurality of TR channels is arranged on the bottom layer, and each TR channel of the beam former chip (8) is connected with one antenna unit of the patch array antenna through an internal wiring of the radio-frequency multi-layer PCB (7);
the expandable AiP module (1) realizes radio frequency feed wiring, control transmission wiring and DC power supply wiring through internal wiring of the radio frequency multi-layer PCB substrate (7), and is provided with a corresponding radio frequency interface (10), a control interface (12) and a power supply interface (11) at the bottom layer;
the comprehensive motherboard (3) comprises a radio frequency synthesis network module, a control signal generation and driving module, a power supply conversion and voltage stabilization module and a control signal generation and driving module, wherein the radio frequency synthesis network module is used for providing radio frequency signals, control signals and power supply for the expandable AiP module (1) respectively;
the radio frequency interface (10) is connected to the radio frequency synthesis network module through a radio frequency connecting wire (4); the control interface (12) is connected with the control signal generating and driving module through a control connecting wire (6); the power supply interface (11) is connected with the power supply conversion and voltage stabilization module through a power supply connecting wire.
2. The phased array front end architecture based on scalable AiP of claim 1, wherein the power supply connection wires are power supply copper posts (5), electrically connected and simultaneously serve as a support structure for the scalable AiP module (1).
3. The expandable AiP-based phased array front end architecture of claim 2, wherein the expandable AiP module (1) is expandable by:
the expandable AiP module (1) and the power supply copper column (5) are fixedly connected through nylon screws, and the control connecting wire (6) and the radio frequency connecting wire (4) are connected and connected out;
one or more expandable AiP modules (1) to be expanded are mounted to the heat dissipation cold plate (2) by adopting metal screws;
the power supply copper column (5), the radio frequency connecting wire (4) and the control connecting wire (6) penetrate through the heat dissipation cold plate (2) to be connected with the integrated motherboard (3).
4. A scalable AiP based phased array front end architecture according to any of claims 1-3, characterized in that the bottom layer of the radio frequency multi-layer PCB substrate (7) is provided with a plurality of beamformer chips (8);
and each beam forming device chip (8) is attached to the bottom layer of the radio frequency multi-layer PCB substrate (7) through an SMT process.
5. A phased array front end architecture based on scalable AiP according to any of claims 1-3, wherein said radio frequency interface (10) employs a surface mount SSMP connector for providing transmit radio frequency signal input and receive radio frequency signal output;
the power supply interface (11) adopts a PCB surface bonding pad for providing voltage bias and power input required by the operation of the beam former chip (8);
the control interface (12) adopts an FPC connector and is used for transmitting and receiving control signals, channel amplitude control signals and channel phase control signals.
6. A phased array front end architecture based on scalable AiP as claimed in any of claims 1-3, wherein said scalable AiP module (1) further comprises a thermal pad (9), one side of said thermal pad (9) being in contact with said beamformer chip (8) and the other side being in contact with said heat sink (2).
7. The scalable AiP-based phased array front end architecture of claim 6, wherein the radio frequency multi-layer PCB substrate (7) comprises ten metal signal layers laminated by nine layers of organic material.
8. The expandable AiP-based phased array front end architecture of claim 7, wherein the ten metal signal layers comprise, in order, a parasitic patch layer TOP, a radiating patch layer mL1, an antenna ground layer mL2, a transition layer mL3, a power and control signal 1 layer mL4, a power and control signal 2 layer mL5, a stripline-up reference layer mL6, a stripline-like phase feed network layer mL7, a stripline-down reference ground and microstrip-line reference layer mL8, a device, and a radio frequency power division network layer BOT.
9. The scalable AiP-based phased array front end architecture of claim 8, wherein the radiating antenna elements of the patch array antenna comprise a parasitic patch antenna element (16) disposed at a parasitic patch layer TOP, a radiating patch element (17) disposed at a radiating patch layer mL1, and an antenna floor element (18) disposed at an antenna floor layer mL2;
the antenna feed structure of the patch array antenna is a pseudo-coaxial feed structure consisting of a vertical metallized radio frequency signal hole (19) connected to one end of a radiating antenna element and a reference ground hole (20) connected to an antenna floor element (18).
10. The phased array front end architecture based on scalable AiP of claim 1, wherein the beamformer chip (8) is configured to perform transmit amplification of radio frequency signals in a transmit operating state, transmit amplitude control of multiple channels, transmit phase control of multiple channels, and multiple channel transmit power allocation; the method comprises the steps of receiving and amplifying a radio frequency signal in a receiving working state, controlling the receiving amplitude of multiple channels, controlling the receiving phase of multiple channels and synthesizing the receiving power of multiple channels.
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