CN117637839A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN117637839A
CN117637839A CN202210970507.4A CN202210970507A CN117637839A CN 117637839 A CN117637839 A CN 117637839A CN 202210970507 A CN202210970507 A CN 202210970507A CN 117637839 A CN117637839 A CN 117637839A
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transistor
substrate
epitaxial layer
forming
doped region
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李德斌
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210970507.4A priority Critical patent/CN117637839A/en
Priority to PCT/CN2022/115989 priority patent/WO2024031755A1/en
Publication of CN117637839A publication Critical patent/CN117637839A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, wherein the structure comprises: the transistor comprises a substrate and a transistor arranged on the substrate, wherein a first doping region and a second doping region are arranged in the substrate, the first doping region is used for forming one of a source electrode or a drain electrode of the transistor, and the second doping region is used for forming the other of the source electrode or the drain electrode of the first transistor; the epitaxial layer is arranged on the surface of the substrate where the first doped region is located, and the doping type of the epitaxial layer is the same as that of the first doped region so as to improve the hot carrier effect of the semiconductor device.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The embodiment of the disclosure relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
The semiconductor device size of the integrated circuit is continuously shrinking with the development of the process, the performance of the semiconductor device is continuously improving, the power consumption is continuously reducing, but the reliability problem becomes increasingly serious. The lateral electric field intensity of the channel of the semiconductor device increases with the continuous downsizing of the semiconductor device, and particularly the electric field intensity near the drain electrode is strongest. As the feature size of semiconductor devices is scaled down to submicron levels, hot carrier effects (Hot Carrier Inject) occur near the drain. When the feature size of a semiconductor device is small, a strong electric field can be generated even at a low voltage, and therefore, hot carriers are liable to occur in a small-sized device as well as a large-scale integrated circuit, and some influence due to the hot carriers is called a hot carrier effect.
Since the semiconductor device operates under a very high voltage, the thermal carrier effect can cause degradation of the performance parameters such as threshold voltage or on-resistance of the semiconductor device to different degrees along with the increase of the service time, and the service life of the semiconductor device is seriously affected, so how to reduce the thermal carrier effect becomes one of important subjects for improving the service life of the semiconductor device.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor structure and a method of fabricating the same to improve hot carrier effects of semiconductor devices.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a semiconductor structure, including: the transistor comprises a substrate and a transistor arranged on the substrate, wherein a first doping region and a second doping region are arranged in the substrate, the first doping region is used for forming one of a source electrode or a drain electrode of the transistor, and the second doping region is used for forming the other of the source electrode or the drain electrode of the transistor; the epitaxial layer is arranged on the surface of the substrate where the first doped region is located, and the doping type of the epitaxial layer is the same as that of the first doped region.
In some embodiments, the sum of the doping depth of the first doped region and the height of the epitaxial layer is equal to the doping depth of the second doped region.
In some embodiments, the epitaxial layer has a height of 8nm to 12nm.
In some embodiments, a plurality of isolation structures are disposed in the substrate, and the transistor is disposed between adjacent isolation structures.
In some embodiments, a transistor includes: the epitaxial layer is arranged on the surface of the substrate between the side wall isolation layer and the isolation structure.
In some embodiments, a transistor includes: and the epitaxial layer is arranged on the surface of the substrate between the top isolation layer and the isolation structure.
In some embodiments, a transistor includes: the epitaxial layer is positioned at one end of the fin structure and is arranged around the surface of the fin structure.
In some embodiments, the transistor includes a first transistor and a second transistor sharing a first doped region with the first transistor.
In some embodiments, the gates of the first transistor and the second transistor are electrically connected.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a substrate, and forming a grid structure on the substrate; forming a mask layer, wherein the mask layer covers the top surface of part of the gate structure and covers the substrate surface positioned on the second side of the gate structure, and exposes the substrate surface positioned on the first side of the gate structure, and the first side and the second side are positioned on two opposite sides of the gate structure; forming an epitaxial layer, wherein the epitaxial layer is positioned on the surface of the substrate at the first side; and removing the mask layer, and doping the epitaxial layer and the substrate positioned on the first side and the substrate positioned on the second side simultaneously.
In some embodiments, the process of forming the epitaxial layer includes: and forming an epitaxial layer on the exposed substrate surface through an epitaxial growth process at 800-850 ℃.
In some embodiments, the epitaxial layer is formed to a height in the range of 8nm to 12nm.
In some embodiments, the step of forming the gate structure includes: forming a gate stack over the substrate surface; and forming a side wall isolation layer which is positioned above the surface of the substrate and covers the side wall and the top surface of the gate stack.
In some embodiments, the step of forming the gate structure includes: forming a groove in the substrate, and forming a grid stack layer on the inner wall of the groove; a top isolation layer is formed on the upper surface of the gate stack, and the upper surface of the top isolation layer is flush with the surface of the substrate.
In some embodiments, forming the gate structure further comprises: forming a first gate structure and a second gate structure; forming a mask layer to expose the surface of the substrate between the first gate structure and the second gate structure; forming the epitaxial layer includes forming a common epitaxial layer on the exposed substrate surface.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the first doping region and the second doping region are arranged in the substrate and used for forming a source electrode or a drain electrode of the transistor, and the epitaxial layer is arranged on the surface of the substrate where the first doping region is arranged, so that the first doping region and the epitaxial layer jointly form one of the source electrode or the drain electrode of the transistor, and the second doping region forms the other of the source electrode or the drain electrode of the transistor; the epitaxial layer can reduce the doping depth of the first doping region in the substrate, the doping depth of the first doping region in the substrate is lower than that of the second doping region, the equivalent resistance of a source electrode or a drain electrode formed by the first doping region and the epitaxial layer together can be increased, the overlapping electric field between the source electrode or the drain electrode of the transistor and the grid electrode of the transistor is effectively weakened, meanwhile, the strong electric field region and the large current density region of the transistor are separated, the occurrence of avalanche multiplication effect is reduced, and further the hot carrier effect of the semiconductor device is improved.
In addition, the transistor may include a first transistor and a second transistor, the first transistor and the second transistor sharing a first doped region, the first doped region and the epitaxial layer together constituting one of a source or a drain of the first transistor and constituting one of a source or a drain of the second transistor, the second doped region constituting the other of the source or the drain of the first transistor, and the third doped region constituting the other of the source or the drain of the second transistor to form two parallel transistor structures; the doping depth of the first doping region is smaller than that of the second doping region, and the doping depth of the first doping region is smaller than that of the third doping region, so that for the first transistor and the second transistor, the equivalent resistance of a source electrode or a drain electrode formed by the first doping region and an epitaxial layer together can be increased, the overlapping electric field between the source electrode or the drain electrode of the first transistor and a corresponding grid electrode is weakened, the overlapping electric field between the source electrode or the drain electrode of the second transistor and the corresponding grid electrode is weakened, the strong electric field region and the large current density region corresponding to the first transistor are separated, the strong electric field region and the large current density region corresponding to the second transistor are separated, the occurrence of collision ionization is reduced, and the hot carrier effect in the transistor device with a parallel structure is improved. Meanwhile, the first transistor and the second transistor which are connected in parallel share the first doped region and the epitaxial layer to form a source electrode or a drain electrode, so that the manufacturing process of the semiconductor structure can be reduced, and the manufacturing efficiency of the semiconductor structure can be improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram of another semiconductor structure according to an embodiment of the present disclosure;
fig. 3 to 5 are schematic structural diagrams corresponding to steps of a method for fabricating a semiconductor structure according to another embodiment of the disclosure.
Detailed Description
As known from the background art, the semiconductor device works under a very high voltage, so that the performance parameters such as the threshold voltage or on-resistance of the semiconductor device are degraded to different degrees along with the increase of the service time, and the service life of the semiconductor device is seriously affected, namely, the problem of the hot carrier effect exists in the semiconductor device.
Analysis has found that hot carrier effects typically occur in transistor devices that apply higher drain voltages. Under high drain bias, carriers generally have higher velocity and energy when reaching the drain from the source, and high energy carriers tend to cause impact ionization at the drain and cause avalanche multiplication effect under high current conditions, thereby generating a large number of electron-hole pairs. Avalanche carriers near the channel surface of the transistor device can be injected into the gate dielectric layer of the transistor device with a certain probability to form fixed charges, thereby causing performance degradation of the transistor device. Among the various methods of suppressing the hot carrier effect, reducing the carrier velocity to the drain and spatially separating the strong electric field region and the large current density region are the two most effective methods. Where the high field region is typically located at the overlap of the drain and transistor gate, it is more difficult to separate the high field region from the high current density region in conventional transistor device structures.
An embodiment of the present disclosure provides a semiconductor structure to improve the problem of hot carrier effect in a semiconductor device.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Fig. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, and fig. 2 is a schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure, in which the semiconductor structure provided by the embodiment will be described in detail with reference to the accompanying drawings, specifically as follows:
referring to fig. 1, a semiconductor structure includes: a substrate 100, and a transistor 10 disposed on the substrate 100, wherein the substrate 100 is provided with a first doped region 111 and a second doped region 112, the first doped region 111 is used for forming one of a source or a drain of the transistor 10, and the second doped region 112 is used for forming the other of the source or the drain of the transistor 10; the epitaxial layer 200 is disposed on the surface of the substrate 100 where the first doped region 111 is located, and the doping type of the epitaxial layer 200 is the same as that of the first doped region 111.
By providing the first doped region 111 and the second doped region 112 in the substrate 100 for forming the source or the drain of the transistor 10, and providing the epitaxial layer 200 on the surface of the substrate 100 where the first doped region 111 is located, the first doped region 111 and the epitaxial layer 200 together form one of the source or the drain of the transistor 10, and the second doped region 112 forms the other of the source or the drain of the transistor 10; the epitaxial layer 200 can reduce the doping depth of the first doped region 111 in the substrate 100, and the doping depth of the first doped region 111 in the substrate 100 is lower than that of the second doped region 112, so that the equivalent resistance of the source or the drain formed by the first doped region 111 and the epitaxial layer 200 together can be increased, the overlapping electric field between the source or the drain of the transistor 10 and the gate of the transistor 10 is effectively weakened, and meanwhile, the strong electric field region 103 and the high current density region (not shown) of the transistor 10 are separated, the occurrence of avalanche multiplication effect is reduced, and the hot carrier effect of the semiconductor device is further improved.
In this embodiment, the first doped region 111 and the epitaxial layer 200 together form the drain of the transistor 10, and the second doped region 112 forms the source of the transistor 10. It should be noted that the connection manner of the specific "source" and "drain" defined above is not limited to the embodiments of the present application, and in other embodiments, the connection manner of "drain" instead of "source" and "source" instead of "drain" may be adopted.
For the substrate 100, the material of the substrate 100 may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, indium gallium arsenide, or the like.
In some embodiments, the substrate 100 may have a doping ion therein, in particular, the doping ion may be an N-type ion or a P-type ion, and the N-type ion may be a phosphorus ion, an arsenic ion, or an antimony ion; the P-type ion may be specifically a boron ion, an indium ion, or a boron fluoride ion.
For the first doped region 111 and the second doped region 112, the first doped region 111 and the second doped region 112 have the same type of dopant ions therein, and in this embodiment, the type of dopant ions in the first doped region 111 and the second doped region 112 is different from the type of dopant ions in the substrate 100. Specifically, the doped ions in the first doped region 111 and the second doped region 112 may be N-type ions or P-type ions, and the N-type ions may be phosphorus ions, arsenic ions or antimony ions; the P-type ion may be specifically a boron ion, an indium ion, or a boron fluoride ion. If the doping ion type in the substrate 100 is N-type, the doping ion types in the first doping region 111 and the second doping region 112 are P-type; if the doping ion type in the substrate 100 is P-type, the doping ion types in the first doping region 111 and the second doping region 112 are both N-type.
In other embodiments, the doping type of the first doped region and the second doped region may both be the same as the doping type of the substrate. It is understood that when the doping type of the substrate is P-type, an N-well may be formed in the substrate, and the doping types of the first doping region and the second doping region are P-type and are located in the N-well of the substrate, so as to form a source or a drain of the transistor; alternatively, when the doping type of the substrate is N-type, a P-well may be formed in the substrate, and the doping types of the first doping region and the second doping region are both N-type and located in the P-well of the substrate, so as to form a source or a drain of the transistor.
For the epitaxial layer 200, the doping ion type in the epitaxial layer 200 is the same as the doping ion type in the first doping region 111. Specifically, the doping ion type in the epitaxial layer 200 may be an N-type ion or a P-type ion, and the N-type ion may be a phosphorus ion, an arsenic ion, or an antimony ion; the P-type ion may be specifically a boron ion, an indium ion, or a boron fluoride ion.
In this embodiment, the material of the epitaxial layer 200 is the same as that of the substrate 100; in other embodiments the material of the epitaxial layer 200 may be different from the material of the substrate 100.
In some embodiments, the height of the epitaxial layer is 8nm to 12nm, in particular, the height of the epitaxial layer may be 8nm, 10nm, or 12nm. It will be appreciated that the first doped region 111 and the epitaxial layer 200 together form the source or drain of the transistor 10, and that the epitaxial layer 200 may be used to reduce the doping depth of the first doped region 111 in the substrate 100, and if the height of the epitaxial layer 200 is less than 8nm, the effect of reducing the doping depth of the first doped region 111 may not be achieved; if the height of the epitaxial layer 200 is higher than 12nm, the depth of the doping ions in the first doped region 111 may be too low or even zero, and thus, the height of the epitaxial layer 200 needs to be adjusted within a certain range to set the dimensions of the source or the drain of the different transistors 10, and the height of the epitaxial layer 200 is not specifically limited in this embodiment.
In some embodiments, the sum of the doping depth of the first doped region 111 and the height of the epitaxial layer 200 is equal to the doping depth of the second doped region 112. It can be understood that, in the present embodiment, the first doped region 111 and the epitaxial layer 200 together form the drain electrode of the transistor 10, the second doped region 112 forms the source electrode of the transistor, when the doping depth of the first doped region 111 and the height of the epitaxial layer 200 are equal to the doping depth of the second doped region 112 in the direction perpendicular to the surface of the substrate 100, the doping ion depths of the source electrode and the drain electrode of the transistor 10 are the same, so that the degradation of the structural performance of the transistor 10 caused by the difference of the concentration or the size of the doping ion of the source electrode and the drain electrode of the transistor 10 can be avoided, thereby improving the reliability of the semiconductor structure.
When the doping depth of the source and the drain of the transistor 10 is fixed, the epitaxial layer 200 and the first doped region 111 together form the source or the drain of the transistor 10, the higher the height of the epitaxial layer 200, the greater the ratio of the height of the epitaxial layer 200 to the doping ion depth in the first doped region 111, the shallower the doping ion depth in the first doped region 111, the interface from the top of the first doped region 111 to the substrate 100, that is, the shallower the PN junction, so that the smaller the area through which the current flows, the greater the resistance of the first doped region 111 and the epitaxial layer 200 together form the drain of the transistor 10, so that the electric field in the channel is reduced, the speed of the carriers reaching the first doped region 111 is also reduced, and the use performance of the transistor 10 structure is affected by the excessive resistance and the too small carrier speed; accordingly, the lower the height of the epitaxial layer 200, the smaller the ratio of the depth of the doping ions in the epitaxial layer 200 to the depth of the doping ions in the first doped region 111, the deeper the interface between the top of the first doped region 111 and the substrate 100, i.e. the PN junction, so that the larger the area through which the current flows, the smaller the resistance of the drain electrode of the transistor 10 formed by the first doped region 111 and the epitaxial layer 200 together, the larger the area through which the current flows, the greater the speed at which the carriers reach the first doped region 111, the smaller the resistance and the too high carrier speed can easily cause avalanche multiplication effect, thereby generating hot carrier effect, reducing the service performance of the structure of the transistor 10, and affecting the reliability of the semiconductor structure. Therefore, in the actual process of forming the semiconductor structure, due to the different transistor sizes, the thickness of the epitaxial layer 10 needs to be adjusted accordingly according to the different transistor sizes and the corresponding doping depths of the source electrode and the drain electrode, so that the hot carrier effect of the semiconductor structure is improved while the performance of the semiconductor structure is not affected.
With continued reference to fig. 1, in some embodiments, a plurality of isolation structures 101 may also be disposed in the substrate 100, with the transistor 10 disposed between adjacent isolation structures 101. The isolation structure 101 can isolate adjacent transistors 10, so as to avoid the damage of the transistor 10 structure caused by the mutual communication between the transistors 10, and improve the reliability of the semiconductor structure.
In the present embodiment, the isolation structure is provided as a single-layer structure; in other embodiments, the isolation structure may be provided as a multi-layer structure. For example, the isolation structure may be a silicon Oxide-Nitride-Oxide (ONO) structure, and the silicon Oxide on the surface of the substrate may be used as a buffer layer between the silicon Nitride and the substrate, so as to avoid dislocation between the silicon Nitride and the surface of the substrate due to excessive hardness of the silicon Nitride, and improve the service performance of the semiconductor structure; the silicon nitride has higher density, can have better insulating effect to isolate adjacent transistors, and has higher hardness, can have supporting effect on the isolation structure, so that the isolation structure keeps a good form; the silicon oxide of the outermost layer can fill gaps in the isolation structure, so that the top surface of the isolation structure is flush with the surface of the substrate, and meanwhile, the adjacent transistors can be isolated by good insulating property, the adjacent transistors are prevented from being conducted mutually, and the performance of the semiconductor structure is improved.
Further, the transistor 10 may include: the epitaxial layer 200 is disposed on the surface of the substrate 100 between the sidewall spacer 304 and the spacer 101, and the gate stack 300 and the sidewall spacer 303 are disposed over the substrate 100. By disposing the gate stack 300 and the sidewall spacer 304 on the surface of the substrate 100, a planar transistor structure can be formed, and the fabrication process of the planar transistor structure is simple, thereby improving the fabrication efficiency of the semiconductor structure.
For the gate stack 300, the gate stack 300 may include a gate dielectric layer 301 and a gate conductive layer 302, where the gate dielectric layer 301 is disposed on the surface of the substrate 100, and the gate conductive layer 302 covers the surface of the gate dielectric layer 301, and the gate conductive layer 302 may prevent the gate conductive layer 302 from reacting with the substrate 100 during the subsequent process, so as to cause damage to the semiconductor structure.
For the gate dielectric layer 301, the material of the gate dielectric layer 301 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
For the gate conductive layer 302, the material of the gate conductive layer 302 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.
For the sidewall spacer 303, the material of the sidewall spacer 303 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. The spacer 303 may isolate the gate stacks 300 of different transistors 10 to prevent the gates of the different transistors from being connected to each other, or to prevent the gates of the transistors from being connected to the sources or drains of other transistors from being electrically leaked, thereby preventing the performance of the semiconductor structure from being affected.
In this embodiment, the gate sidewall layer has a single-layer structure; in other embodiments, the gate sidewall layer may be a multi-layer structure. For example, the gate sidewall layer may be a silicon Oxide-Nitride-Oxide (ONO) structure, and the insulating capability of the gate sidewall layer may be increased by forming the ONO structure, so as to further avoid leakage between the gate stack and other semiconductor devices.
In some embodiments, the transistor may include: the epitaxial layer is arranged on the surface of the substrate between the top isolation layer and the isolation structure. By arranging the gate stack inside the substrate, a buried gate structure can be formed, and the buried gate can increase the area of the channel region to improve the current control capability of the transistor, overcome the short channel effect, and further improve the usability of the semiconductor structure.
For the top isolation layer, the material of the top isolation layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. The top isolation layer is positioned on the surface of the gate stack, the top surface is flush with the top surface of the substrate, the gate stack can be buried into the substrate, and meanwhile, the gate stack is isolated from other device structures in the semiconductor structure, so that the gate stack is prevented from being communicated with the gates, the sources, the drains and the like of other devices, and the reliability of the semiconductor structure is improved.
In other embodiments, the transistor may be disposed as a fin structure on the substrate and a gate stack surrounding the fin structure, with the epitaxial layer disposed at one end of the fin structure and disposed around a surface of the fin structure. It can be appreciated that the Fin structure is used to form a Fin Field effect transistor (Fin Field-Effect Transistor, finFET), and the FinFET is mainly different from a planar structure transistor in that the channel region of the FinFET is formed by raised high and thin fins on an insulating substrate, the source and the drain are respectively located at two ends of the channel region, three gates are closely attached to the side wall and the top of the channel region for assisting current control, and the Fin structure increases the area of the gate around the channel region, enhances the control capability of the gate on the channel region, so that the short channel effect in the planar structure transistor can be effectively relieved, the circuit control is greatly improved, the leakage current is reduced, and the gate length of the transistor can be also greatly shortened. The epitaxial layer is located at one end of the fin, that is, the side wall and the top surface of one end of the fin structure are both provided with the epitaxial layer, one end of the fin structure and the corresponding epitaxial layer jointly form the source electrode or the drain electrode of the FinFET, and the transistor with the three plane structures can be understood to be located at the side wall and the top surface of the fin structure, so that the doping depth inside one end of the fin structure is reduced through the epitaxial layer while the channel area of the transistor is increased, and the hot carrier effect of the FinFET is reduced.
In the gate structure provided in the above three embodiments, an epitaxial layer may be disposed in the first doped region to reduce the hot carrier effect of the transistor, and it may be understood that by disposing an epitaxial layer on the surface of the substrate of the source or the drain of the transistor, the depth of doped ions in the substrate of the source or the drain may be reduced, so that the PN junction of the source or the drain of the transistor in the substrate becomes shallow, the area through which current flows is reduced, the resistance of the source or the drain of the transistor is increased, and the electric field in the channel is reduced, so that the speed of carriers reaching the source or the drain is also reduced, and at this time, the area where impact ionization occurs, i.e., the strong electric field region, is separated from the high current density area of the channel near the source or the drain, thereby reducing the avalanche multiplication effect and suppressing the hot carrier effect.
Referring to fig. 2, in some embodiments, the transistor 10 may include a first transistor 11 and a second transistor 12, the second transistor 12 sharing a first doped region 111 with the first transistor 11. That is, the first transistor 11 shares a source or drain with the second transistor 12, then the first doped region 111 and the epitaxial layer 200 together form one of the source or drain of the first transistor 11 and one of the source or drain of the second transistor 12, the second doped region 112 forms the other of the source or drain of the first transistor 11, and the third doped region 113 forms the other of the source or drain of the second transistor 12 to form two parallel transistor structures; the doping depth of the first doped region 111 is smaller than that of the second doped region 112, and the doping depth of the first doped region 111 is smaller than that of the third doped region 113, so that for the first transistor 11 and the second transistor 12, the equivalent resistance of the source or the drain formed by the first doped region 111 and the epitaxial layer 200 together can be increased, the overlapping electric field between the corresponding gates of the first transistor 11 is weakened, the overlapping electric field between the source or the drain of the second transistor 12 and the corresponding gates is weakened, the strong electric field region and the large current density region corresponding to the first transistor 11 are separated, and the strong electric field region and the large current density region corresponding to the second transistor 12 are separated, thereby reducing the occurrence of impact ionization and further improving the hot carrier effect in the transistor device with a parallel structure. Meanwhile, the first transistor 11 and the second transistor 12 connected in parallel share the first doped region 111 and the epitaxial layer 200 to form a source or a drain, so that the manufacturing process of the semiconductor structure can be reduced, and the manufacturing efficiency of the semiconductor structure can be improved.
For the first transistor 11 and the second transistor 12, in the present embodiment, the first transistor 11 includes a first gate stack 310 and a first sidewall spacer 313, and the second transistor 12 includes a second gate stack 320 and a second sidewall spacer 323; wherein the first gate stack 310 and the second gate stack 320 are located on the surface of the substrate 100, and the first sidewall spacer 313 is located on the surface of the substrate 100 and covers the top and sidewalls of the first gate stack 310; the second sidewall spacer 323 is located on the surface of the substrate 100 and covers the top and the sidewall of the second gate stack 320, thereby forming the first transistor 11 with parallel planar structure and the second transistor 12 with planar structure.
In this embodiment, the first transistor and the second transistor are both configured as planar transistor structures, and the first transistor and the second transistor are not limited to the structures; in other embodiments, based on the provision of the gate structure in the above embodiments, the first transistor and the second transistor may each be provided as a buried gate transistor structure or a fin field effect transistor structure. In this embodiment, the structure of the first transistor is the same as that of the second transistor; in other embodiments, the structure of the first transistor may be different from the structure of the second transistor, for example, the first transistor is a planar transistor structure and the second transistor is a buried gate transistor structure.
For the first gate stack 310 and the second gate stack 320, the first gate stack 310 may include a first gate dielectric layer 311 and a first gate conductive layer 312, and the second gate stack 320 may include a second gate dielectric layer 321 and a second gate conductive layer 322; the gate dielectric layer is arranged on the surface of the substrate, and the gate conductive layer covers the surface of the gate dielectric layer, so that the gate conductive layer and the substrate react in the subsequent process to cause the damage of the semiconductor structure.
For the first gate dielectric layer 311 and the second gate dielectric layer 321, the material of the first gate dielectric layer 311 includes at least one of silicon oxide, silicon nitride or silicon oxynitride; the material of the second gate dielectric layer 321 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
For the first gate conductive layer 312 and the second gate conductive layer 322, the material of the first gate conductive layer 312 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten; the material of the second gate conductive layer 322 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.
For the first and second sidewall spacers 313 and 323, the material of the first sidewall spacer 313 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride; the material of the second sidewall spacer 323 includes at least one of silicon oxide, silicon nitride or silicon oxynitride. The first sidewall spacer 313 and the second sidewall spacer 323 can isolate the gates of the respective transistors, thereby avoiding the mutual communication of the gates of the transistors or the leakage of the gates of the transistors, and thus avoiding the performance of the semiconductor structure from being affected.
Note that, in this embodiment, the first side wall isolation layer and the second side wall isolation layer are both provided as a single-layer structure; in other embodiments, the first sidewall spacer and the second gate sidewall spacer may be both provided as a multi-layer structure, for example, may be a silicon Oxide-Nitride-Oxide (ONO) structure, and by forming the ONO structure, the insulating capability of the sidewall spacers may be increased, so that leakage between the gate stack and other semiconductor devices is further avoided, and meanwhile, the silicon Nitride has a higher stress, so that the sidewall spacers may be well supported, and the good form of the transistor gate structure is maintained.
Further, in some embodiments, the gates of the first transistor and the second transistor may be electrically connected. When the drain resistance increases, the drive current of the transistor will decrease with the supply voltage unchanged. To maintain the driving capability, two transistors may be connected in parallel to increase the driving current in such a way as to increase the equivalent width of the transistors. In the structure of two side-by-side raised drain transistors, the side-by-side transistors share one drain, so that the occupied area of the two transistors is reduced. The gates of the two side-by-side transistors are connected in a back-end process to form a transistor in parallel operation. Through parallelly connected first transistor and second transistor, and the grid electricity of first transistor and second transistor is connected, can drive two transistors simultaneously through a grid control end to satisfy the design needs of different semiconductor structures, improve the practicality of semiconductor structure.
According to the semiconductor structure provided by the embodiment of the disclosure, the first doped region and the second doped region are arranged in the substrate to form the source electrode or the drain electrode of the transistor, the epitaxial layer is arranged on the surface of the substrate where the first doped region is located, and the epitaxial layer is used for reducing the doping depth of the first doped region in the substrate, so that the first doped region and the epitaxial layer jointly form one of the source electrode or the drain electrode of the transistor, the second doped region forms the other of the source electrode or the drain electrode of the transistor, and compared with the second doped region, the doping depth of the first doped region in the substrate is lower, so that the equivalent resistance of the source electrode or the drain electrode jointly formed by the first doped region and the epitaxial layer can be increased, the overlapping electric field between the source electrode or the drain electrode of the transistor and the gate electrode of the transistor is effectively reduced, meanwhile, the strong electric field region and the large current density region of the transistor are separated, the occurrence of avalanche multiplication effect is reduced, and the hot carrier effect of the semiconductor device is further improved.
Another embodiment of the present disclosure provides a method for fabricating a semiconductor structure, which can be used to form the semiconductor structure to improve the hot carrier effect of the semiconductor device. It should be noted that, in the same or corresponding parts as those of the above embodiments, reference may be made to the corresponding descriptions of the above embodiments, and detailed descriptions thereof will be omitted.
Fig. 3 to 5 are schematic structural views corresponding to steps of a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure, and the method for manufacturing a semiconductor structure according to the present embodiment will be described in detail with reference to the accompanying drawings, specifically as follows:
referring to fig. 3, a substrate 100 is provided, and a gate structure 310 is formed on the substrate.
For the substrate 100, the material of the substrate 100 may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, indium gallium arsenide, or the like.
In some embodiments, the substrate 100 may have a doping ion therein, in particular, the doping ion may be an N-type ion or a P-type ion, and the N-type ion may be a phosphorus ion, an arsenic ion, or an antimony ion; the P-type ion may be specifically a boron ion, an indium ion, or a boron fluoride ion.
With respect to the gate structure, and with continued reference to fig. 3, in this embodiment, the step of forming the gate structure 310 includes: forming a gate stack 300, the gate stack 300 being located over a surface of the substrate 100; a sidewall spacer 303 is formed, where the sidewall spacer 303 is located above the surface of the substrate 100 and covers the sidewalls and top surface of the gate stack 300. By disposing the gate stack 300 and the sidewall spacer 304 on the surface of the substrate 100, a planar transistor structure can be formed, and the fabrication process of the planar transistor structure is simple, thereby improving the fabrication efficiency of the semiconductor structure.
For the gate stack 300, the gate stack 300 may include a gate dielectric layer 301 and a gate conductive layer 302, where the gate dielectric layer 301 is disposed on the surface of the substrate 100, and the gate conductive layer 302 covers the surface of the gate dielectric layer 301, and the gate conductive layer 302 may prevent the gate conductive layer 302 from reacting with the substrate 100 during the subsequent process, so as to cause damage to the semiconductor structure.
For the gate dielectric layer 301, the material of the gate dielectric layer 301 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
For the gate conductive layer 302, the material of the gate conductive layer 302 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.
For the sidewall spacer 303, the material of the sidewall spacer 303 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. The spacer 303 may isolate the gate stacks 300 of different transistors 10 to prevent the gates of the different transistors from being connected to each other, or to prevent the gates of the transistors from being connected to the sources or drains of other transistors from being electrically leaked, thereby preventing the performance of the semiconductor structure from being affected.
In other embodiments, the step of forming the gate structure includes: forming a groove in the substrate, and forming a grid stack layer on the inner wall of the groove; a top isolation layer is formed on the upper surface of the gate stack, and the upper surface of the top isolation layer is flush with the surface of the substrate. By arranging the gate stack inside the substrate, a buried gate structure can be formed, and the buried gate can increase the area of the channel region to improve the current control capability of the transistor, overcome the short channel effect, and further improve the usability of the semiconductor structure.
For the top isolation layer, the material of the top isolation layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. The top isolation layer is positioned on the surface of the gate stack, the top surface is flush with the top surface of the substrate, the gate stack can be buried into the substrate, and meanwhile, the gate stack is isolated from other device structures in the semiconductor structure, so that the gate stack is prevented from being communicated with the gates, the sources, the drains and the like of other devices, and the reliability of the semiconductor structure is improved.
With continued reference to fig. 3, in some embodiments, after providing the substrate 100, prior to forming the gate structure 310, further comprises: isolation structures 101 are formed with gate structures 310 formed between adjacent isolation structures 101. The isolation structure 101 can be used for isolating adjacent transistors 10, so as to avoid the damage of the transistor 10 structure caused by the mutual communication between the transistors 10 and improve the reliability of the semiconductor structure.
Referring to fig. 4, a mask layer 400 is formed, the mask layer 400 covering a portion of the top surface of the gate structure 310 and covering the surface of the substrate 100 on the second side of the gate structure 310 and exposing the surface of the substrate 100 on the first side of the gate structure 310, the first and second sides being on opposite sides of the gate structure 310; an epitaxial layer 200 is formed, the epitaxial layer 200 being located on the substrate surface on the first side.
For the mask layer 400, the material forming the mask layer 400 includes silicon oxide, silicon nitride, photoresist, or the like.
In some embodiments, the process of forming epitaxial layer 200 includes: the epitaxial layer 200 is formed on the exposed surface of the substrate 100 through an epitaxial growth process at 800-850 ℃.
In some embodiments, before forming the mask layer, forming the gate structure further includes: forming a first gate structure and a second gate structure; forming a mask layer to expose the surface of the substrate between the first gate structure and the second gate structure; forming the epitaxial layer includes forming a common epitaxial layer on the exposed substrate surface. That is, an epitaxial layer is formed on the surface of the substrate between the first gate structure and the second gate structure, so that the first transistor formed by the first gate structure and the second transistor formed by the second gate structure share the source or drain and the epitaxial layer on the surface of the substrate to form two parallel transistor structures; the first transistor and the second transistor which are connected in parallel share the source electrode or the drain electrode and the epitaxial layer, so that the manufacturing process of the semiconductor structure can be reduced, and the manufacturing efficiency of the semiconductor structure can be improved.
Referring to fig. 5, the mask layer 400 is removed, and the epitaxial layer 200 and the substrate 100 on the first side and the substrate 100 on the second side are simultaneously doped to form the first doped region 111 in the substrate 100 on the first side and the second doped region 112 in the substrate 100 on the second side.
Because the epitaxial layer 200 is located on the surface of the substrate 100, the doping depth of the first doped region 111 in the substrate 100 is lower than that of the second doped region 112, so that the equivalent resistance of the source or the drain of the transistor formed by the first doped region 111 and the epitaxial layer 200 together can be increased, the overlapping electric field between the source or the drain of the transistor and the gate of the transistor is effectively weakened, meanwhile, the strong electric field region and the large current density region of the transistor are separated, the occurrence of avalanche multiplication effect is reduced, and the hot carrier effect of the semiconductor device is further improved.
In some embodiments, the epitaxial layer 200 is formed to have a height ranging from 8nm to 12nm, and in particular, the epitaxial layer may have a height of 8nm, 10nm, or 12nm. It will be appreciated that the first doped region 111 and the epitaxial layer 200 together form the source or drain of the transistor 10, and that the epitaxial layer 200 may be used to reduce the doping depth of the first doped region 111 in the substrate 100, and if the height of the epitaxial layer 200 is less than 8nm, the effect of reducing the doping depth of the first doped region 111 may not be achieved; if the height of the epitaxial layer 200 is higher than 12nm, the depth of the doping ions in the first doped region 111 may be too low or even zero, and thus, the height of the epitaxial layer 200 needs to be adjusted within a certain range to set the dimensions of the source or the drain of the different transistors 10, and the height of the epitaxial layer 200 is not specifically limited in this embodiment.
According to the manufacturing method of the semiconductor structure, the first doping region and the second doping region are arranged in the substrate to form the source electrode or the drain electrode of the transistor, the epitaxial layer is arranged on the surface of the substrate where the first doping region is located, and the epitaxial layer is used for reducing the doping depth of the first doping region in the substrate, so that the first doping region and the epitaxial layer jointly form one of the source electrode or the drain electrode of the transistor, the second doping region forms the other of the source electrode or the drain electrode of the transistor, the doping depth of the first doping region in the substrate is lower than that of the second doping region, the equivalent resistance of the source electrode or the drain electrode jointly formed by the first doping region and the epitaxial layer can be increased, the overlapping electric field between the source electrode or the drain electrode of the transistor and the grid electrode of the transistor is effectively reduced, meanwhile, the strong electric field region and the large current density region of the transistor are separated, the occurrence of avalanche multiplication effect is reduced, and the hot carrier effect of the semiconductor device is further improved.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.

Claims (15)

1. A semiconductor structure, comprising:
a substrate, and a transistor on the substrate;
a first doped region and a second doped region are arranged in the substrate, the first doped region is used for forming one of a source electrode or a drain electrode of the transistor, and the second doped region is used for forming the other of the source electrode or the drain electrode of the transistor;
the epitaxial layer is arranged on the surface of the substrate where the first doped region is located, and the doping type of the epitaxial layer is the same as that of the first doped region.
2. The semiconductor structure of claim 1, wherein a sum of a doping depth of the first doped region and a height of the epitaxial layer is equal to a doping depth of the second doped region.
3. The semiconductor structure of claim 1, wherein the epitaxial layer has a height of 8nm to 12nm.
4. The semiconductor structure of claim 1, wherein a plurality of isolation structures are disposed in the substrate, the transistor being disposed between adjacent isolation structures.
5. The semiconductor structure of claim 4, wherein the transistor comprises: and the epitaxial layer is arranged on the surface of the substrate between the side wall isolation layer and the isolation structure.
6. The semiconductor structure of claim 4, wherein the transistor comprises: and the epitaxial layer is arranged on the surface of the substrate between the top isolation layer and the isolation structure.
7. The semiconductor structure of claim 4, wherein the transistor comprises: the epitaxial layer is positioned at one end of the fin structure and is arranged around the surface of the fin structure.
8. The semiconductor structure of claim 1, wherein the transistor comprises a first transistor and a second transistor, the second transistor sharing the first doped region with the first transistor.
9. The semiconductor structure of claim 8, wherein gates of the first transistor and the second transistor are electrically connected.
10. A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming a grid structure on the substrate;
forming a mask layer, wherein the mask layer covers part of the top surface of the gate structure, covers the substrate surface positioned on the second side of the gate structure, exposes the substrate surface positioned on the first side of the gate structure, and the first side and the second side are positioned on two opposite sides of the gate structure;
Forming an epitaxial layer, wherein the epitaxial layer is positioned on the surface of the substrate at the first side;
and removing the mask layer, and simultaneously doping the epitaxial layer and the substrate on the first side and the substrate on the second side.
11. The method of fabricating a semiconductor structure of claim 10, wherein the process of forming the epitaxial layer comprises: and forming the epitaxial layer on the exposed surface of the substrate through an epitaxial growth process at 800-850 ℃.
12. The method of fabricating a semiconductor structure according to claim 10, wherein the epitaxial layer is formed to a height in the range of 8nm to 12nm.
13. The method of fabricating a semiconductor structure of claim 10, wherein forming the gate structure comprises:
forming a gate stack above the substrate surface;
and forming a side wall isolation layer which is positioned above the surface of the substrate and covers the side wall and the top surface of the grid electrode lamination.
14. The method of fabricating a semiconductor structure of claim 10, wherein forming the gate structure comprises:
Forming a groove in the substrate, and forming a grid stack layer on the inner wall of the groove;
and forming a top isolation layer on the upper surface of the gate stack, wherein the upper surface of the top isolation layer is flush with the surface of the substrate.
15. The method of fabricating a semiconductor structure according to any one of claims 10-14, wherein forming the gate structure further comprises: forming a first gate structure and a second gate structure; the forming mask layer exposes the substrate surface between the first gate structure and the second gate structure; the forming an epitaxial layer includes forming a common epitaxial layer on the exposed substrate surface.
CN202210970507.4A 2022-08-12 2022-08-12 Semiconductor structure and manufacturing method thereof Pending CN117637839A (en)

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