CN117637772A

CN117637772A - Array substrate, manufacturing method thereof and display panel

Info

Publication number: CN117637772A
Application number: CN202311703436.2A
Authority: CN
Inventors: 骆官水; 张宁; 唐诗; 谢忠憬
Original assignee: TCL China Star Optoelectronics Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd
Priority date: 2023-12-12
Filing date: 2023-12-12
Publication date: 2024-03-01

Abstract

The application discloses an array substrate, a manufacturing method thereof and a display panel. The manufacturing method of the array substrate comprises the following steps: forming a bridging metal layer and a gate on a substrate; forming a gate insulating layer, a semiconductor layer, a second metal layer and a first protection layer on the substrate, wherein the gate insulating layer covers the gate and the bridging metal layer; forming three-section photoresist with different thicknesses on the first protective layer, and patterning the first protective layer, the second metal layer, the semiconductor layer and the gate insulating layer by taking the three-section photoresist as a mask plate, wherein after patterning, the residual photoresist on the first protective layer; continuing to form a transparent conductive connection layer on the substrate; stripping the rest photoresist to form a conductive connecting layer and a pixel electrode which are arranged at intervals on the transparent conductive connecting layer; the first protective layer and the second metal layer, which are not covered by the conductive connection layer and the pixel electrode, are etched. The method aims at reducing the number of photomasks required for producing the array substrate, simplifying the process flow and reducing the production cost.

Description

Array substrate, manufacturing method thereof and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display panel.

Background

A thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD) has become one of the mainstream displays, in which the manufacturing process of the TFT array substrate has a great influence on the panel manufacturing cost. The TFT array substrate is prepared by forming a film, exposing, developing, etching, etc., and patterning the film layers such as the gate electrode, the gate insulating layer, the semiconductor layer, the source electrode, the drain electrode, and the protective layer of the thin film transistor (Thin Film Transistor, TFT), wherein the patterning process requires multiple exposure of each film layer, and multiple exposure requires multiple photomasks.

The preparation process of the TFT array substrate is subjected to the development process from 7-channel photomask technology to the current 5-channel or 4-channel photomask technology, and the 5-channel or 4-channel photomask technology has become the main stream process for preparing the TFT array substrate. However, the requirements of the display panel market on the productivity and efficiency of the TFT array substrate are becoming more and more strict, and the existing TFT array substrate needs to be prepared by 5 or 4 photomasks, which has a large number of photomasks, thus resulting in complex process flow and high production cost.

Therefore, a new solution is needed to solve the above-mentioned problems.

Disclosure of Invention

The invention aims to provide an array substrate, a manufacturing method thereof and a display panel, and aims to reduce the number of photomasks required for producing the array substrate, simplify the process flow and reduce the production cost.

In order to solve the problems, the technical scheme of the application is as follows:

the application provides a manufacturing method of an array substrate, which comprises the following steps:

forming a first metal layer on a substrate;

patterning the first metal layer to form a bridging metal layer and a grid electrode;

sequentially forming a stacked gate insulating layer, a semiconductor layer, a second metal layer and a first protective layer on the substrate, wherein the gate insulating layer covers the gate and the bridging metal layer;

forming three-section type photoresists with different thicknesses on the first protective layer, and patterning the first protective layer, the second metal layer, the semiconductor layer and the gate insulating layer by taking the three-section type photoresists as mask plates, wherein after patterning, the residual photoresist on the first protective layer;

continuing to form a transparent conductive layer on the substrate;

stripping the residual photoresist to form a conductive connecting layer and a pixel electrode which are arranged at intervals on the transparent conductive layer; and

Etching the first protective layer and the second metal layer which are not covered by the conductive connection layer and the pixel electrode.

In an embodiment of the present application, the forming three-section photoresist with different thicknesses on the first protection layer, and using the three-section photoresist as a mask plate, patterning the first protection layer, the second metal layer, the semiconductor layer and the gate insulating layer, and after patterning, the step of remaining photoresist on the first protection layer includes:

forming the three-section photoresist with different thicknesses on the first protective layer, wherein the three-section photoresist comprises a hollowed-out part, a first photoresist part, a second photoresist part and a third photoresist part, the thickness of the first photoresist part is smaller than that of the second photoresist part, the thickness of the second photoresist part is smaller than that of the third photoresist part, and the hollowed-out part exposes a part of the first protective layer;

etching the part of the first protection layer exposed to the hollowed-out part, and forming the first via hole and the second via hole in the first protection layer;

stripping the first photoresist portion;

forming a second protection layer in the first via hole and the second via hole, wherein the second protection layer covers the second metal layer exposed by the first via hole and the second via hole;

Patterning the first protective layer, the second metal layer, the semiconductor layer and the gate insulating layer exposed through the first photoresist portion with the second photoresist portion, the third photoresist portion and the second protective layer as mask plates; and

and stripping the second protective layer and the second photoresist part.

In an embodiment of the present application, the step of forming the three-stage photoresist with different thicknesses on the first protection layer includes:

forming a photoresist film on the first protective layer;

etching the photoresist film to form two first photoresist parts, a third photoresist part, two second photoresist parts and two hollowed-out parts, wherein the two first photoresist parts are arranged at intervals, the third photoresist part is positioned between the two first photoresist parts, the two second photoresist parts are connected between the third photoresist part and the two first photoresist parts, one of the hollowed-out parts is positioned above the bridging metal layer, and the third photoresist part corresponds to the grid electrode.

In an embodiment of the present application, the step of etching the first protective layer and the second metal layer uncovered by the conductive connection layer and the pixel electrode includes:

Etching the first protective layer uncovered by the conductive connection layer and the pixel electrode to form a first electrode protective layer and a second electrode protective layer which are arranged at intervals; and

and etching the second metal layer exposed through the first electrode protection layer and the second electrode protection layer to form a first electrode and a second electrode which are arranged at intervals.

forming a first metal layer on a substrate;

forming two-section type photoresists with different thicknesses on the first protective layer, and patterning the first protective layer, the second metal layer, the semiconductor layer and the gate insulating layer by taking the two-section type photoresists as mask plates, wherein after patterning, the residual photoresist on the first protective layer;

continuing to form a transparent conductive layer on the substrate;

In an embodiment of the present application, the forming of the two-segment photoresist with different thicknesses on the first protection layer, and patterning the first protection layer, the second metal layer, the semiconductor layer and the gate insulating layer with the two-segment photoresist as a mask, after patterning, the step of remaining photoresist on the first protection layer includes:

forming the two-section photoresist with different thicknesses on the first protective layer, wherein the two-section photoresist comprises a hollowed-out part, a second photoresist part and a third photoresist part, the thickness of the second photoresist part is smaller than that of the third photoresist part, and the hollowed-out part exposes part of the first protective layer;

etching the part of the first protection layer exposed to the hollowed-out part, and forming a first via hole, a second via hole, a third via hole and a fourth via hole in the first protection layer;

patterning the second metal layer, the semiconductor layer and the gate insulating layer exposed through the third via hole and the fourth via hole by using the second photoresist part, the third photoresist part and the second protective layer as mask plates; and

and stripping the second protective layer and the second photoresist part.

In an embodiment of the present application, the step of forming the two-stage photoresist with different thicknesses on the first protective layer includes:

forming a photoresist film on the first protective layer;

and etching the photoresist film to form a third photoresist part corresponding to the grid electrode and two second photoresist parts connected to two sides of the third photoresist part, wherein each second photoresist part is provided with two hollowed-out parts arranged at intervals, and one hollowed-out part is positioned above the bridging metal layer.

The application provides an array substrate, include: a substrate; the first metal layer is arranged on the substrate and comprises a bridging metal layer and a grid electrode which are arranged at intervals; the grid insulation layer is arranged on the substrate and covers the bridging metal layer and the grid electrode; a semiconductor layer provided on the gate insulating layer; a first electrode and a second electrode, the first electrode and the second electrode being arranged on the semiconductor layer at intervals; the first protection layer is arranged on the first electrode and the second electrode, a first via hole is formed in the first protection layer at a position corresponding to the first electrode, and a second via hole is formed in the first protection layer at a position corresponding to the second electrode; the conductive connecting layer is arranged on the first protective layer, connected with the bridging metal layer and connected with the first electrode through the first via hole; and the pixel electrode is arranged on the first protective layer, the pixel electrode is connected with the second electrode through the second via hole, part of the pixel electrode is arranged on the gate insulating layer in an extending mode, and the distance from the part of the pixel electrode arranged on the gate insulating layer to the substrate is equal to the thickness of the first metal layer.

In an embodiment of the present application, the first protection layer includes a first electrode protection layer and a second electrode protection layer, a projection of the first electrode protection layer on the substrate overlaps with a projection of the first electrode on the substrate, and a projection of the second electrode protection layer on the substrate overlaps with a projection of the second electrode on the substrate.

The application provides a display panel, including array substrate, array substrate includes: a substrate; the first metal layer is arranged on the substrate and comprises a bridging metal layer and a grid electrode which are arranged at intervals; the grid insulation layer is arranged on the substrate and covers the bridging metal layer and the grid electrode; a semiconductor layer provided on the gate insulating layer; a first electrode and a second electrode, the first electrode and the second electrode being arranged on the semiconductor layer at intervals; the first protection layer is arranged on the first electrode and the second electrode, a first via hole is formed in the first protection layer at a position corresponding to the first electrode, and a second via hole is formed in the first protection layer at a position corresponding to the second electrode; the conductive connecting layer is arranged on the first protective layer, connected with the bridging metal layer and connected with the first electrode through the first via hole; and the pixel electrode is arranged on the first protective layer, the pixel electrode is connected with the second electrode through the second via hole, part of the pixel electrode is arranged on the gate insulating layer in an extending mode, and the distance from the part of the pixel electrode arranged on the gate insulating layer to the substrate is equal to the thickness of the first metal layer.

In the application, the preparation of the array substrate only needs to use 2 photomasks, and compared with the technical scheme that the existing array substrate manufacturing process needs to use 5 photomasks or 4 photomasks, the manufacturing method of the array substrate greatly reduces the number of photomasks required for producing the array substrate, simplifies the process flow of the array substrate production, improves the production efficiency of the array substrate, and reduces the production cost of the array substrate.

Drawings

FIG. 1 is a first flowchart of a method of fabricating an array substrate of the present application;

FIG. 2 is a schematic diagram of an array substrate of the present application;

FIGS. 3A-3S are schematic diagrams illustrating steps 101-107 in a first flowchart of a method for fabricating an array substrate according to the present application;

FIG. 4 is a second flowchart of a method of fabricating an array substrate of the present application;

fig. 5A to 5R are schematic diagrams illustrating steps 201 to 207 in a second flowchart of the manufacturing method of the array substrate of the present application.

Detailed Description

The meaning of the terms used in the specification and claims corresponds to the meaning commonly understood by one of ordinary skill in the art to which the present application pertains. The terms used in the specification and claims are used merely for convenience of description and understanding of the application and are not intended to limit the application to a narrow interpretation of the specific terms used in the specification and claims.

Referring to fig. 1, the present application proposes a method for manufacturing an array substrate 100, where the method for manufacturing an array substrate 100 includes the following steps:

step 101: a first metal layer 20 is formed on the substrate 10.

Specifically, referring to fig. 3A, the substrate 10 may be a glass substrate 10 or a Polyimide (PI) substrate 10. The material of the first metal layer 20 may be copper, gold, silver, platinum, palladium, iridium, tungsten, molybdenum, or other metals, or brass, cast iron, aluminum tungsten alloy, molybdenum aluminum alloy, or other alloy materials.

After forming the first metal layer 20, step 102 is continuously performed: the first metal layer 20 is patterned to form a bridge metal layer 21 and a gate 22.

Specifically, referring to fig. 3B, a photoresist 85 is first coated on the first metal layer 20; then, as shown in fig. 3C, the photoresist 85 is exposed and developed by using a first preset mask plate, so as to remove the photoresist 85 correspondingly positioned outside the bridge metal layer 21 and the gate 22; then, as shown in fig. 3D, the first metal layer 20 not covered by the photoresist 85 is etched away, and patterning of the first metal layer 20 is completed to form the bridge metal layer 21 and the gate 22. Wherein the bridging metal layer 21 and the gate 22 are disposed on the substrate 10 at intervals. Finally, as shown in fig. 3E, the photoresist 85 covering the bridge metal layer 21 and the gate electrode 22 is removed by development.

In the process of removing the first metal layer 20 uncovered by the photoresist 85 by etching, when the material of the first metal layer 20 is Al (Aluminum), wet etching is used to etch the first metal layer 20, wherein the effective components of the etching solution include nitric acid, phosphoric acid, acetic acid and deionized water. When the material of the first metal layer 20 is Cu (Copper), wet etching is used to etch the first metal layer 20, wherein the effective components of the etching solution include hydrogen peroxide, iminodiacetic acid, 5-aminotetrazole, hydrogen fluoride, and water.

After forming the bridge metal layer 21 and the gate 22, which are disposed at intervals, step 103 is continuously performed: a stacked gate insulating layer 30, a semiconductor layer 40, a second metal layer 50, and a first protective layer 60 are sequentially formed on the substrate 10, wherein the gate insulating layer 30 covers the gate electrode 22 and the bridge metal layer 21.

Referring to fig. 3F, a gate insulating layer 30 is formed on the bridge metal layer 21 and the gate 22, and the gate insulating layer 30 covers the gate 22 and the bridge metal layer 21; forming a semiconductor layer 40 on the gate insulating layer 30; forming a second metal layer 50 on the semiconductor layer 40; a first protective layer 60 is formed on the second metal layer 50.

The material of the gate insulating layer 30 is one of silicon nitride, silicon oxide or silicon oxynitride, or the gate insulating layer 30 is one of a stacked structure of silicon nitride/silicon oxide, silicon nitride/silicon oxide/aluminum oxide, etc. The material of the semiconductor layer 40 may be a crystalline or amorphous oxide semiconductor with high mobility and high stability or other semiconductor types, such as monocrystalline silicon, monocrystalline non-metal or IGZO, IGTO, IGO, IZO, AIZO, ATZO metal oxide with low leakage current, and the semiconductor layer 40 is in ohmic contact with the first electrode 51 and the second electrode 52 (shown in fig. 2) to form a channel. The material of the second metal layer 50 may be copper, gold, silver, platinum, palladium, iridium, tungsten, molybdenum, or other metals, or brass, cast iron, aluminum tungsten alloy, molybdenum aluminum alloy, or other alloy materials. In forming the semiconductor layer 40, ion implantation may be performed on the semiconductor layer 40: heavily doped ion implantation is performed to form a source or drain heavily doped region, specifically, heavily doped ions are implanted under the first electrode 51 and the second electrode 52 to form a source or drain heavily doped region.

After forming the gate insulating layer 30, the semiconductor layer 40, the second metal layer 50, and the first protective layer 60, which are stacked, step 104 is continued: and forming three-section type photoresists with different thicknesses on the first protection layer 60, and patterning the first protection layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulation layer 30 by taking the three-section type photoresists as mask plates, wherein after patterning, the residual photoresist on the first protection layer 60.

Specifically, referring to fig. 3G, a photoresist is coated on the first protective layer 60 to form a photoresist film 80; then, as shown in fig. 3H, exposing and developing the photoresist film 80 by using a second preset mask plate to remove the photoresist and form three-stage photoresist with different thicknesses; then, as shown in fig. 3I, the first protection layer 60 is patterned by using the three-stage photoresist as a mask; then, as shown in fig. 3J to 3L, the second metal layer 50 is patterned; then, as shown in fig. 3M, the semiconductor layer 40 is patterned; then, as shown in fig. 3N, the gate insulating layer 30 is patterned; after patterning, as shown in fig. 3O, a remaining portion of the photoresist is formed on the first protective layer 60 after stripping off a portion of the photoresist.

In the process of patterning the first protection layer 60, dry etching is used to etch the first protection layer 60, wherein the etchant may be one of sulfur hexafluoride gas, nitrogen trifluoride gas and chlorine gas.

As shown in fig. 3I, in the process of patterning the first protective layer 60, a first via hole 61 and a second via hole 62 are formed in the first protective layer 60, the first via hole 61 exposing a portion of the second metal layer 50, the second via hole 62 exposing a portion of the second metal layer 50, the first via hole 61 and the second via hole being spaced apart.

In the process of patterning the first protective layer 60, a third via 63 and a fourth via 64 are formed in the first protective layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30, the third via 63 exposing a portion of the gate insulating layer, the fourth via 64 exposing a portion of the bridge metal layer 21. Wherein the distance from the bottom wall of the third via 63 to the substrate 10 is equal to the thickness of the first metal layer 20.

In the process of patterning the first protective layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30 by using the three-stage photoresist as a mask, multiple ashing steps are performed, and a portion of the three-stage photoresist with smaller thickness is sequentially removed, so that the remaining portion of the photoresist is continuously used as a mask to etch each film.

After patterning the first protection layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30, step 105 is further performed: the formation of the transparent conductive layer 70 on the substrate 10 is continued.

Specifically, referring to fig. 3P, a transparent conductive layer 70 is plated on a surface of the array substrate 100 facing away from the substrate 10, wherein the transparent conductive layer 70 is made of Indium Tin Oxide (ITO), and the indium tin oxide may be transparent indium tin oxide, and the transparent conductive layer 70 may be an indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO) stack.

The portion of the transparent conductive layer 70 covered on the first protective layer 60 is connected to the second metal layer 50 through the first via hole 61 and the second via hole 62, a portion of the transparent conductive layer 70 is disposed on the gate insulating layer 30 through the third via hole 63 in an extending manner, another portion of the transparent conductive layer 70 is connected to the bridge metal layer 21 through the fourth via hole 64, and the remaining portion of the transparent conductive layer 70 is covered on the remaining portion of the photoresist.

After forming transparent conductive layer 70 on substrate 10, step 106 is continued: the remaining photoresist is stripped to form the transparent conductive layer 70 into the conductive connection layer 71 and the pixel electrode 72 which are disposed at intervals.

Specifically, referring to fig. 3Q, the remaining photoresist and a portion of the transparent conductive layer covering the surface of the remaining photoresist are stripped to form a conductive connection layer 71 and a pixel electrode 72 that are disposed at intervals, wherein the conductive connection layer 71 connects the second metal layer 50 and the bridging metal layer 21 through the first via hole 61 and the fourth via hole 64, a first portion of the pixel electrode 72 covers the first protection layer 60, a second portion of the pixel electrode 72 connects the second metal layer 50 through the second via hole 62, and a third portion of the pixel electrode 72 extends to the gate insulating layer 30 through the third via hole 63.

After stripping the remaining portion of the photoresist, step 107 is continued: the first protective layer 60 and the second metal layer 50, which are not covered by the conductive connection layer 71 and the pixel electrode 72, are etched.

Specifically, referring to fig. 3R and 3S, after stripping the remaining portion of the photoresist, a portion of the first protective layer 60 is exposed to the transparent conductive layer 70. Portions of the first protective layer 60 exposed to the transparent conductive layer 70 are etched, and fifth vias 65 are formed in the first protective layer 60 and the second metal layer 50.

In the first aspect, the fifth via hole 65 forms the first protection layer 60 into the first electrode protection layer 66 and the second electrode protection layer 67 that are disposed at intervals, wherein the first via hole 61 is disposed in the first electrode protection layer 66, the second via hole 62 is disposed in the second electrode protection layer 67, and the first electrode protection layer 66 and the second electrode protection layer 67 are disposed on the second metal layer 50 at intervals.

In the second aspect, the fifth via 65 forms the second metal layer 50 into the first electrode 51 and the second electrode 52 which are disposed at intervals, wherein the first electrode protection layer 66 is disposed on the first electrode 51, the first via 61 exposes at least a portion of the first electrode 51, the second electrode protection layer 67 is disposed on the second electrode 52, and the second via 62 exposes at least a portion of the second electrode 52. The conductive connection layer 71 connects the first electrode 51 and the bridging metal layer 21, and the pixel electrode 72 connects the second electrode 52 via the second via hole 62.

The fifth via 65 exposes a portion of the semiconductor layer 40, and in one embodiment, the portion of the semiconductor layer 40 exposed to the fifth via 65 is subjected to an oxidation process, so that an oxide film is formed on the portion of the semiconductor layer 40 exposed to the fifth via 65, thereby improving the stability of the thin film transistor structure. The first electrode 51 serves as one of the source or the drain of the thin film transistor, and the second electrode 52 serves as the other of the source or the drain of the thin film transistor.

In the process of manufacturing the array substrate 100, only two photomasks are used in the steps 102 and 104, compared with the technical scheme that 5 or 4 photomasks are needed in the existing array substrate 100 manufacturing process, the manufacturing method of the array substrate 100 greatly reduces the number of photomasks needed for manufacturing the array substrate 100, simplifies the manufacturing process of the array substrate 100, improves the production efficiency of the array substrate 100, and reduces the manufacturing cost of the array substrate 100.

In an embodiment of the present application, the step of forming three-step photoresist with different thicknesses on the first protection layer 60, and using the three-step photoresist as a mask plate to pattern the first protection layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulation layer 30, and after patterning, the step of remaining photoresist on the first protection layer 60 includes:

Step 104a: the three-stage photoresist with different thicknesses is formed on the first protection layer 60, wherein the three-stage photoresist comprises a hollowed-out portion 81, a first photoresist portion 82, a second photoresist portion 83 and a third photoresist portion 84, the thickness of the first photoresist portion 82 is smaller than that of the second photoresist portion 83, the thickness of the second photoresist portion 83 is smaller than that of the third photoresist portion 84, and the hollowed-out portion 81 exposes a part of the first protection layer 60.

Specifically, referring to fig. 3G and 3H, a photoresist is coated on the first protective layer 60 to form a photoresist film 80.

Exposing and developing the photoresist film 80 by using a second preset mask plate, wherein the second preset mask plate is a three-stage photomask, and the three-stage photomask comprises a shading part, a first transmission part, a second transmission part and a total transmission part, wherein the light transmission quantity of the total transmission part is larger than that of the first transmission part, the light transmission quantity of the first transmission part is larger than that of the second transmission part, and the light transmission quantity of the second transmission part is larger than that of the shading part; the light transmission amount of each part of the photoresist film 80 is adjusted by a three-step photomask, and the photoresist film 80 is exposed and developed to form a hollowed-out part 81, a first photoresist part 82, a second photoresist part 83 and a third photoresist part 84 with different heights. Wherein, the light transmission amount of the total transmission part is maximum, and a hollowed-out part 81 is correspondingly formed on the photoresist film 80; the first transmission part has larger light transmission amount, and a first photoresist 82 with thinner thickness is correspondingly formed on the photoresist film 80; the second transmission part has smaller light transmission amount, and a second photoresist part 83 with thicker thickness is correspondingly formed on the photoresist film 80; the light-shielding portion has the smallest light transmission amount, and the third photoresist portion 84 having the thickest thickness is formed on the photoresist film 80.

After forming the three-step photoresist with different thicknesses on the first protective layer 60, the process continues to step 104b: etching the portion of the first protection layer 60 exposed to the hollowed-out portion 81, and forming the first via hole 61 and the second via hole 62 in the first protection layer 60.

Specifically, referring to fig. 3H and 3I, the photoresist film 80 includes at least two spaced hollowed-out portions 81, portions of the first protection layer 60 exposed to the two spaced hollowed-out portions 81 are etched, and a first via hole 61 and a second via hole 62 are formed in the first protection layer 60, wherein the first via hole 61 and the second via hole 62 expose portions of the second metal layer 50, respectively.

After forming the first via 61 and the second via 62 in the first protection layer 60, the process continues to step 104c: the first photoresist portion 82 is stripped.

Specifically, referring to fig. 3J, the first ashing is performed on the three-stage photoresist to remove the first photoresist portion 82 with a relatively small thickness, so that a portion of the first protective layer 60 covered by the first photoresist portion 82 is exposed to the photoresist film 80. In the first ashing process, the thicknesses of the second photoresist portion 83 and the third photoresist portion 84 are reduced correspondingly, but the thickness of the second photoresist portion 83 is still smaller than the thickness of the third photoresist portion 84.

After the first photoresist portion 82 is stripped, the process continues to step 104d: a second protection layer 90 is formed in the first via 61 and in the second via 62, wherein the second protection layer 90 covers the second metal layer 50 exposed by the first via 61 and the second via 62.

Specifically, referring to fig. 3J, a second protection layer 90 is formed in the first via hole 61 and the second via hole 62 by using an Ink Jet Printing (IJP) technology, the material of the second protection layer 90 may be an organic material, and may be PFA (Polymer Film on Array), and PFA is cured and formed to be transparent, so as to replace the first protection layer 60 to perform an insulation function.

After forming the second protection layer 90 in the first via 61 and the second via 62, the process continues to step 104e: the first protective layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30 exposed through the first photoresist portion 82 are patterned using the second photoresist portion 83, the third photoresist portion 84 and the second protective layer 90 as masks.

Specifically, referring to fig. 3K, 3L, 3M and 3N, portions of the first protection layer 60 exposed to the second photoresist portion 83, the third photoresist portion 84 and the second protection layer 90 are etched, and third vias 63 and fourth vias 64 are formed on the upper surface of the first protection layer 60 at intervals, wherein the third vias 63 and the fourth vias 64 respectively expose a portion of the second metal layer 50, the fourth vias 64 are located on a side of the first vias 61 away from the second vias 62, and the third vias 63 are located on a side of the second vias 62 away from the first vias 61.

Referring to fig. 3L, a portion of the second metal layer 50 exposed to the third via 63 and a portion of the second metal layer 50 exposed to the fourth via 64 are etched such that the third via 63 and the fourth via 64 extend to expose a portion of the semiconductor layer 40, respectively.

Referring to fig. 3M, a portion of the semiconductor layer 40 exposed to the third via 63 and a portion of the semiconductor layer 40 exposed to the fourth via 64 are etched such that the third via 63 and the fourth via 64 extend to expose a portion of the gate insulating layer 30, respectively.

Referring to fig. 3N, the portion of the gate insulating layer 30 exposed by the fourth via 64 is etched so that the fourth via 64 extends to expose at least a portion of the bridge metal layer 21, and the portion of the gate insulating layer 30 exposed by the third via 63 is etched so that the third via 63 extends into the gate insulating layer 30, wherein the distance from the bottom wall of the third via 63 to the substrate 10 is equal to the thickness of the bridge metal layer 21.

Because of the limited precision of the process, in the actual product, the distance from the bottom wall of the third via 63 to the substrate 10 is substantially equal to the thickness of the bridging metal layer 21, where substantially equal means that the ratio of the distance from the bottom wall of the third via 63 to the substrate 10 to the thickness of the bridging metal layer 21 is in the range of 0.9 to 1.1.

After patterning the first protection layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30, step 104f is continued: the second protective layer 90 and the second photoresist portion 83 are stripped.

Specifically, referring to fig. 3O, step 104f1: the second protection layer 90 is etched to remove the second protection layer 90 covering the first via 61 and the second via 62. The second protective layer 90 may be removed by dry etching, or the second protective layer 90 may be removed by ashing treatment.

Step 104f2: the second photoresist portion 83 and the third photoresist portion 84 are subjected to a second ashing, and the second photoresist portion 83 having a thickness smaller than that of the third photoresist portion 84 is removed, so that a portion of the first protective layer 60 covered by the original second photoresist portion 83 is exposed to the photoresist film 80, and the thickness of the third photoresist portion 84 is correspondingly reduced in the second ashing process, but the third photoresist portion 84 is not removed in the second ashing process, and the third photoresist portion 84 has a certain thickness after the second ashing. In addition, when the second protection layer 90 has residues in step 104f1, the second ashing can clean the residues of the second protection layer 90.

In an alternative embodiment, the step 104f1 may be omitted and only the step 104f2 may be performed, and the second passivation layer 90 may be removed together with the second ashing.

Alternatively, in an alternative embodiment, step 104f2 may be omitted and only step 104f1 may be performed, i.e., the second resist portion 83 is stripped at the same time when the ashing process is used to remove the second protective layer 90.

For step 106: and stripping the residual photoresist to enable the transparent conductive layer to form a conductive connecting layer and a pixel electrode which are arranged at intervals.

Specifically, referring to fig. 3O, step 106a: the third photoresist portion 84 is flocked so that a rough structure is formed on the surface of the third photoresist portion 84, the rough structure includes a plurality of nano-pillars, and the height of the nano-pillars is in the range of 100nm to 200 nm. Specifically, the roughness structure of the surface of the third photoresist portion 84 is a suede.

After the flocking process is performed on the third photoresist portion 84, the process continues with step 106b: a transparent conductive layer 70 is formed in the first via 61, the second via 62, the third via 63, the fourth via 64, the upper surface of the first protective layer 60, and the outer surface of the third photoresist portion 84.

Specifically, referring to fig. 3P, the material of the transparent conductive layer 70 includes Indium Tin Oxide (ITO), where the indium tin oxide may be transparent indium tin oxide, and the transparent conductive layer 70 may be a stack of indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO), and during the deposition of the transparent conductive layer 70 on the third photoresist portion 84, since the surface of the third photoresist portion 84 is formed with a rough structure composed of a plurality of nano-pillars, a portion of the transparent conductive layer 70 is attached to the nano-pillars and cannot fall on the surface of the third photoresist portion 84, so that most of the area on the outer surface of the third photoresist portion 84 is not covered by the transparent conductive layer 70, thereby facilitating the stripping of the third photoresist portion 84 and the transparent conductive layer 70 on the surface of the third photoresist portion 84.

After forming the transparent conductive layer 70, step 106c is continued: the third photoresist portion 84 is stripped to form the transparent conductive layer 70 into the conductive connection layer 71 and the pixel electrode 72 which are disposed at intervals.

Wherein the third photoresist portion 84 is the remaining portion of the photoresist above. Specifically, referring to fig. 3Q, since the roughness structure of the surface of the third photoresist portion 84 is formed by a plurality of nano-pillars, a large amount of gaps exist between the plurality of nano-pillars, and the developing solution or the etching solution easily contacts and acts on the third photoresist portion 84 through the gaps, thereby completing the stripping of the third photoresist portion 84 on which the transparent conductive layer 70 has been deposited. After the third photoresist portion 84 is stripped, the first protective layer 60 covered by the original third photoresist portion 84 is exposed to the photoresist film 80, and the transparent conductive layer 70 forms the conductive connection layer 71 and the pixel electrode 72 which are disposed at intervals.

In an embodiment of the present application, the step of forming the three-step photoresist with different thicknesses on the first protective layer 60 includes:

step 104a1: a photoresist film 80 is formed on the first protective layer 60.

Specifically, referring to fig. 3G, a photoresist is coated on the first protective layer 60 to form a photoresist film 80.

After forming the photoresist film 80 on the first protective layer 60, the process continues to step 104a2: the photoresist film 80 is etched to form two first photoresist portions 82 disposed at intervals, a third photoresist portion 84 disposed between the two first photoresist portions 82, two second photoresist portions 83 connected between the third photoresist portions 84 and the two first photoresist portions 82, and the hollowed-out portions 81 in the two second photoresist portions 83, wherein one of the first photoresist portions 82 is disposed above the bridge metal layer 21, and the third photoresist portion 84 corresponds to the gate 22.

Specifically, referring to fig. 3H, a three-stage photomask is disposed on the photoresist film 80, where the three-stage photomask includes a light shielding portion, a first transmission portion, a second transmission portion, and a total transmission portion, the light shielding portion is used for shielding light in a preset wavelength band, the first transmission portion, the second transmission portion, and the total transmission portion are used for transmitting at least part of the light, a light transmission amount of the total transmission portion is greater than a light transmission amount of the first transmission portion, a light transmission amount of the first transmission portion is greater than a light transmission amount of the second transmission portion, and a light transmission amount of the second transmission portion is greater than a light transmission amount of the light shielding portion;

the light transmission amounts of the respective portions of the three-stage photomask are different, and the exposure amounts of the respective portions of the resist film 80 are adjusted by the three-stage photomask.

The photoresist film 80 is exposed and developed, the hollow portion 81 of the first protective layer 60 is formed in an exposed portion of the photoresist film 80 corresponding to the total transmission portion, the first photoresist portion 82 is formed in the photoresist film 80 corresponding to the first transmission portion, the second photoresist portion 83 is formed in the photoresist film 80 corresponding to the second transmission portion, and the third photoresist portion 84 is formed in the photoresist film 80 corresponding to the light shielding portion.

Exposing the photoresist film 80 by light of a preset wave band through the total transmission part, the first transmission part, the second transmission part and the shading part of the three-section photomask; the resist film 80 after the three-stage photomask exposure is developed to form a hollowed-out portion 81, and a first resist portion 82, a second resist portion 83 and a third resist portion 84 having different thicknesses.

In an embodiment of the present application, the step of etching the first protective layer 60 and the second metal layer 50, which are not covered by the conductive connection layer 71 and the pixel electrode 72, includes:

step 107a: the first protective layer 60 not covered by the conductive connection layer 71 and the pixel electrode 72 is etched to form a first electrode protective layer 66 and a second electrode protective layer 67 which are disposed at intervals.

Specifically, referring to fig. 3Q and 3R, the first electrode protection layer 66 is provided with the first via hole 61, and the second electrode protection layer 67 is provided with the second via hole 62.

After etching the first protective layer 60 not covered by the conductive connection layer 71 and the pixel electrode 72, step 107b is continued: the second metal layer 50 exposed through the first electrode protection layer 66 and the second electrode protection layer 67 is etched to form the first electrode 51 and the second electrode 52 which are disposed at intervals.

Specifically, referring to fig. 3S, a fifth via 65 is formed in the first protection layer 60 and the second metal layer 50.

In order to improve the stability of the thin film transistor structure, after the step 107b is completed, ozone may be introduced into the top of the semiconductor layer 40, and an oxide protection layer may be formed above the semiconductor layer 40 after ozone treatment, so as to improve the stability of the thin film transistor structure.

Referring to fig. 4, the present application further provides a method for manufacturing an array substrate, where the method includes the following steps:

step 201: a first metal layer 20 is formed on the substrate 10.

Specifically, referring to fig. 5A, the substrate 10 may be a glass substrate 10 or a Polyimide (PI) substrate 10; the material of the first metal layer 20 may be copper, gold, silver, platinum, palladium, iridium, tungsten, molybdenum, or other metals, or brass, cast iron, aluminum tungsten alloy, molybdenum aluminum alloy, or other alloy materials.

After forming the first metal layer 20, step 202 is continued: the first metal layer 20 is patterned to form a bridge metal layer 21 and a gate 22.

Specifically, referring to fig. 5B, a photoresist 85 is first coated on the first metal layer 20; then, as shown in fig. 5C, the photoresist 85 is exposed and developed by using a first preset mask plate, and the photoresist 85 corresponding to the bridge metal layer 21 and the gate 22 is removed; then, as shown in fig. 5D, the first metal layer 20 not covered by the photoresist 85 is etched away, and patterning of the first metal layer 20 is completed to form the bridge metal layer 21 and the gate 22. Wherein the bridging metal layer 21 and the gate 22 are disposed on the substrate 10 at intervals. Finally, as shown in fig. 5E, the photoresist 85 covering the bridge metal layer 21 and the gate electrode 22 is removed by development.

After forming the bridge metal layer 21 and the gate 22, which are disposed at intervals, step 203 is continuously performed: a stacked gate insulating layer 30, a semiconductor layer 40, a second metal layer 50, and a first protective layer 60 are sequentially formed on the substrate 10, wherein the gate insulating layer 30 covers the gate electrode 22 and the bridge metal layer 21.

Referring to fig. 5F, a gate insulating layer 30 is formed on the bridge metal layer 21 and the gate 22, and the gate insulating layer 30 covers the gate 22 and the bridge metal layer 21; forming a semiconductor layer 40 on the gate insulating layer 30; forming a second metal layer 50 on the semiconductor layer 40; a first protective layer 60 is formed on the second metal layer 50.

The material of the gate insulating layer 30 is one of silicon nitride, silicon oxide or silicon oxynitride, or the gate insulating layer 30 is one of a stacked structure of silicon nitride/silicon oxide, silicon nitride/silicon oxide/aluminum oxide, etc. The material of the semiconductor layer 40 may be a crystalline or amorphous oxide semiconductor with high mobility and high stability or other semiconductor types, such as monocrystalline silicon, monocrystalline non-metal or IGZO, IGTO, IGO, IZO, AIZO, ATZO metal oxide with low leakage current, and the semiconductor layer 40 is in ohmic contact with the first electrode 51 and the second electrode 52 to form a channel. The material of the second metal layer 50 may be copper, gold, silver, platinum, palladium, iridium, tungsten, molybdenum, or other metals, or brass, cast iron, aluminum tungsten alloy, molybdenum aluminum alloy, or other alloy materials. In forming the semiconductor layer 40, ion implantation may be performed on the semiconductor layer 40: heavily doped ion implantation is performed to form a source or drain heavily doped region, specifically, heavily doped ions are implanted under the first electrode 51 and the second electrode 52 to form a source or drain heavily doped region.

After forming the gate insulating layer 30, the semiconductor layer 40, the second metal layer 50, and the first protective layer 60, which are stacked, step 204 is continued: two-stage photoresist with different thicknesses is formed on the first protection layer 60, and the first protection layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30 are patterned by using the two-stage photoresist as a mask, and after patterning, the remaining photoresist on the first protection layer 60.

Specifically, referring to fig. 5G, a photoresist is coated on the first protective layer 60 to form a photoresist film 80; then, as shown in fig. 5H, exposing and developing the photoresist film 80 by using a second preset mask plate to remove the photoresist and form two-stage photoresist with different thicknesses; then, as shown in fig. 5I, the first protection layer 60 is patterned by using the two-stage photoresist as a mask; the second metal layer 50 is then patterned as shown in fig. 5J and 5K; then, as shown in fig. 5L, the semiconductor layer 40 is patterned; then, as shown in fig. 5M, the gate insulating layer 30 is patterned; after patterning, as shown in fig. 5N, a portion of the photoresist is stripped off and a portion of the photoresist remains on the first protective layer 60.

As shown in fig. 5I, in the process of patterning the first protective layer 60, a first via hole 61 and a second via hole 62 are formed in the first protective layer 60, the first via hole 61 exposing a portion of the second metal layer 50, the second via hole 62 exposing a portion of the second metal layer 50, the first via hole 61 and the second via hole being spaced apart.

After patterning the first protection layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30, step 205 is further performed: the formation of the transparent conductive layer 70 on the substrate 10 is continued.

Specifically, referring to fig. 5O, a transparent conductive layer 70 is plated on a surface of the array substrate 100 facing away from the substrate 10, wherein the transparent conductive layer 70 is made of Indium Tin Oxide (ITO), and the indium tin oxide may be transparent indium tin oxide, and the transparent conductive layer 70 may be an indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO) stack.

After forming transparent conductive layer 70 on substrate 10, step 206 is continued: the remaining photoresist is stripped to form the transparent conductive layer 70 into the conductive connection layer 71 and the pixel electrode 72 which are disposed at intervals.

Specifically, referring to fig. 5P, the remaining photoresist and a portion of the transparent conductive layer covering the surface of the remaining photoresist are stripped to form a conductive connection layer 71 and a pixel electrode 72, which are disposed at intervals, wherein the conductive connection layer 71 connects the second metal layer 50 and the bridging metal layer 21 through the first via hole 61 and the fourth via hole 64, a first portion of the pixel electrode 72 covers the first protection layer 60, a second portion of the pixel electrode 72 connects the second metal layer 50 through the second via hole 62, and a third portion of the pixel electrode 72 extends to the gate insulating layer 30 through the third via hole 63.

After stripping the remaining portion of the photoresist, step 207 is continued: the first protective layer 60 and the second metal layer 50, which are not covered by the conductive connection layer 71 and the pixel electrode 72, are etched.

Specifically, referring to fig. 5Q and 5R, after stripping the remaining portion of the photoresist, a portion of the first protective layer 60 is exposed to the transparent conductive layer 70. Portions of the first protective layer 60 exposed to the transparent conductive layer 70 are etched, and fifth vias 65 are formed in the first protective layer 60 and the second metal layer 50.

In the process of manufacturing the array substrate 100, only two photomasks are used in the steps 202 and 204, compared with the technical scheme that 5 or 4 photomasks are needed in the existing array substrate 100 manufacturing process, the manufacturing method of the array substrate 100 greatly reduces the number of photomasks needed for manufacturing the array substrate 100, simplifies the manufacturing process of the array substrate 100, improves the production efficiency of the array substrate 100, and reduces the manufacturing cost of the array substrate 100.

In an embodiment of the present application, the step of forming two-stage photoresist with different thicknesses on the first protection layer 60, and patterning the first protection layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulation layer 30 by using the two-stage photoresist as a mask plate, and after patterning, the remaining photoresist on the first protection layer 60 includes:

Step 204a: the two-stage photoresist with different thicknesses is formed on the first protection layer 60, wherein the two-stage photoresist includes a hollowed-out portion 81, a second photoresist portion 83 and a third photoresist portion 84, the thickness of the second photoresist portion 83 is smaller than the thickness of the third photoresist portion 84, and the hollowed-out portion 81 exposes a portion of the first protection layer 60.

Specifically, referring to fig. 5G and 5H, a photoresist is coated on the first protective layer 60 to form a photoresist film 80.

The second preset mask plate is adopted to expose and develop the photoresist film 80, the second preset mask plate is a two-stage photomask, and the two-stage photomask comprises a shading part, a semi-transmission part and a full-transmission part, wherein the light transmission quantity of the full-transmission part is larger than that of the semi-transmission part, and the light transmission quantity of the semi-transmission part is larger than that of the shading part. The light transmission amount of each part of the photoresist film 80 is adjusted by a two-stage photomask, and the photoresist film 80 is exposed and developed to form a hollowed-out part 81, a second photoresist part 83 and a third photoresist part 84 with different heights. Wherein, the light transmission amount of the total transmission part is maximum, and a hollowed-out part 81 is correspondingly formed on the photoresist film 80; the semi-transmissive portion has a smaller light transmission amount, and a second photoresist portion 83 having a thicker thickness is formed on the photoresist film 80; the light-shielding portion has the smallest light transmission amount, and the third photoresist portion 84 having the thickest thickness is formed on the photoresist film 80.

After forming the two-stage photoresist with different thicknesses on the first protective layer 60, the process continues to step 204b: etching the portion of the first protection layer 60 exposed to the hollowed-out portion 81, and forming a first via hole 61, a second via hole 62, a third via hole 63 and a fourth via hole 64 in the first protection layer 60;

specifically, referring to fig. 5H and 5I, the photoresist film 80 includes at least four spaced hollowed-out portions 81, portions of the first protection layer 60 exposed to the four spaced hollowed-out portions 81 are etched, and first, second, third and fourth vias 61, 62, 63 and 64 are formed on the upper surface of the first protection layer 60, wherein the first, second, third and fourth vias 61, 62, 63 and 64 respectively expose portions of the second metal layer 50, the fourth via 64 is located on a side of the first via 61 away from the second via 62, and the third via 63 is located on a side of the second via 62 away from the first via 61.

After forming the first via 61, the second via 62, the third via 63 and the fourth via 64 on the upper surface of the first protection layer 60, the process continues to step 204c: a second protection layer 90 is formed in the first via 61 and in the second via 62, wherein the second protection layer 90 covers the second metal layer 50 exposed by the first via 61 and the second via 62.

Specifically, referring to fig. 5J, a second protection layer 90 is formed in the first via hole 61 and the second via hole 62 by using an Ink Jet Printing (IJP) technology, the material of the second protection layer 90 may be an organic material, and may be PFA (Polymer Film on Array), and PFA is cured and formed to be transparent, so as to replace the first protection layer 60 to perform an insulation function.

After forming the second protection layer 90 in the first via 61 and the second via 62, the process continues to step 204d: the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30 exposed through the third via hole 63 and the fourth via hole 64 are patterned using the second photoresist portion 83, the third photoresist portion 84 and the second protective layer 90 as masks.

Specifically, referring to fig. 5K, the portion of the second metal layer 50 exposed to the third via 63 and the portion of the second metal layer 50 exposed to the fourth via 64 are etched such that the third via 63 and the fourth via 64 extend to expose a portion of the semiconductor layer 40, respectively.

Referring to fig. 5L, a portion of the semiconductor layer 40 exposed to the third via 63 and a portion of the semiconductor layer 40 exposed to the fourth via 64 are etched such that the third via 63 and the fourth via 64 extend to expose a portion of the gate insulating layer 30, respectively.

Referring to fig. 5M, the portion of the gate insulating layer 30 exposed by the fourth via 64 is etched so that the fourth via 64 extends to expose at least a portion of the bridge metal layer 21, and the portion of the gate insulating layer 30 exposed by the third via 63 is etched so that the third via 63 extends into the gate insulating layer 30, wherein the distance from the bottom wall of the third via 63 to the substrate 10 is equal to the thickness of the bridge metal layer 21.

After patterning the first protection layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30, step 204e is continued: the second protective layer 90 and the second photoresist portion 83 are stripped.

Specifically, referring to fig. 5N, step 204e1: the second protection layer 90 is etched to remove the second protection layer 90 covering the first via 61 and the second via 62. The second protective layer 90 may be removed by dry etching, or the second protective layer 90 may be removed by ashing treatment.

Step 204e2: the second photoresist portion 83 and the third photoresist portion 84 are ashed, and the second photoresist portion 83 having a thickness smaller than that of the third photoresist portion 84 is removed, so that a portion of the first protective layer 60 covered by the original second photoresist portion 83 is exposed to the photoresist film 80, and the thickness of the third photoresist portion 84 is reduced correspondingly during the ashing process, but the third photoresist portion 84 is not removed during the ashing process, and the third photoresist portion 84 has a certain thickness after the ashing. In addition, when the second protection layer 90 has residues in step 204e1, the ashing may clean the residues of the second protection layer 90.

In an alternative embodiment, step 204e1 may be omitted and only 204e2 may be performed, and the ashing may remove the second protection layer 90.

Alternatively, in an alternative embodiment, step 204e2 may be omitted and only step 204e1 may be performed, i.e., the second photoresist portion 83 is stripped at the same time when the ashing process is used to remove the second protection layer 90.

For step 206: and stripping the residual photoresist to enable the transparent conductive layer to form a conductive connecting layer and a pixel electrode which are arranged at intervals.

Specifically, referring to fig. 5N, step 206a: the third photoresist portion 84 is flocked so that a rough structure is formed on the surface of the third photoresist portion 84, the rough structure includes a plurality of nano-pillars, and the height of the nano-pillars is in the range of 100nm to 200 nm. Specifically, the roughness structure of the surface of the third photoresist portion 84 is a suede.

After the flocking process is performed on the third photoresist portion 84, the process continues with step 206b: a transparent conductive layer 70 is formed in the first via 61, the second via 62, the third via 63, the fourth via 64, the upper surface of the first protective layer 60, and the outer surface of the third photoresist portion 84.

Specifically, referring to fig. 5O, the material of the transparent conductive layer 70 includes Indium Tin Oxide (ITO), where the indium tin oxide may be transparent indium tin oxide, and the transparent conductive layer 70 may be a stack of indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO), and during the deposition of the transparent conductive layer 70 on the third photoresist portion 84, since the surface of the third photoresist portion 84 is formed with a rough structure composed of a plurality of nano-pillars, a portion of the transparent conductive layer 70 is attached to the nano-pillars and cannot fall on the surface of the third photoresist portion 84, so that most of the area on the outer surface of the third photoresist portion 84 is not covered by the transparent conductive layer 70, thereby facilitating the stripping of the third photoresist portion 84 and the transparent conductive layer 70 on the surface of the third photoresist portion 84.

After forming the transparent conductive layer 70, step 206c is continued: the third photoresist portion 84 is stripped to form the transparent conductive layer 70 into the conductive connection layer 71 and the pixel electrode 72 which are disposed at intervals.

Wherein the third photoresist portion 84 is the remaining portion of the photoresist above. Specifically, referring to fig. 5P, since the roughness structure of the surface of the third photoresist portion 84 is formed by a plurality of nano-pillars, a large amount of gaps exist between the plurality of nano-pillars, and the developing solution or the etching solution easily contacts and acts on the third photoresist portion 84 through the gaps, thereby completing the stripping of the third photoresist portion 84 on which the transparent conductive layer 70 has been deposited. After the third photoresist portion 84 is stripped, the first protective layer 60 covered by the original third photoresist portion 84 is exposed to the photoresist film 80, and the transparent conductive layer 70 forms the conductive connection layer 71 and the pixel electrode 72 which are disposed at intervals.

In an embodiment of the present application, the step of forming the two-stage photoresist with different thicknesses on the first protective layer 60 includes:

step 204a1: forming a photoresist film 80 on the first protective layer 60;

specifically, referring to fig. 5G, a photoresist is coated on the first protective layer 60 to form a photoresist film 80.

After forming the photoresist film 80 on the first protection layer 60, the process continues to step 204a2: the photoresist film 80 is etched to form a third photoresist portion 84 corresponding to the gate 22 and two second photoresist portions 83 connected to two sides of the third photoresist portion 84, and two hollowed portions 81 disposed at intervals are formed on each second photoresist portion 83, wherein one hollowed portion 81 is located above the bridging metal layer 21.

Specifically, referring to fig. 5H, a second preset mask plate is used to expose and develop the photoresist film 80, where the second preset mask plate is a halftone mask plate, and the halftone mask plate includes a light shielding portion, a semi-transmitting portion, and a fully transmitting portion, where the light transmission amount of the fully transmitting portion is greater than the light transmission amount of the semi-transmitting portion, and the light transmission amount of the semi-transmitting portion is greater than the light transmission amount of the light shielding portion; the light transmission amount of each portion of the resist film 80 is adjusted by a halftone mask, and the resist film 80 is exposed and developed to form a hollowed-out portion 81, and a second resist portion 83 and a third resist portion 84 having a difference in height. Wherein, the light transmission amount of the total transmission part is maximum, and a hollowed-out part 81 is correspondingly formed on the photoresist film 80; the semi-transmissive portion has a larger light transmission amount, and a second photoresist portion 83 having a smaller thickness is formed on the photoresist film 80; the light-shielding portion has the smallest light transmission amount, and the third photoresist portion 84 having the thickest thickness is formed on the photoresist film 80.

The step of etching the photoresist film 80 includes:

a halftone mask plate is arranged on the photoresist film 80, the halftone mask plate comprises a shading part, a semi-transmission part and a total transmission part, the shading part is used for shading light rays of a preset wave band, the semi-transmission part is used for transmitting part of the light rays, the total transmission part is used for total transmission of the light rays, and the light transmission quantity of the total transmission part is larger than that of the semi-transmission part;

The halftone mask plate has different light transmission amounts in each portion, and the halftone mask plate adjusts the exposure amount in each portion of the resist film 80.

The photoresist film 80 is exposed and developed, the hollow portion 81 of the first protective layer 60 is formed in an exposed portion of the photoresist film 80 corresponding to the total transmission portion, the second photoresist portion 83 is formed in the photoresist film 80 corresponding to the semi-transmission portion, and the third photoresist portion 84 is formed in the photoresist film 80 corresponding to the light shielding portion.

Exposing the photoresist film 80 by light of a preset wave band passing through the full transmission part, the semi-transmission part and the light shielding part of the half-tone mask plate; the resist film 80 after the halftone mask exposure is developed to form a hollowed-out portion 81, a second resist portion 83 and a third resist portion 84 having different thicknesses.

Referring to fig. 2, the present application proposes an array substrate 100 including a substrate 10, a first metal layer 20, a gate insulating layer 30, a semiconductor layer 40, first and second electrodes 51 and 52, a first protective layer 60, a conductive connection layer 71, and a pixel electrode 72. The first metal layer 20 is disposed on the substrate 10, and includes a bridge metal layer 21 and a gate 22 disposed at intervals; a gate insulating layer 30 is provided on the substrate 10 and covers the bridge metal layer 21 and the gate 22; a semiconductor layer 40 is provided on the gate insulating layer 30; the first electrode 51 and the second electrode 52 are arranged on the semiconductor layer 40 at intervals; a first protection layer 60 is disposed on the first electrode 51 and the second electrode 52, the first protection layer 60 is provided with a first via hole 61 at a position corresponding to the first electrode 51, and the first protection layer 60 is provided with a second via hole 62 at a position corresponding to the second electrode 52; a conductive connection layer 71 disposed on the first protection layer 60, the conductive connection layer 71 being connected to the bridge metal layer 21 and connected to the first electrode 51 via the first via 61; the pixel electrode 72 is disposed on the first protection layer 60, the pixel electrode 72 is connected with the second electrode 52 through the second via hole 62, a portion of the pixel electrode 72 is disposed on the gate insulating layer 30 in an extending manner, and a distance from the portion of the pixel electrode 72 disposed on the gate insulating layer 30 to the substrate 10 is equal to the thickness of the first metal layer 20.

The array substrate 100 in the application can be manufactured only through 2 photomasks, and compared with the technical scheme that 5 or 4 photomasks are needed in the existing array substrate 100 manufacturing process, the array substrate 100 of the application greatly reduces the number of photomasks needed for producing the array substrate 100, simplifies the process flow of the array substrate 100 production, improves the production efficiency of the array substrate 100, and reduces the production cost of the array substrate 100.

The distance from the portion of the pixel electrode 72 disposed on the gate insulating layer 30 to the substrate 10 is equal to the thickness of the first metal layer 20, where equal means that the lengths of the two are substantially equal, because there is a process error during the production process, and the thicknesses of the two cannot be ensured to be absolutely equal. Wherein substantially equal specifically means that the ratio of the distance from the portion of the pixel electrode 72 disposed on the gate insulating layer 30 to the substrate 10 to the thickness of the first metal layer 20 is in the range of 0.9 to 1.1.

The portion of the pixel electrode 72 disposed on the gate insulating layer 30 is located in the third via hole 63 (shown in fig. 2), and the pixel electrode 72 is connected to the drain electrode of the thin film transistor through the second via hole 62.

Referring to fig. 2, in an embodiment of the present application, the first protective layer 60 includes a first electrode protective layer 66 and a second electrode protective layer 67, where a projection of the first electrode protective layer 66 on the substrate 10 overlaps a projection of the first electrode 51 on the substrate 10, and a projection of the second electrode protective layer 67 on the substrate 10 overlaps a projection of the second electrode 52 on the substrate 10.

Specifically, a first electrode protection layer 66 is disposed on the first electrode 51, the first electrode protection layer 66 is provided with a first via hole 61, the first via hole 61 exposes a portion of the first electrode 51, and one end of the conductive connection layer 71 is connected to the first electrode 51 through the first via hole 61. A second electrode protection layer 67 is disposed on the second electrode 52, the second electrode protection layer 67 is provided with a second via hole 62, the second via hole 62 exposes a portion of the second electrode 52, and the pixel electrode 72 is connected to the second electrode 52 through the second via hole 62; a fifth via 65 is formed between the first electrode protection layer 66 and the first electrode 51 and between the second electrode protection layer 67 and the second electrode 52, and the fifth via 65 exposes a portion of the semiconductor layer 40.

In an embodiment of the present application, a third protection layer is disposed in the fifth via 65, and the third protection layer covers a portion of the semiconductor layer 40 exposed by the fifth via 65.

Since the fifth via 65 exposes a portion of the semiconductor layer 40, the stability of the thin film transistor structure is reduced. In order to improve the stability of the thin film transistor structure, ozone is introduced into the fifth via hole 65, and an oxide film layer is formed on the exposed semiconductor layer 40 through ozone treatment, and the oxide film layer forms the third protection layer, thereby improving the stability of the thin film transistor structure.

The application proposes a display panel, which may be an LCD, may be an LED, may be an OLED, may be an MLED, and includes an array substrate 100.

The foregoing has described in detail the specific embodiments of the present application. The above-described embodiments of the present application are only preferred embodiments of the present application, and many variations and modifications may be made by those of ordinary skill in the art without departing from the spirit of the present application. Such variations and modifications are intended to fall within the scope of the present application as defined in the claims.

Claims

1. The manufacturing method of the array substrate is characterized by comprising the following steps of:

forming a first metal layer on a substrate;

Continuing to form a transparent conductive layer on the substrate;

2. The method for manufacturing an array substrate according to claim 1, wherein the step of forming three-stage photoresist having different thicknesses on the first protective layer, and patterning the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer using the three-stage photoresist as a mask plate, and after patterning, the remaining photoresist on the first protective layer comprises:

stripping the first photoresist portion;

and stripping the second protective layer and the second photoresist part.

3. The method of manufacturing an array substrate of claim 2, wherein the step of forming the three-stage photoresist having different thicknesses on the first protective layer comprises:

forming a photoresist film on the first protective layer;

4. The method of manufacturing an array substrate of claim 1, wherein the step of etching the first protective layer and the second metal layer uncovered by the conductive connection layer and the pixel electrode comprises:

5. The manufacturing method of the array substrate is characterized by comprising the following steps of:

forming a first metal layer on a substrate;

Continuing to form a transparent conductive layer on the substrate;

6. The method of manufacturing an array substrate according to claim 5, wherein the step of forming two-stage photoresist having different thicknesses on the first protective layer, and patterning the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer using the two-stage photoresist as a mask, and after patterning, the remaining photoresist on the first protective layer comprises:

and stripping the second protective layer and the second photoresist part.

7. The method of manufacturing an array substrate according to claim 6, wherein the step of forming the two-stage photoresist having different thicknesses on the first protective layer comprises:

forming a photoresist film on the first protective layer;

8. An array substrate, characterized by comprising:

A substrate;

the first metal layer is arranged on the substrate and comprises a bridging metal layer and a grid electrode which are arranged at intervals;

the grid insulation layer is arranged on the substrate and covers the bridging metal layer and the grid electrode;

a semiconductor layer provided on the gate insulating layer;

a first electrode and a second electrode, the first electrode and the second electrode being arranged on the semiconductor layer at intervals;

the first protection layer is arranged on the first electrode and the second electrode, a first via hole is formed in the first protection layer at a position corresponding to the first electrode, and a second via hole is formed in the first protection layer at a position corresponding to the second electrode;

the conductive connecting layer is arranged on the first protective layer, connected with the bridging metal layer and connected with the first electrode through the first via hole; and

the pixel electrode is arranged on the first protective layer, the pixel electrode is connected with the second electrode through the second via hole, part of the pixel electrode is arranged on the gate insulating layer in an extending mode, and the distance from the part of the pixel electrode arranged on the gate insulating layer to the substrate is equal to the thickness of the first metal layer.

9. The array substrate of claim 8, wherein the first protective layer comprises a first electrode protective layer and a second electrode protective layer, a projection of the first electrode protective layer onto the substrate overlapping a projection of the first electrode onto the substrate, a projection of the second electrode protective layer onto the substrate overlapping a projection of the second electrode onto the substrate.

10. A display panel comprising an array substrate according to any one of claims 8-9.