CN117637698A - Structure and method for detecting performance of packaged chip - Google Patents
Structure and method for detecting performance of packaged chip Download PDFInfo
- Publication number
- CN117637698A CN117637698A CN202210983387.1A CN202210983387A CN117637698A CN 117637698 A CN117637698 A CN 117637698A CN 202210983387 A CN202210983387 A CN 202210983387A CN 117637698 A CN117637698 A CN 117637698A
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- redundant
- die
- unconnected
- loop
- bumps
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 229910000679 solder Inorganic materials 0.000 claims abstract description 63
- 238000012360 testing method Methods 0.000 claims abstract description 36
- 238000004806 packaging method and process Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 238000009736 wetting Methods 0.000 claims description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 239000010953 base metal Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
Abstract
The application discloses a structure and a method for detecting performance of a packaged chip, wherein the structure can comprise: the packaging substrate is provided with at least one unconnected solder ball, each corner area of the die is provided with at least one redundant bump, and the redundant bumps positioned in the corner areas and the at least one unconnected solder ball are connected in series to form a test loop. The method can detect whether the package substrate and the package body of the die are not wetted or not by measuring the resistance value or the capacitance value of the test loop.
Description
Technical Field
The present invention relates generally to the field of chip packaging technologies, and in particular, to a structure and a method for detecting performance of a packaged chip.
Background
According to IPC standards, non-wetting is defined as the inability of molten solder to form a metallic bond with the base metal. This can result in solder being unavailable to the substrate or the solder joints of the PCB pads or components during reflow. As package substrate size and Die (Die) size increase, the Coefficient of Thermal Expansion (CTE) mismatch between the substrate and Die increases, and warpage increases, resulting in increased failure rates of the bump on the Die and the substrate. Moreover, the packaging substrate is thinned, and the warpage of the substrate is further increased, so that the non-wetting failure rate of the bump and the substrate is increased.
In addition, as the wafer node process of the chip evolves, embedded Trace Substrates (ETS) become a new option for shrinking die size and for making the lines on the package substrate denser. Because the pads (BOP) and the lines (BOT) are embedded into the package substrate, the contact area between the bumps and the pads or the lines is reduced, and the non-wetting failure rate of the bumps and the substrate is increased.
Disclosure of Invention
The invention aims to provide a structure and a method for detecting the performance of a packaged chip, which can be used for detecting whether a package body of a package substrate and a die has a non-wetting problem or not.
The application discloses detect structure of encapsulation chip performance, include: the packaging substrate is provided with at least one unconnected tin ball;
and the die is provided with at least one redundant lug in each corner area, and the redundant lugs positioned in the corner areas and the at least one unconnected solder ball are connected in series to form a test loop.
In some embodiments, the redundant bumps located in different corner regions, and between the redundant bumps and the unconnected solder balls, are electrically connected via the substrate wiring.
In some embodiments, the redundant bumps located in the same corner region are electrically connected via a rewiring layer inside the die, and the resistance or capacitance of the loop is tested by the at least one unconnected solder ball to determine whether there are non-wetting redundant bumps between the die and the package substrate.
In one embodiment, an unconnected solder ball is disposed on the package substrate, and the capacitance value of the loop is tested by the unconnected solder ball to determine whether there is an unwetted redundant bump between the die and the package substrate.
In one embodiment, two unconnected solder balls are disposed on the package substrate, and the resistance value of the loop is tested by the two unconnected solder balls to determine whether there are non-wetted redundant bumps between the die and the package substrate.
In one embodiment, the resistance or capacitance value indicates that a non-wetting redundancy bump is present between the die and the package substrate when the loop is open.
In one embodiment, the redistribution layer comprises aluminum and has a thickness of 2 microns to 3 microns.
The application also discloses a method for detecting the performance of the packaged chip, which is applied to a structure for detecting the performance of the packaged chip, and comprises the following steps: the packaging substrate is provided with at least one unconnected tin ball; the die is provided with at least one redundant lug in each corner area, and the redundant lugs in each corner area and the at least one unconnected solder ball are connected in series to form a test loop; the method comprises the following steps:
and testing the resistance value or the capacitance value of the loop through the at least one unconnected solder ball to determine whether a non-wetted redundant bump exists between the die and the packaging substrate.
In one embodiment, after determining that there are no non-wetting redundant bumps between the die and the package substrate, the method further comprises:
disconnecting the rewiring layer connection between the redundant bumps positioned in the same corner area, connecting the redundant bumps positioned in the same corner area through the bottommost metal layer of the metal interconnection layer inside the die, and selectively testing the resistance value or the capacitance value of the loop through the at least one unconnected tin ball to determine whether the bottommost metal layer of the metal interconnection layer has cracks.
In one embodiment, the bottommost metal layer is an ultra-low dielectric layer having a thickness of 0.2 microns to 0.5 microns.
According to the embodiment of the application, the unconnected solder balls on the packaging substrate are connected with the redundant bumps at the corner areas of the die to form a test structure, and whether the packaging body of the packaging substrate and the die is not wetted can be determined only by testing the resistance value or the capacitance value of the structure through the unconnected solder balls. Therefore, the test structure is simple and easy to build, and the test method is simple and convenient, thereby being beneficial to monitoring the production and manufacturing process in real time.
Furthermore, after determining that the package body has no problem of non-wetting, the connection line between the redundant bumps in the same corner region is simply adjusted, namely, the redundant bumps in the same corner region are connected through the bottommost metal layer of the metal interconnection layer in the die, and then the resistance value or the capacitance value of the structure is tested through the non-connected solder balls, so that whether the bottommost metal layer of the metal interconnection layer has cracks can be determined.
Drawings
Fig. 1 shows a schematic diagram of a structure for detecting performance of a packaged chip according to one embodiment of the present application.
Fig. 2 illustrates a cross-sectional schematic view of a metal interconnect layer in a die in accordance with one embodiment of the present application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
The application discloses a structure for detecting performance of a packaged chip, and fig. 1 shows a schematic diagram of the structure for detecting performance of the packaged chip in one embodiment. The structure includes a package substrate (e.g., a printed circuit board PCB) 101 and a die 102. At least one unconnected solder ball 103 is disposed on the package substrate 101. For example, in the example of fig. 1, four unconnected solder balls 103 are disposed on the package substrate 101, and it should be understood that the number of unconnected solder balls 103 disposed on the package substrate 101 in the embodiment of the present application is not limited thereto. Each Corner region (Corner) 107 of the die 102 is provided with at least one redundant (Dummy) bump 104. In the example of fig. 1, each corner region 107 is provided with two redundant bumps 104, and it should be understood that the number of redundant bumps 104 provided in each corner region 107 is not limited thereto. In addition, it should be noted that, in addition to the corner area 107, the embodiment of the present application may further provide the redundant bump 104 in other edge areas of the die or other areas where the non-wetting problem easily occurs, so as to increase the detection probability. It should be appreciated that in addition to the redundant bumps 104 disposed in the corner regions 107, the center region of the die 102 is also provided with bumps that electrically connect the die internal structures. The redundant bumps 104, the at least one unconnected solder balls 103, at each corner region 107 are connected in series to form a test loop.
In one embodiment, the redundant bumps 104 located in different corner regions 107 and between the redundant bumps 104 and the unconnected solder balls 103 are electrically connected via the substrate wiring 105.
In one embodiment, the redundant bumps 104 located in the same corner region 107 are electrically connected via a rewiring layer (Re-distributed layer, RDL) 106 inside the die 102. In one embodiment, the redistribution layer 106 comprises aluminum, and the redistribution layer 106 has a thickness of 2 microns to 3 microns, e.g., the redistribution layer 106 has a thickness of 2.3 microns, 2.5 microns, 2.8 microns, etc.
After the test loop is formed, the resistance or capacitance of the loop is tested by the at least one unconnected solder ball 103 to determine whether there are non-wetted redundant bumps 104 between the die 102 and the package substrate 101.
In one embodiment, an unconnected solder ball 103 is provided on the package substrate 101, and the capacitance of the loop is tested by the unconnected solder ball 103 to determine whether there is an unwetted redundant bump 104 between the die 102 and the package substrate 101. For example, a multimeter can be used to measure the capacitance of the unconnected solder balls 103 to power or ground, and determine that there are non-wetted redundant bumps 104 between the die 102 and the package substrate 101 when the capacitance indicates that the loop is open.
In another embodiment, two or more unconnected solder balls 103 are disposed on the package substrate 101, and only two unconnected solder balls 103 need be included in the loop, and the resistance value of the loop is tested by the two unconnected solder balls 103 to determine whether there are non-wetting redundant bumps 104 between the die 102 and the package substrate 101. For example, the resistance between the two unconnected solder balls 103 may be tested, and when the resistance indicates that the loop is open, it is determined that there are non-wetting redundant bumps 104 between the die 102 and the package substrate 101.
It should be appreciated that before packaging the package substrate 101 with the die 102, the package substrate 101 and the die 102 each complete a respective test, i.e., the package substrate 101, the die 102, and the electrical tests between the package substrate 101 and the die 102 are all passed. The present application may further test whether there are non-wetting redundant bumps 104 between the die 102 and the package substrate 101.
In another embodiment of the present application, a method for detecting performance of a packaged chip is also disclosed, where the method is applied to a structure for detecting performance of a packaged chip, for example, a structure shown in fig. 1. The structure includes a package substrate 101 and a die 102. At least one unconnected solder ball 103 is disposed on the package substrate 101. Each corner region 107 of the die 102 is provided with at least one redundancy bump 104. The redundant bumps 104, the at least one unconnected solder balls 103, at each corner region 107 are connected in series to form a test loop. The redundant bumps 104 located in different corner regions, and between the redundant bumps 104 and the non-104 are electrically connected via a redistribution layer 106 inside the die 102. In one embodiment, the redistribution layer 106 comprises aluminum, and the thickness of the redistribution layer 106 is 2 microns to 3 microns. The method comprises the following steps:
the resistance or capacitance of the loop is selectively tested by the at least one unconnected solder ball 103 to determine whether there are non-wetted redundant bumps between the die and package substrate.
In one embodiment, the selective testing of the resistance or capacitance of the loop by the at least one unconnected solder ball 103 may include the following:
(i) If an unconnected solder ball 103 is disposed on the package substrate 101, testing a capacitance value of the loop through the unconnected solder ball 103, and determining that a redundant bump 104 is not wetted between the die 102 and the package substrate 101 when the capacitance value indicates that the loop is open.
(ii) If two or more unconnected solder balls 103 are disposed on the package substrate 102, the circuit only needs to include two unconnected solder balls 103 therein, the resistance value of the circuit is tested by the two unconnected solder balls 103, and when the resistance value indicates that the circuit is open, it is determined that there is a redundant bump 104 between the die 102 and the package substrate 101.
In one embodiment, after determining that there are no non-wetting redundant bumps between the die 102 and the package substrate 101, the method may further comprise: disconnecting the rewiring layer 106 between the redundant bumps 104 located in the same corner region and connecting the redundant bumps 104 located in the same corner region via the bottommost metal layer of the metal interconnect layer inside the die 101, and selectively testing the resistance value or capacitance value of the loop by the at least one unconnected solder ball 103 to determine whether a crack exists in the bottommost metal layer of the metal interconnect layer. The bottom metal layer is an ultra-low dielectric layer, and the thickness of the ultra-low dielectric layer is 0.2-0.5 micron, for example, the thickness of the ultra-low dielectric layer is 0.21 micron, 0.3 micron, 0.4 micron, 0.46 micron, etc.
Fig. 2 illustrates a cross-sectional schematic view of a metal interconnect layer in a die in one embodiment of the present application. In this embodiment, the metal interconnection layer includes a plurality of metal layers, and a dielectric layer (not shown) is formed between each metal layer. The bottom metal layer 201 adopts an ultra low dielectric layer (ELK), for example, the dielectric constant K is 3.03, and the dielectric constants of the metal layers 202 and 203 on the bottom metal layer 201 are greater than that of the bottom metal layer 201, for example, the dielectric constants K of the metal layers 202 and 203 are 4.2. A re-wiring layer 204 and a passivation layer 205 are formed on the metal layer 203. After determining that there are no non-wetting redundant bumps between the die and the package substrate, disconnecting the rewiring layer 204 between the redundant bumps located in the same corner region, connecting the redundant bumps located in the same corner region via the bottommost metal layer 201 of the metal interconnect layer inside the die, and determining whether a crack exists in the bottommost metal layer of the metal interconnect layer by at least one resistance value or capacitance value of the non-connected solder ball selective test loop. And determining that the bottommost metal layer of the metal interconnection layer has cracks when the resistance value or the capacitance value indicates that the loop is open.
Since the stress of the connection between the die and the package substrate is greatest in the corner region, the problem of non-wetting is most likely to occur in the corner region, therefore, if the non-connected solder balls on the package substrate are connected with the redundant bumps on each corner region on the die, wherein the redundant bumps adjacent to the same corner region are connected by adopting the RDL on the package substrate, the redundant bumps positioned in different corner regions and the redundant bumps and the non-connected solder balls are electrically connected through the substrate wiring, thus a loop for detecting whether the non-wetting redundant bumps exist can be formed.
Since the package substrate has been subjected to the O/S test, the die has also been subjected to the probe O/S test. In this loop, the connection points of the package substrate and the die are redundant bumps. If any one of the redundant bumps is not wetted, an open circuit is formed between the two non-connected solder balls, and the direct current resistance value of the measuring loop can be detected. If there is only one unconnected solder ball, this can be detected by measuring the capacitance between the unconnected solder ball and a reference solder ball, which may be, for example, ground or supply voltage. Of course, in other embodiments of the present application, more redundant bumps may be added to increase the probability of detecting non-wetted bumps.
This test structure allows for the connection between the die and the package substrate to be most stressed at the corner areas, while for large die sizes redundant bumps are needed, while considering that the corner areas of the die and the mechanical support of the PCB would also require the presence of unconnected solder balls, therefore the application does not increase the area of the die as well as the package area.
The test structure only needs to add a section of transmission line on the packaged structure, and as the test structure is mainly used for testing the DC resistance value or the capacitance value, no requirement is required for signal integrity, the added transmission line can be segmented into multiple layers, and the existing package design is basically not changed. The test structure only needs to add a section of RDL wire on the die, and basically has no influence on the design of the die. Meanwhile, structures can be added below the redundant bumps of the die, for example, no RDL connection is used, and ELK layer wire interconnection is used, so that whether the ELK is cracked or not can be detected.
The test process can be detected by adopting a universal meter. Real-time monitoring can be realized in the Surface Mount Technology (SMT) production and manufacture of the die and the PCB, real-time establishment can be realized in the reliability test of the die, and the production and manufacture process can be conveniently monitored.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.
All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
Claims (15)
1. A structure for detecting performance of a packaged chip, comprising:
the packaging substrate is provided with at least one unconnected tin ball;
and the die is provided with at least one redundant lug in each corner area, and the redundant lugs positioned in the corner areas and the at least one unconnected solder ball are connected in series to form a test loop.
2. The structure of claim 1, wherein the redundant bumps located in different corner regions and the redundant bumps and the unconnected solder balls are electrically connected via substrate wiring.
3. The structure of claim 1, wherein redundant bumps located in the same corner region are electrically connected via a rewiring layer inside the die, and the resistance or capacitance of the loop is tested by the at least one unconnected solder ball to determine whether there are non-wetted redundant bumps between the die and the package substrate.
4. A structure for testing performance of a packaged chip according to claim 3, wherein an unconnected solder ball is disposed on the package substrate, and the capacitance of the loop is tested by the unconnected solder ball to determine whether there is a redundant bump between the die and the package substrate.
5. A structure for detecting performance of a packaged chip according to claim 3, wherein two unconnected solder balls are disposed on the package substrate, and the resistance value of the loop is tested by the two unconnected solder balls to determine whether there is a redundant bump between the die and the package substrate.
6. A structure for detecting performance of a packaged chip as defined in claim 3 wherein said resistance or capacitance value indicates that said circuit is open and that there are non-wetted redundant bumps between said die and said package substrate.
7. The structure of claim 3, wherein the redistribution layer comprises aluminum and has a thickness of 2-3 microns.
8. A method of detecting performance of a packaged chip, the method being applied to a structure for detecting performance of a packaged chip, the structure comprising: the packaging substrate is provided with at least one unconnected tin ball; the die is provided with at least one redundant lug in each corner area, and the redundant lugs in each corner area and the at least one unconnected solder ball are connected in series to form a test loop; the method comprises the following steps:
and testing the resistance value or the capacitance value of the loop through the at least one unconnected solder ball to determine whether a non-wetted redundant bump exists between the die and the packaging substrate.
9. The method of claim 8, wherein selectively testing the resistance or capacitance of the loop through the at least one unconnected solder ball comprises:
if the packaging substrate is provided with an unconnected solder ball, testing the capacitance value of the loop through the unconnected solder ball;
and if the packaging substrate is provided with two unconnected solder balls, testing the resistance value of the loop through the two unconnected solder balls.
10. The method of claim 8, wherein when the resistance or capacitance value indicates that the loop is open, determining that an unwetted redundant bump is present between the die and the package substrate.
11. The method of claim 8, wherein the redundant bumps located in different corner regions and the redundant bumps and the unconnected solder balls are electrically connected via substrate routing.
12. The method of claim 8, wherein redundant bumps located in the same corner region are electrically connected via a rewiring layer inside the die.
13. The method of detecting performance of a packaged chip of claim 12, wherein after determining that there are no non-wetting redundant bumps between the die and the package substrate, the method further comprises:
disconnecting the rewiring layer connection between the redundant bumps positioned in the same corner area, connecting the redundant bumps positioned in the same corner area through the bottommost metal layer of the metal interconnection layer inside the die, and selectively testing the resistance value or the capacitance value of the loop through the at least one unconnected tin ball to determine whether the bottommost metal layer of the metal interconnection layer has cracks.
14. The method of claim 12, wherein the redistribution layer comprises aluminum and has a thickness of 2 microns to 3 microns.
15. The method of claim 13, wherein the bottom metal layer is an ultra-low dielectric layer, and the thickness of the ultra-low dielectric layer is 0.2-0.5 microns.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210983387.1A CN117637698A (en) | 2022-08-16 | 2022-08-16 | Structure and method for detecting performance of packaged chip |
| PCT/CN2023/077726 WO2024036910A1 (en) | 2022-08-16 | 2023-02-22 | Structure and method for testing performance of packaged chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210983387.1A CN117637698A (en) | 2022-08-16 | 2022-08-16 | Structure and method for detecting performance of packaged chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117637698A true CN117637698A (en) | 2024-03-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210983387.1A Pending CN117637698A (en) | 2022-08-16 | 2022-08-16 | Structure and method for detecting performance of packaged chip |
Country Status (2)
| Country | Link |
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| CN (1) | CN117637698A (en) |
| WO (1) | WO2024036910A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6166556A (en) * | 1998-05-28 | 2000-12-26 | Motorola, Inc. | Method for testing a semiconductor device and semiconductor device tested thereby |
| KR100519657B1 (en) * | 2003-03-13 | 2005-10-10 | 삼성전자주식회사 | Semiconductor chip having test pads and tape carrier package using thereof |
| KR101783953B1 (en) * | 2010-12-27 | 2017-10-11 | 삼성디스플레이 주식회사 | Display device and method of testing the same |
| US8765497B2 (en) * | 2011-09-02 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging and function tests for package-on-package and system-in-package structures |
-
2022
- 2022-08-16 CN CN202210983387.1A patent/CN117637698A/en active Pending
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2023
- 2023-02-22 WO PCT/CN2023/077726 patent/WO2024036910A1/en unknown
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| WO2024036910A1 (en) | 2024-02-22 |
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