WO2024036910A1

WO2024036910A1 - Structure and method for testing performance of packaged chip

Info

Publication number: WO2024036910A1
Application number: PCT/CN2023/077726
Authority: WO
Inventors: 梅萌; 史刚; 王培春; 李广峰
Original assignee: 澜起电子科技(昆山)有限公司
Priority date: 2022-08-16
Filing date: 2023-02-22
Publication date: 2024-02-22
Also published as: CN117637698A

Abstract

Disclosed in the present application are a structure and method for testing the performance of a packaged chip. The structure may comprise a package substrate and a die, wherein the package substrate is provided with at least one unconnected solder ball; each corner area of the die is provided with at least one redundant bump; and the redundant bumps located in the corner areas are connected in series to the at least one unconnected solder ball to form a test loop. The present application can detect, by means of measuring the resistance value or capacitance value of the test loop, whether the package substrate and a package body of the die have the problem of non-wetting.

Description

Structure and method for testing packaged chip performance

Technical field

The present invention generally relates to the field of chip packaging technology, and in particular to a structure and method for detecting the performance of packaged chips.

Background technique

According to IPC standards, none wetting is defined as the inability of molten solder to form a metallic bond with the base metal. This results in the substrate or PCB pads or component solder joints not being able to capture the solder during the reflow process. As the size of the packaging substrate and the die size increase, the coefficient of thermal expansion (CTE) between the substrate and the die does not match, and the warpage increases, which will lead to non-wetting failure of the bumps on the die and the substrate. rate increases. Not only that, the development of packaging substrates towards thinner and lighter packaging will also lead to further increase in the warpage of the substrate, which will increase the non-wetting failure rate between the bumps and the substrate.

In addition, with the evolution of chip wafer node technology, in order to reduce the die size and make the circuits on the packaging substrate denser, embedded trace substrate (ETS) has become a new option. Since the bonding pads (BOP) and circuits (BOT) are embedded in the package substrate in the ETS substrate, this will reduce the contact area between the bumps and the pads or circuits, and increase the non-wetting failure rate between the bumps and the substrate.

Contents of the invention

The purpose of this application is to provide a structure and method for detecting the performance of packaged chips, which can be used to detect whether there is a problem of non-wetting in the package of the package substrate and the die. The structure is simple, the test method is simple, and the test can be performed at any time. Helps monitor the manufacturing process in real time.

This application discloses a structure for detecting the performance of packaged chips, which includes: a packaging substrate, on which at least one unconnected solder ball is provided;

The die, each corner area of the die is provided with at least one redundant bump, and the redundant bumps located in each corner area and the at least one unconnected solder ball are connected in series to form a test loop. road.

In some embodiments, electrical connections are made between redundant bumps located in different corner areas and between redundant bumps and unconnected solder balls via substrate wiring.

In some embodiments, redundant bumps located in the same corner area are electrically connected via a rewiring layer inside the die, and the resistance value or capacitance value of the loop is tested through the at least one unconnected solder ball, To determine whether there are unwetted redundant bumps between the die and the packaging substrate.

In one embodiment, an unconnected solder ball is provided on the packaging substrate, and the capacitance value of the circuit is tested through the unconnected solder ball to determine whether there is no wetting between the die and the packaging substrate. of redundant bumps.

In one embodiment, two unconnected solder balls are provided on the packaging substrate, and the resistance value of the circuit is tested through the two unconnected solder balls to determine whether there is a gap between the die and the packaging substrate. Uninfiltrated redundant bumps.

In one embodiment, when the resistance value or capacitance value indicates that the loop is an open circuit, it is determined that there are unwetted redundant bumps between the die and the packaging substrate.

In one embodiment, the redistribution layer includes aluminum, and the thickness of the redistribution layer is 2 to 3 microns.

The application also discloses a method for detecting the performance of a packaged chip. The method is applied to a structure for detecting the performance of a packaged chip. The structure includes: a packaging substrate, on which at least one unconnected solder ball is provided; a die, At least one redundant bump is provided in each corner area of the die, and the redundant bumps located in each corner area and the at least one unconnected solder ball are connected in series to form a test loop; the method includes :

Test the resistance value or capacitance value of the loop through the at least one unconnected solder ball to determine whether there are unwetted redundant bumps between the die and the packaging substrate.

In one embodiment, after determining that there are no unwetted redundant bumps between the die and the packaging substrate, the method further includes:

Disconnect the rerouting layers between redundant bumps located in the same corner area and The redundant bumps in a corner area are connected through the lowest metal layer of the metal interconnection layer inside the die, and the resistance value or capacitance value of the loop is selectively tested through the at least one unconnected solder ball. to determine whether there is a crack in the bottom metal layer of the metal interconnection layer.

In one embodiment, the bottom metal layer is an ultra-low dielectric layer, and the thickness of the ultra-low dielectric layer is 0.2 microns to 0.5 microns.

The embodiment of the present application connects the unconnected solder balls on the packaging substrate to the redundant bumps at the corner areas of the die to form a test structure. It is only necessary to test the resistance value or capacitance value of the structure through the unconnected solder balls. It can be determined whether there is no problem of non-wetting in the package between the packaging substrate and the die. Therefore, this test structure is simple and easy to set up, and the test method is simple, which is conducive to real-time monitoring of the production and manufacturing process.

Furthermore, after confirming that the package does not have a problem of non-wetting, this application simply adjusts the connection lines between the redundant bumps in the same corner area, that is, the connection lines between the redundant bumps located in the same corner area are connected via the tube. The bottom metal layer of the metal interconnection layer inside the core is connected, and then the resistance value or capacitance value of the structure is tested through the unconnected solder ball to determine whether there is a crack in the bottom metal layer of the metal interconnection layer.

Description of drawings

Figure 1 shows a schematic diagram of a structure for detecting the performance of a packaged chip according to one embodiment of the present application.

FIG. 2 shows a schematic cross-sectional view of a metal interconnect layer in a die according to an embodiment of the present application.

Detailed ways

In the following description, many technical details are provided to enable readers to better understand this application. However, those of ordinary skill in the art can understand that the technical solution claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

This application discloses a structure for detecting the performance of a packaged chip. Figure 1 shows a schematic diagram of the structure for detecting the performance of a packaged chip in one embodiment. The structure includes a packaging substrate (eg, a printed circuit board PCB) 101 and a die 102 . At least one unconnected solder ball 103 is provided on the packaging substrate 101 . For example, in the example of FIG. 1 , four unconnected solder balls 103 are provided on the packaging substrate 101 . It should be understood that the number of unconnected solder balls 103 provided on the packaging substrate 101 in the embodiment of the present application does not depend on this. is limited. Each corner area (Corner) 107 of the die 102 is provided with at least one redundant (Dummy) bump 104. In the example of FIG. 1 , each corner area 107 is provided with two redundant bumps 104 . It should be understood that the number of redundant bumps 104 provided in each corner area 107 is not limited thereto. In addition, it should be noted that in addition to the corner area 107, embodiments of the present application may also provide redundant bumps 104 in other edge areas of the die or other areas prone to non-wetting problems to increase the detection probability. It should be understood that in addition to the redundant bumps 104 provided in the corner areas 107 of the die 102, the central area of the die 102 is also provided with bumps that electrically connect the internal structure of the die. The redundant bumps 104 located in each corner area 107 and the at least one unconnected solder ball 103 are connected in series to form a test loop.

In one embodiment, the redundant bumps 104 located in different corner areas 107 and the redundant bumps 104 and the unconnected solder balls 103 are electrically connected via the substrate wiring 105 .

In one embodiment, the redundant bumps 104 located in the same corner area 107 are electrically connected via a redistributed layer (RDL) 106 inside the die 102 . In one embodiment, the redistribution layer 106 includes aluminum, and the thickness of the redistribution layer 106 is 2 to 3 microns. For example, the thickness of the redistribution layer 106 is 2.3 microns, 2.5 microns, 2.8 microns, etc.

After the above test loop is formed, the resistance value or capacitance value of the loop is tested through the at least one unconnected solder ball 103 to determine whether there is unwetted redundancy between the die 102 and the packaging substrate 101 Bump 104.

In one embodiment, an unconnected solder ball 103 is provided on the packaging substrate 101, and the capacitance value of the loop is tested through the unconnected solder ball 103 to determine the relationship between the die 102 and the packaging substrate 101. Whether there are uninfiltrated redundant bumps 104. For example, a multimeter can be used to measure the The capacitance value connecting the solder ball 103 to the power supply or ground, and when the capacitance value indicates that the loop is an open circuit, it is determined that there is an unwetted redundant bump 104 between the die 102 and the packaging substrate 101 .

In another embodiment, two or more unconnected solder balls 103 are provided on the packaging substrate 101, and only two of the unconnected solder balls 103 are included in the circuit. Connect the solder balls 103 to test the resistance value of the loop to determine whether there are unwetted redundant bumps 104 between the die 102 and the packaging substrate 101 . For example, the resistance value between the two unconnected solder balls 103 can be tested. When the resistance value indicates that the loop is an open circuit, it is determined that there is unwetted redundancy between the die 102 and the packaging substrate 101 Bump 104.

It should be understood that before the packaging substrate 101 and the die 102 are packaged, the packaging substrate 101 and the die 102 have respectively completed corresponding tests, that is, the packaging substrate 101, the die 102, and the electrical connection between the packaging substrate 101 and the die 102. All sex tests passed. The application can further test whether there are unwetted redundant bumps 104 between the die 102 and the packaging substrate 101 .

Another embodiment of the present application also discloses a method for detecting the performance of a packaged chip. The method is applied to a structure for detecting the performance of a packaged chip, for example, the structure shown in FIG. 1 . The structure includes a packaging substrate 101 and a die 102 . At least one unconnected solder ball 103 is provided on the packaging substrate 101 . Each corner area 107 of the die 102 is provided with at least one redundant bump 104 . The redundant bumps 104 located in each corner area 107 and the at least one unconnected solder ball 103 are connected in series to form a test loop. The redundant bumps 104 located in different corner areas and the redundant bumps 104 and the bumps 104 are electrically connected via the rewiring layer 106 inside the die 102 . In one embodiment, the redistribution layer 106 includes aluminum, and the thickness of the redistribution layer 106 is 2 to 3 microns. The methods include:

The resistance value or capacitance value of the loop is selectively tested through the at least one unconnected solder ball 103 to determine whether there are unwetted redundant bumps between the die and the packaging substrate.

In one embodiment, selectively testing the resistance value or capacitance value of the loop through the at least one unconnected solder ball 103 may include the following situations:

(i) If an unconnected solder ball 103 is provided on the packaging substrate 101, then through the Unconnected solder balls 103 test the capacitance value of the loop. When the capacitance value indicates that the loop is open, it is determined that there are unwetted redundant bumps 104 between the die 102 and the packaging substrate 101 .

(ii) If there are two or more unconnected solder balls 103 on the packaging substrate 102, only two of the unconnected solder balls 103 need to be included in the circuit. 103. Test the resistance value of the loop. When the resistance value indicates that the loop is an open circuit, it is determined that there are unwetted redundant bumps 104 between the die 102 and the packaging substrate 101.

In one embodiment, after determining that there are no unwetted redundant bumps between the die 102 and the packaging substrate 101, the method may further include: disconnecting the redundant bumps located in the same corner area. 104 are connected through the redistribution layer 106, and the redundant bumps 104 located in the same corner area are connected through the lowest metal layer of the metal interconnection layer inside the die 101, and through the at least one unused The solder ball 103 is connected to selectively test the resistance value or capacitance value of the circuit to determine whether there is a crack in the bottom metal layer of the metal interconnection layer. The bottom metal layer is an ultra-low dielectric layer, and the thickness of the ultra-low dielectric layer is 0.2 microns to 0.5 microns. For example, the thickness of the ultra-low dielectric layer is 0.21 microns, 0.3 microns, 0.4 microns, and 0.46 microns. wait.

FIG. 2 shows a schematic cross-sectional view of a metal interconnect layer in a die in an embodiment of the present application. In this embodiment, the metal interconnection layer includes multiple metal layers, and a dielectric layer (not shown in the figure) is formed between each metal layer. Among them, the bottom metal layer 201 adopts an ultra-low dielectric layer (ELK), for example, the dielectric constant K is 3.03, and the dielectric constant of the metal layers 202 and 203 on the bottom metal layer 201 is greater than the bottom metal layer 201, for example , the dielectric constant K of the metal layers 202 and 203 is 4.2. A rewiring layer 204 and a passivation layer 205 are formed on the metal layer 203. After determining that there are no unwetted redundant bumps between the die and the package substrate, disconnect the rewiring layer 204 between the redundant bumps located in the same corner area, and enable the redundant bumps located in the same corner area. The blocks are connected via the bottom metal layer 201 of the metal interconnect layer inside the die, and the resistance value or capacitance value of the loop is selectively tested through at least one unconnected solder ball to determine the bottom metal layer of the metal interconnect layer. Are there any cracks? When the resistance value or capacitance value indicates that the loop is open, it is determined that a crack exists in the bottom metal layer of the metal interconnection layer.

Since the connection between the die and the packaging substrate has the greatest stress in the corner area, the corner area is most prone to non-wetting problems. Therefore, if the unconnected solder balls on the packaging substrate are connected to the redundant bumps on each corner area of the die , where the adjacent redundant bumps located in the same corner area are connected using RDL on the package substrate, and the redundant bumps located in different corner areas, and the redundant bumps and unconnected solder balls are electrically connected via substrate wiring , thus forming a loop for detecting the presence of unwetted redundant bumps.

Since the packaging substrate has already undergone O/S testing, the die has also undergone probe O/S testing. In this loop, the connection point between the package substrate and the die is the redundant bump. If any one of the redundant bumps is not wetted, an open circuit will appear between the two unconnected solder balls, which can be detected by measuring the DC resistance of the loop. If there is only one unconnected solder ball, it can be detected by measuring the capacitance between the unconnected solder ball and a reference solder ball. For example, the reference solder ball can be the ground voltage or the power supply voltage. Of course, in other embodiments of the present application, more redundant bumps can be added to increase the probability of detecting non-wetted bumps.

This test structure takes into account that the connection between the die and the packaging substrate has the greatest stress in the corner area. At the same time, for large-sized die, redundant bumps need to exist, and considering the mechanical support of the corner area of the die and the PCB The presence of unconnected solder balls is also required. Therefore, this application does not increase the area of the die and the packaging area.

This test structure only needs to add a section of transmission line to the packaged structure. Since it is mainly testing the DC resistance value or capacitance value, there is no requirement for signal integrity. The added transmission line can be segmented and multi-layered, and will basically not change the existing packaging design. This test structure only needs to add a section of RDL trace on the die, which basically has no impact on the design of the die. At the same time, some structures can be added under the redundant bumps of the die. For example, instead of RDL connection, ELK layer wire interconnection can be used to detect whether cracks will appear in the ELK.

The testing process only requires a multimeter to detect. Real-time monitoring can be achieved during surface assembly technology (SMT) production and manufacturing of die and PCB, and real-time establishment can also be achieved during reliability testing of die to facilitate monitoring of the production and manufacturing process.

It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these There is no such actual relationship or sequence between entities or operations. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprises a" does not exclude the presence of additional identical elements in a process, method, article, or device that includes the stated element. In the application documents of this patent, if it is mentioned that an act is performed based on a certain element, it means that the act is performed based on at least that element, which includes two situations: performing the act based on that element only, and performing the act based on both that element and Other elements perform this behavior. Expressions such as multiple, multiple times, multiple, etc. include 2, 2 times, 2 kinds, and 2 or more, 2 or more times, or 2 or more kinds.

This specification includes combinations of various embodiments described herein. Individual references to an embodiment (eg, "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated to be mutually exclusive or to those skilled in the art Clearly mutually exclusive, otherwise these embodiments are not mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

All documents mentioned in this specification are considered to be included in the disclosure of this application in their entirety so as to serve as a basis for modifications when necessary. In addition, it should be understood that the above descriptions are only preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification shall be included in the protection scope of one or more embodiments of this specification.

Claims

A structure for testing the performance of packaged chips, which is characterized by including:

A packaging substrate, with at least one unconnected solder ball provided on the packaging substrate;

Each corner area of the die is provided with at least one redundant bump, and the redundant bumps located in each corner area and the at least one unconnected solder ball are connected in series to form a test loop.
The structure for detecting the performance of packaged chips according to claim 1, wherein the redundant bumps located in different corner areas and the redundant bumps and unconnected solder balls are electrically connected through substrate wiring.
The structure for detecting the performance of packaged chips according to claim 1, wherein the redundant bumps located in the same corner area are electrically connected via the rewiring layer inside the die, and the at least one unconnected tin Ball tests the resistance value or capacitance value of the loop to determine whether there are unwetted redundant bumps between the die and the packaging substrate.
The structure for detecting the performance of a packaged chip according to claim 3, characterized in that an unconnected solder ball is provided on the packaging substrate, and the capacitance value of the circuit is tested by the one unconnected solder ball to determine the tube. Whether there are unwetted redundant bumps between the core and the package substrate.
The structure for detecting the performance of a packaged chip according to claim 3, characterized in that two unconnected solder balls are provided on the package substrate, and the resistance value of the circuit is determined by testing the two unconnected solder balls. Whether there are unwetted redundant bumps between the die and the packaging substrate.
The structure for detecting the performance of a packaged chip according to claim 3, characterized in that when the resistance value or the capacitance value indicates that the loop is an open circuit, it is determined that there is unwetted redundancy between the die and the packaging substrate. remaining bumps.
The structure for detecting the performance of packaged chips according to claim 3, wherein the rewiring layer includes aluminum, and the thickness of the rewiring layer is 2 to 3 microns.
A method for detecting the performance of packaged chips, characterized in that the method is applied to a structure for detecting the performance of packaged chips. The structure includes: a packaging substrate, on which at least one unconnected solder ball is provided; a die, At least one redundant bump is provided in each corner area of the die, and the redundant bumps located in each corner area and the at least one unconnected solder ball are connected in series to form a test loop. Road; the method includes:

Test the resistance value or capacitance value of the loop through the at least one unconnected solder ball to determine whether there are unwetted redundant bumps between the die and the packaging substrate.
The method for detecting the performance of packaged chips according to claim 8, characterized in that selectively testing the resistance value or capacitance value of the loop through the at least one unconnected solder ball includes:

If an unconnected solder ball is provided on the packaging substrate, the capacitance value of the circuit is tested through the unconnected solder ball;

If two unconnected solder balls are provided on the packaging substrate, the resistance value of the loop is tested through the two unconnected solder balls.
The method for detecting the performance of a packaged chip according to claim 8, characterized in that when the resistance value or the capacitance value indicates that the loop is an open circuit, it is determined that there is an unwetted layer between the die and the packaging substrate. Redundant bumps.
The method for detecting the performance of a packaged chip according to claim 8, wherein the redundant bumps located in different corner areas and the redundant bumps and unconnected solder balls are electrically connected via substrate wiring.
The method for detecting the performance of a packaged chip according to claim 8, wherein the redundant bumps located in the same corner area are electrically connected via a rewiring layer inside the die.
The method for detecting the performance of a packaged chip according to claim 12, wherein after determining that there are no unwetted redundant bumps between the die and the packaging substrate, the method further includes:

Disconnect the rewiring layer connection between the redundant bumps located in the same corner area, and connect the redundant bumps located in the same corner area via the lowest metal layer of the metal interconnection layer inside the die, And selectively test the resistance value or capacitance value of the loop through the at least one unconnected solder ball to determine whether there is a crack in the bottom metal layer of the metal interconnection layer.
The method for detecting the performance of a packaged chip according to claim 12, wherein the rewiring layer includes aluminum, and the thickness of the rewiring layer is 2 to 3 microns.
The method for detecting packaged chip performance according to claim 13, characterized in that: The bottom metal layer is an ultra-low dielectric layer, and the thickness of the ultra-low dielectric layer is 0.2 microns to 0.5 microns.