JP6230276B2 - Electronic device, inspection method and wiring board - Google Patents

Description

  The present invention relates to an electronic device, an inspection method for an electronic device, and a wiring board.

  There is known an electronic device in which an electronic component such as a semiconductor chip is mounted on a wiring board. Further, a technique for conducting a continuity test on a manufactured electronic device and screening a defective product is known.

JP 2005-347651 A

  In an electronic device, the wiring in the wiring board may be disconnected due to a stress caused by external force or heat during the manufacture or use, or a crack caused by such a stress, resulting in a defect.

According to one aspect of the present invention, a first wiring board and a first electronic component mounted on the first wiring board, wherein the first wiring board includes the first board and the first board. the first wiring which is disposed in a first region facing the first electronic component, and a first terminal and a second terminal disposed at both ends of the first wiring, the first wiring, A first wiring part disposed in an end region of the first region and having a first hole, and an inner region of the first region inside the end region, wherein the first hole is a size. or shape electronic device that having a second wiring portion having a different second hole is provided.

According to another aspect of the present invention, the electronic device includes a first wiring board and a first electronic component mounted on the first wiring board, wherein the first wiring board includes the first board and the first board. on the substrate, a first wiring disposed on the first region facing the first electronic component, and a first terminal and a second terminal disposed at both ends of the first wiring, the first wiring Is disposed in an end region of the first region, and has a first wiring portion having a first hole, and is disposed in an inner region of the first region inside the end region, and the first hole It is a test method for inspecting an electronic device that having a second wiring portion having a second hole size or shape different from the first terminal and the second monitoring said first wiring with a terminal portion Electrically connecting to the first wiring, and supplying the first electrical signal to the first wiring by the monitor unit; The serial monitor inspection method comprising the step of monitoring the first electrical signal is provided.

  According to the disclosed technology, the electronic device can be monitored using a wiring having an opening provided in the wiring board, and a failure of the electronic device due to the disconnection of the wiring board can be prevented in advance, or It becomes possible to discover early.

It is a figure which shows an example of a semiconductor package. It is a figure which shows an example of the semiconductor package which concerns on 1st Embodiment. It is a figure which shows the 1st structural example of the monitor wiring which concerns on 1st Embodiment. It is a figure which shows the 1st modification of the monitor wiring which concerns on 1st Embodiment. It is a figure which shows the 2nd structural example of the monitor wiring which concerns on 1st Embodiment. It is explanatory drawing of the sensitivity of the monitor wiring which concerns on 1st Embodiment. It is a figure which shows the example of arrangement | positioning of the monitor wiring which concerns on 1st Embodiment. It is a figure which shows the 2nd modification of the monitor wiring which concerns on 1st Embodiment. It is a figure which shows the 3rd modification of the monitor wiring which concerns on 1st Embodiment. It is a figure which shows the structural example of a monitor part. It is a figure which shows an example of the semiconductor package which provided the monitor part. It is a figure which shows an example of the electronic device which provided the monitor part. It is a figure which shows another example of arrangement | positioning of the monitor wiring which concerns on 1st Embodiment. It is a figure which shows the 1st structural example of the monitor wiring which concerns on 2nd Embodiment. It is explanatory drawing of the stress direction and stress concentration of the monitor wiring of the 1st structural example which concerns on 2nd Embodiment. It is a figure which shows the example of arrangement | positioning of the monitor wiring which concerns on 2nd Embodiment. It is a figure which shows the 2nd structural example of the monitor wiring which concerns on 2nd Embodiment. It is explanatory drawing of the stress direction and stress concentration of the monitor wiring of the 2nd structural example which concerns on 2nd Embodiment. It is a figure which shows the structural example of the monitor wiring which concerns on 3rd Embodiment. It is a figure which shows an example of the semiconductor package which concerns on 4th Embodiment. It is FIG. (1) which shows an example of the package substrate manufacturing method which concerns on 5th Embodiment. It is FIG. (2) which shows an example of the package substrate manufacturing method which concerns on 5th Embodiment. It is a figure which shows the 1st structural example of the electronic device which concerns on 6th Embodiment. It is a figure which shows the 2nd structural example of the electronic device which concerns on 6th Embodiment. It is a figure which shows the 3rd structural example of the electronic device which concerns on 6th Embodiment.

First, taking an example of a semiconductor device (semiconductor package) as an electronic device, an example of a defect that occurs will be described.
FIG. 1 is a diagram illustrating an example of a semiconductor package. FIG. 1A is a schematic plan view of a principal part of an example of a semiconductor package seen through, and FIG. 1B is a schematic cross-sectional view taken along line L1-L1 of FIG.

  1A and 1B illustrate a semiconductor package 1 in which a semiconductor chip (semiconductor element) 20 is mounted on a package substrate (wiring substrate) 10 as an example of an electronic device. FIG. 1A shows a configuration example of a corner portion (corner portion) of the semiconductor package 1.

  As shown in FIG. 1B, the package substrate 10 includes a substrate 11 and a conductive portion 12 provided on the substrate 11. The substrate 11 includes a core substrate and an insulating layer provided thereon. The conductive portion 12 includes wiring and vias. Of the conductive portion 12, a protective film 13 such as a solder resist is formed on the uppermost wiring 12 a provided on the substrate 11, except for a portion connected to the semiconductor chip 20 (terminals 12 b arranged vertically and horizontally). Is provided.

  As shown in FIG. 1B, the semiconductor chip 20 has terminals 21 arranged vertically and horizontally corresponding to the terminals 12 b of the package substrate 10. The semiconductor chip 20 is disposed such that the terminal 21 is disposed on the side where the terminal 21 is disposed toward the surface 12b of the package substrate 10, and the corresponding terminal 21 and the terminal 12 b are electrically connected using bumps 30 such as solder. It is connected. That is, the semiconductor chip 20 is flip-chip connected to the package substrate 10.

An underfill resin 40 is filled between the semiconductor chip 20 connected using the bumps 30 and the package substrate 10 as shown in FIG.
In the semiconductor package 1 as described above, a difference in thermal expansion coefficient exists between the package substrate 10 and the semiconductor chip 20 due to a difference in materials used for the package substrate 10 and the semiconductor chip 20. In such a semiconductor package 1, heat (heat of the external environment, heat generated by the operation of the semiconductor chip 20, etc.) is applied at the time of use, and the heat is cooled so that thermal expansion and contraction are achieved. And cracks may be formed due to the difference in thermal expansion coefficient.

  An example of a crack formed in the semiconductor package 1 is a crack 100 as shown in FIG. For example, the crack 100 is first formed in the underfill resin 40, and then the package substrate 10 and the semiconductor chip 20 are repeatedly deformed by thermal expansion and contraction due to heating and cooling during use. Will grow to extend. Since the deformation of the package substrate 10 due to heating and cooling and the stress due to the deformation are larger on the outer side than on the central part, the crack 100 is likely to occur in the outer region as shown in FIG. It tends to occur in a direction (concentric circle) connecting the bumps 30 adjacent to each other obliquely. When the crack 100 extending to the package substrate 10 cuts the internal wiring 12a and the like, a disconnection failure occurs in the package substrate 10. The crack 100 may occur not only in the underfill resin 40 but also in the protective film 13 such as a solder resist.

  As described above, in the semiconductor package 1, the package substrate 10 may be disconnected due to the crack 100 that grows with time due to repeated heating and cooling, leading to defects.

  Here, the case where the underfill resin 40 is provided between the package substrate 10 and the semiconductor chip 20 and the wiring 12a of the package substrate 10 is disconnected due to the crack 100 formed and grown there is illustrated. The underfill resin 40 may not be provided between the package substrate 10 and the semiconductor chip 20. Even in such a case, the wiring of the package substrate 10 itself is caused by the deformation of the package substrate 10 as described above. Cracks such as disconnection of 12a may occur. In addition, when the underfill resin 40 is provided between the package substrate 10 and the semiconductor chip 20, the wiring 12 a is disconnected not by the growth of cracks from the underfill resin 40 but by the cracks generated by the deformation of the package substrate 10. It can happen.

  By the way, whether or not the disconnection of the package substrate 10 as described above occurs or when it occurs may vary depending on the use environment and the operation state of the semiconductor package 1. Therefore, it is not always easy to predict when the semiconductor package 1 becomes defective due to the disconnection of the package substrate 10. If it is possible to know that the possibility of the disconnection of the package substrate 10 has increased before the semiconductor package 1 becomes defective due to the disconnection of the package substrate 10, measures such as replacement of the semiconductor package 1 can be taken. It becomes possible.

In view of the above, wiring (monitor wiring) described below as an embodiment is provided on the package substrate of the semiconductor package.
First, the first embodiment will be described.

  FIG. 2 is a diagram illustrating an example of a semiconductor package according to the first embodiment. FIG. 2A is a schematic plan view of a principal part of an example of the semiconductor package according to the first embodiment seen through, and FIG. 2B is a schematic L2-L2 cross-sectional view of FIG. is there. FIG. 2A shows a configuration example of the corner portion of the semiconductor package according to the first embodiment. For convenience, in FIG. 2B, wirings other than the monitor wiring are not illustrated.

A semiconductor package 1A shown in FIGS. 2A and 2B includes a package substrate 10A and a semiconductor chip 20 mounted on the package substrate 10A.
As shown in FIG. 2B, the package substrate 10 </ b> A includes a substrate 11 and a conductive portion 12 provided on the substrate 11. The substrate 11 includes a core substrate and an insulating layer provided thereon. The conductive portion 12 includes wiring and vias. Of the conductive portion 12, on the uppermost layer wiring 12a (signal wiring, power supply wiring) provided on the substrate 11, a portion connected to the semiconductor chip 20 (terminals 12b arranged in the vertical and horizontal directions) is excluded. A protective film 13 such as a resist is provided.

  As shown in FIG. 2B, the semiconductor chip 20 has terminals 21 arranged vertically and horizontally corresponding to the terminals 12b of the package substrate 10. The package substrate 10 </ b> A and the semiconductor chip 20 are electrically connected to each other using bumps 30 between the terminals 12 b and the terminals 21 that are arranged vertically and horizontally to correspond to each other, and the semiconductor chip 20 is flip-chip connected to the package substrate 10. ing.

As shown in FIG. 2B, an underfill resin 40 is filled between the semiconductor chip 20 and the package substrate 10.
On the package substrate 10A of the semiconductor package 1A, as shown in FIGS. 2A and 2B, a monitor wiring 50 is provided in a region (mounting region) AR on which the semiconductor chip 20 is mounted. A monitor terminal 60 and a monitor terminal 70 are provided at both ends of the monitor wiring 50. For example, the monitor wiring 50, the monitor terminal 60, and the monitor terminal 70 are provided in the same layer as the uppermost wiring 12a and the terminal 12b provided on the substrate 11 of the package substrate 10A. For example, the same material as the uppermost wiring 12a and the terminal 12b is used for the monitor wiring 50, the monitor terminal 60, and the monitor terminal 70. For example, the monitor terminal 60 and the monitor terminal 70 are arranged on the substrate 11 in the vertical and horizontal directions together with the terminal 12b group.

  As shown in FIGS. 2A and 2B, the monitor wiring 50 corresponds to a region between adjacent terminals 12b in a group of terminals 12b arranged vertically and horizontally (between the bumps 30 connected to them). Area). As described above, a crack that can cause disconnection of the wiring 12a is likely to occur in an outer region where deformation is relatively larger than the central portion of the package substrate 10, and a direction D (see FIG. 2) connecting the bumps 30 adjacent to each other diagonally. (A) is easy to occur. Therefore, for example, as shown in FIGS. 2 (A) and 2 (B), the monitor wiring 50 intersects the end region such as the corner portion of the package substrate 10A with a direction D where a crack is likely to occur. Provided.

  The monitor wiring 50 is smaller than the wiring 12a on the uppermost layer on the substrate 11 and the wiring 12c (signal wiring, power supply wiring) on the inner layer of the substrate 11 with respect to the stress caused by deformation due to heating and cooling of the package substrate 10A. The structure is such that disconnection occurs due to stress.

  FIG. 3 is a diagram illustrating a first configuration example of the monitor wiring according to the first embodiment. FIG. 3A is a schematic plan view of an essential part of the first configuration example of the monitor wiring according to the first embodiment, and FIG. 3B is an example of a state in which the monitor wiring of FIG. It is a principal part plane schematic diagram.

  The monitor wiring 50 shown in FIG. 3A has at least one, here a plurality of circular holes 51a, as an example, arranged on a center line C extending in the longitudinal direction (wiring length direction) X. ing. For example, the sizes (diameters) of the plurality of holes 51a are the same or substantially the same, and the distance d1 and the distance d2 from the hole 51a to the edge 52 and the edge 53 in the short direction (wiring width direction) Y of the monitor wiring 50 are the same. Or it is made substantially the same.

  Assume that a stress in the wiring length direction X is applied to the monitor wiring 50 having such a configuration by deformation of the package substrate 10A. In this case, the monitor wiring 50 is surrounded by a portion between the hole 51a and the edge 52 and the edge 53, that is, a portion 54 and a portion 55 in which the wiring width is partially narrowed (dotted line in FIG. 3A). The stress tends to concentrate on the part). By providing the monitor wiring 50 with the portion 54 and the portion 55 where stress is easily concentrated, when the stress in the wiring length direction X is applied, as shown in FIG. In addition, the monitor wiring 50 is easily disconnected at the portion 55.

  For example, the monitor wiring 50 can have the same or substantially the same wiring width as the wiring 12a such as the signal wiring connected to the terminal 12b (bump 30) and the inner layer wiring 12c of the package substrate 10A. Holes 51a like the monitor wiring 50 are not provided in the wiring 12a and the wiring 12c such as signal wiring. The package substrate 10A has a hole 51a, so that stress is easily concentrated at the predetermined portion 54 and the portion 55, and the monitor wiring 50 that is likely to be disconnected there is easily cracked as shown in FIG. 2A. Provided to intersect with direction D. By providing the monitor wiring 50 having the holes 51a so as to intersect the direction D where cracks are likely to occur, signal wiring and the like against stress generated in a predetermined direction (direction intersecting the direction D) due to deformation of the package substrate 10A. The monitor wiring 50 is likely to break before the wiring 12a and the wiring 12c.

  The monitor wiring 50 uses the monitor terminal 60 and the monitor terminal 70 to apply an electrical signal, for example, a constant voltage or a constant current, and monitor the electrical signal to monitor wiring. The presence or absence of 50 breaks is detected. Since the monitor wiring 50 is easier to disconnect than the wiring 12a and the wiring 12c such as the signal wiring, the monitor wiring is more easily disconnected before the wiring 12a is disconnected by monitoring the electrical signal and detecting the disconnection. It becomes possible to know that the stress that breaks 50 occurs in the package substrate 10A.

  That is, by detecting the disconnection of the monitor wiring 50, it is known that the possibility of the disconnection before the wiring 12a or the like is disconnected and the possibility that the semiconductor package 1A becomes defective is increased. It is possible to prevent the disconnection of the semiconductor package and the defect of the semiconductor package 1A. Alternatively, by detecting the disconnection of the monitor wiring 50, it is possible to detect the disconnection of the wiring 12a and the like and the defect of the semiconductor package 1A at an early stage.

  Note that the monitor wiring 50 having the hole 51a as described above can be provided at any location in the package substrate 10A. However, in order to prevent disconnection of the wiring 12a and the wiring 12c such as signal wiring and the defect of the semiconductor package 1A in advance or to find out early, the wiring 12a and the wiring 12c are provided so as to intersect with the direction D in which cracks are likely to occur as described above. It is preferable. Further, in the semiconductor package 1A, the stress generated by the deformation of the package substrate 10A is larger at the end than in the center of the mounting region of the semiconductor chip 20 in the plane direction, and the inner layer of the substrate 11 in the thickness direction. Than the surface layer. Therefore, the monitor wiring 50 having the hole 51a as described above is preferably provided at the end portion of the package substrate 10A, and is preferably provided on the surface layer of the substrate 11. Furthermore, since a crack that breaks the wiring 12a and the like is likely to occur in the mounting area AR of the semiconductor chip 20 of the package substrate 10A, the monitor wiring 50 having the hole 51a as described above is provided in the mounting area AR. preferable.

  As described above, the monitor wiring 50 having the hole 51a has a structure in which stress is easily concentrated on the portion 54 and the portion 55 between the hole 51a and the edge 52 and the edge 53, and is easily disconnected at the portion 54 and the portion 55. It has a structure. In such monitor wiring 50, by adjusting the size (diameter) of the hole 51a, the ease of disconnection and the magnitude of the stress to be disconnected can be adjusted.

  FIG. 4 is a diagram illustrating a first modification of the monitor wiring according to the first embodiment. FIGS. 4A and 4B are schematic plan views of relevant parts of a first modification of the monitor wiring according to the first embodiment.

  If the size of the hole 51a provided in the monitor wiring 50 is increased, the distance d1 and the distance d2 from the hole 51a to the edge 52 and the edge 53 in the wiring width direction Y are shortened as shown in FIG. And the width | variety of the site | part 55 becomes narrow. Therefore, the monitor wiring 50 in which the size of the hole 51a is increased is disconnected with a smaller stress. On the contrary, if the size of the hole 51a provided in the monitor wiring 50 is reduced, the distance d1 and the distance d2 become longer and the widths of the portion 54 and the portion 55 become wider as shown in FIG. 50 becomes disconnected by a larger stress. The size of the hole 51a provided in the monitor wiring 50 can be set based on the stress that can occur in the package substrate 10A.

Further, the magnitude of the disconnecting stress of the monitor wiring 50 can be adjusted by the shape of the hole 51a provided.
FIG. 5 is a diagram illustrating a second configuration example of the monitor wiring according to the first embodiment. FIG. 5A is a schematic plan view of a main part of the second configuration example of the monitor wiring according to the first embodiment, and FIG. 5B is an example of a state in which the monitor wiring of FIG. It is a principal part plane schematic diagram.

  In addition to the circular hole 51a as described above, the monitor wiring 50 may be provided with a diamond-shaped hole 51b as shown in FIG. Such a diamond-shaped hole 51b can be provided in the monitor wiring 50, and here, a case where a plurality of holes 51b are provided is illustrated as an example. For example, the sizes of the plurality of holes 51b are the same or substantially the same. As shown in FIG. 5A, the holes 51b are arranged such that a pair of opposing vertices are positioned on a center line C extending in the wiring length direction X, and the other pair of opposing vertices are arranged in the wiring width direction Y. The distance d3 and the distance d4 to the edge 52 and the edge 53 are the same or substantially the same.

  In the monitor wiring 50 provided with such a diamond-shaped hole 51b, when stress in the wiring length direction X is applied by deformation of the package substrate 10A, the gap between the opposing vertex of the hole 51a and the edge 52 and the edge 53 is reduced. The stress tends to concentrate on the part 54 and the part 55. Then, as shown in FIG. 5B, the monitor wiring 50 is easily disconnected at the part 54 and the part 55.

FIG. 6 is an explanatory diagram of the sensitivity of the monitor wiring according to the first embodiment.
FIG. 6 shows the relative magnitude of the disconnecting stress (F) between the monitor wiring 50 (M1) provided with the circular hole 51a and the monitor wiring 50 (M2) provided with the diamond-shaped hole 51b. Show. Here, the distance d1 and distance d2 to the edge 52 and the edge 53 when the circular hole 51a is provided, and the distance d3 and the distance to the edge 52 and the edge 53 when the diamond-shaped hole 51b is provided. d4 is made the same. As shown in FIG. 6, when the diamond-shaped hole 51b is provided, the stress until disconnection is relatively larger than when the circular hole 51a is provided.

  Thus, the ease of disconnection (sensitivity) of the monitor wiring 50 can be adjusted by the shape of the hole provided in the monitor wiring 50. Based on the stress that can occur in the package substrate 10A of the semiconductor package 1A, the monitor wiring 50 shown in FIG. 2A may be provided with a diamond-shaped hole 51b as shown in FIG.

  FIG. 7 is a view showing an example of the arrangement of monitor wirings according to the first embodiment. FIG. 7 is a schematic plan view of a principal part of an example of the semiconductor package according to the first embodiment seen through. FIG. 7 shows a configuration example of the corner portion of the semiconductor package according to the first embodiment.

  As described above, in the semiconductor package 1A, the stress generated by the deformation of the package substrate 10A is larger at the end than in the center of the mounting area AR of the semiconductor chip 20 in the planar direction. Therefore, based on the knowledge shown in FIG. 6, as shown in FIG. 7, a region (end region) 10 </ b> Aa in which a relatively large stress is generated corresponding to the end of the mounting region AR of the semiconductor chip 20 of the package substrate 10 </ b> A. Arranges the monitor wiring 50 provided with a circular hole 51a. On the other hand, a monitor wiring 50 provided with a diamond-shaped hole 51b is arranged in a region (internal region) 10Ab in which a relatively small stress is generated inside the end region 10Aa of the package substrate 10A.

  By arranging the monitor wiring 50 provided with the holes 51a and 51b having different shapes in this way, the disconnection detection sensitivity by the monitor wiring 50 in the mounting area AR of the semiconductor chip 20 of the package substrate 10A is made uniform. Can do.

Note that the monitor wiring 50 provided with the diamond-shaped holes 51b may be arranged in the end region 10Aa, and the monitor wiring 50 provided with the circular holes 51a may be arranged in the inner region 10Ab.
In addition, when the monitor wiring 50 is provided with the diamond-shaped hole 51b as described in FIG. 5, the size of the diamond-shaped hole 51b is set in the same manner as described for the circular hole 51a in FIG. By adjusting, the magnitude of the breaking stress can be adjusted.

Monitor wiring 50 provided with holes 51a or 51b having the same shape but different sizes may be disposed in the end region 10Aa and the inner region 10Ab.
3 and 5 illustrate the case where the circular holes 51a and the diamond-shaped holes 51b are provided in one row on the center line C, respectively, the holes 51a and the holes 51b each include a plurality of rows. It can also be provided.

  FIG. 8 is a diagram showing a second modification of the monitor wiring according to the first embodiment, and FIG. 9 is a diagram showing a third modification of the monitor wiring according to the first embodiment. FIG. 8 and FIG. 9 are schematic plan views of main parts of a second modification and a third modification of the monitor wiring according to the first embodiment, respectively.

  As shown in FIG. 8, the monitor wiring 50 can be provided with a plurality of circular holes 51 a (here, two rows as an example). In this case, the holes 51a are provided so that the holes 51a in the respective rows are arranged in a predetermined direction, for example, the direction D in which cracks are likely to occur, or are arranged in the wiring width direction Y, although illustration is omitted here. It can also be provided.

  Further, as shown in FIG. 9, the monitor wiring 50 can be provided with a plurality of rows of rhombus holes 51b (here, two rows as an example). In this case, the holes 51b are provided so that the holes 51b in the respective rows are arranged in a predetermined direction, for example, the direction D in which cracks are likely to occur, or are arranged in the wiring width direction Y although illustration is omitted here. It can also be provided.

  As described above, a predetermined electrical signal is supplied to the monitor wiring 50 of the package substrate 10A described above using the monitor terminal 60 and the monitor terminal 70, and the electrical signal is monitored. The presence or absence of disconnection can be detected. Such a function unit (monitor unit) that supplies an electrical signal to the monitor wiring 50 and monitors the electrical signal can be provided in the semiconductor package 1A or an electronic device using the semiconductor package 1A.

  FIG. 10 is a diagram illustrating a configuration example of the monitor unit. FIG. 11 is a diagram illustrating an example of a semiconductor package provided with a monitor unit, and FIG. 12 is a diagram illustrating an example of an electronic device provided with a monitor unit. 11 and 12 schematically show cross sections of the semiconductor package and the electronic device, respectively.

10 includes an electrical signal supply unit 81, an electrical signal detection unit 82, a continuity determination unit 83, and a disconnection information output unit 84.
The electric signal supply unit 81 is connected to a power supply (VDD). The electrical signal supply unit 81 is connected to the monitor terminal 60 and the monitor terminal 70 and supplies a predetermined electrical signal to the monitor wiring 50 between the monitor terminal 60 and the monitor terminal 70. For example, the electric signal supply unit 81 applies a constant voltage between the monitor terminal 60 and the monitor terminal 70 (monitor wiring 50) or constant between the monitor terminal 60 and the monitor terminal 70 (monitor wiring 50). Apply current.

The electric signal detector 82 detects an electric signal supplied to the monitor wiring 50 by the electric signal supplier 81.
The continuity determination unit 83 determines whether the monitor wiring 50 is disconnected based on the electrical signal detected by the electrical signal detection unit 82. The continuity determination unit 83 determines, for example, whether or not the monitor wiring 50 is conductive based on a change in voltage or current supplied to the monitor wiring 50 as an electrical signal and detected by the electrical signal detection unit 82, and the disconnection thereof. The presence or absence of is determined.

  When the continuity determination unit 83 determines that the monitor wiring 50 is disconnected, the disconnection information output unit 84 outputs information indicating the disconnection of the monitor wiring 50 (DATA) to the outside of the monitor unit 80.

For example, as shown in FIG. 11, the monitor unit 80 having the above-described configuration can be built in the semiconductor chip 20 mounted on the package substrate 10A.
In the semiconductor package 1 </ b> A shown in FIG. 11, the monitor terminals 60 and the monitor terminals 70 at both ends of the monitor wiring 50 are electrically connected to the terminals 21 of the semiconductor chip 20 through the bumps 30. The monitor unit 80 (its electrical signal supply unit 81) as shown in FIG. 10 is connected to the terminal 21 of the semiconductor chip 20 to which the monitor terminal 60 and the monitor terminal 70 are electrically connected. 22 is electrically connected. The monitor unit 80 is electrically connected to the power supply (VDD) via the terminals 12b of the package substrate 10A, the bumps 30, the terminals 21 of the semiconductor chip 20, and the wirings 22. The information (DATA) indicating the disconnection of the monitor wiring 50 output from the monitor unit 80 (the disconnection information output unit 84) is output to the package substrate 10A side via the wiring 22, the terminal 21, and the bump 30.

Thus, using the monitor unit 80 built in the semiconductor chip 20, the conduction state of the monitor wiring 50 of the package substrate 10 </ b> A is monitored, and information about the presence or absence of the disconnection is acquired.
Further, for example, as shown in FIG. 12, the monitor unit 80 can also be provided on the board 3 when the electronic device 2 is obtained by mounting the semiconductor package 1A on a wiring board (board).

  The electronic device 2 shown in FIG. 12 includes a semiconductor package 1A and a board 3 on which the semiconductor package 1A is mounted. The semiconductor package 1 </ b> A is electrically connected to the board 3 through the bumps 31. A monitor unit 80 as shown in FIG. 10 is mounted on the board 3. The monitor terminal 60 and the monitor terminal 70 at both ends of the monitor wiring 50 are electrically connected to the terminal 3b and the wiring 3a of the board 3 through the conductive part 12 and the bump 31 in the package substrate 10A, and the monitor part is connected to the wiring 3a. 80 (the electric signal supply unit 81) is electrically connected. The monitor unit 80 is electrically connected to the power supply (VDD) via the wiring 3a, and is information (DATA) indicating disconnection of the monitor wiring 50 output from the monitor unit 80 (its disconnection information output unit 84). ) Is output to the board 3 side via the wiring 3a.

  As described above, the monitor unit 80 mounted on the board 3 of the electronic device 2 is used to monitor the conduction state of the monitor wiring 50 of the package substrate 10A and acquire information about the presence or absence of the disconnection.

  In the package substrate 10A, a plurality of monitor wires 50 and monitor terminals 60 and 70 at both ends thereof may be provided. In this case, for example, the monitor unit 80 is connected to each monitor wiring 50, or the monitor units 80 are connected in series or in parallel to connect the monitor unit 80 to a predetermined pair of terminals (monitor terminals).

  By the way, the package substrate 10A can be stressed in a plurality of directions. In order to give sensitivity to such stresses in a plurality of directions, the monitor wiring 50 provided with the holes 51a and 51b as described above can be arranged as shown in FIG.

FIG. 13 is a diagram illustrating another arrangement example of the monitor wiring according to the first embodiment. FIG. 13 is a schematic plan view of a principal part of an example of the semiconductor package according to the first embodiment seen through.
The monitor wiring 50 provided with the holes 51a and 51b as described above is easily disconnected as shown in FIGS. 3B and 5B due to the stress in the wiring length direction X, in other words, in the wiring width direction Y. Is relatively sensitive to stress in the wiring length direction X. If stress is generated in the package substrate 10A from the central portion to the outside, as shown in FIG. 13, the monitor wiring 50 has a relatively high sensitivity to the stress in the wiring length direction X of the package substrate 10A. It arrange | positions so that it may become a direction which goes outside from a center part. In FIG. 13, the direction of sensitivity of the monitor wiring 50 is indicated by arrows.

By disposing the monitor wiring 50 as shown in FIG. 13, it is possible to detect disconnection due to stress generated in a plurality of directions of the package substrate 10A with high sensitivity.
Next, a second embodiment will be described.

FIG. 14 is a diagram illustrating a first configuration example of the monitor wiring according to the second embodiment. FIG. 14 is a schematic plan view of an essential part of a first configuration example of the monitor wiring according to the second embodiment.
The monitor wiring 50 shown in FIG. 14 has a plurality of circular holes 51a arranged on the center line C extending in the wiring length direction X as described above. The monitor wiring 50 shown in FIG. 14 has a distance d5 and a distance d6 from the hole 51a to the edge 52 and the edge 53 on both sides across the hole 51a in the direction D1 (Y) intersecting (orthogonal) with the wiring length direction X. However, it has the shape (arc-shaped outer shape part) which becomes the same or substantially the same. Further, the monitor wiring 50 shown in FIG. 14 has the same or substantially the same distance d7 and distance d8 from the hole 51a to the edge 52 and the edge 53 on both sides of the hole 51a in another direction D2 intersecting the wiring length direction X. It has such a shape (arc-shaped outer shape portion). Further, the monitor wiring 50 shown in FIG. 14 has the same or substantially the same distance d9 and distance d10 from the hole 51a to the edge 52 and the edge 53 on both sides of the hole 51a in another direction D3 intersecting the wiring length direction X. They have the same shape (arc-shaped outer shape). In the monitor wiring 50 shown in FIG. 14, the edge 52 and the edge 53 have, for example, a shape such that the distance d5 and the distance d6, the distance d7 and the distance d8, and the distance d9 and the distance d10 are all the same or substantially the same. Is done.

Such a monitor wiring 50 is arranged on the package substrate 10A on which the semiconductor chip 20 is mounted in the same manner as described in the first embodiment.
According to the monitor wiring 50 as shown in FIG. 14, it is possible to give sensitivity to stresses in a plurality of directions generated on the package substrate 10A.

FIG. 15 is an explanatory diagram of the stress direction and stress concentration of the monitor wiring in the first configuration example according to the second embodiment.
Assume that a stress in the wiring length direction X (thick arrow in FIG. 15A) is applied to the monitor wiring 50 as shown in FIG. 14, for example, as shown in FIG. In this case, a portion 56 of the monitor wiring 50 between the hole 51a and the edge 52 in the direction D1 orthogonal to the wiring length direction X, between the hole 51a and the edge 53, and between the edge 52 and the edge 53 (FIG. 15A). The stress is likely to concentrate on the part surrounded by the dotted line), and the monitor wiring 50 is likely to break at this part 56.

  Further, for example, as shown in FIG. 15B, it is assumed that stress in the direction D2 intersecting the wiring length direction X (thick arrow in FIG. 15B) is applied to the monitor wiring 50. In this case, stress tends to concentrate on the portion 57 (the portion surrounded by the dotted line in FIG. 15B) between the hole 51a and the edge 52 in the direction D3 and between the hole 51a and the edge 53 of the monitor wiring 50, The monitor wiring 50 is easily disconnected at this portion 57.

  Further, it is assumed that, for example, as shown in FIG. 15C, a stress in the direction D3 intersecting the wiring length direction X (thick arrow in FIG. 15C) is applied to the monitor wiring 50. In this case, stress tends to concentrate on the portion 58 (the portion surrounded by the dotted line in FIG. 15C) between the hole 51a and the edge 52 in the direction D2 and between the hole 51a and the edge 53 of the monitor wiring 50. At this portion 58, the monitor wiring 50 is easily disconnected.

  As described above, the monitor wiring 50 shown in FIG. 14 has a structure capable of obtaining sensitivity to stress in a plurality of directions. According to such monitor wiring 50, the degree of freedom of arrangement on the package substrate 10A can be increased.

FIG. 16 is a diagram illustrating an arrangement example of monitor wirings according to the second embodiment. FIG. 16 is a schematic plan view of a principal part of an example of a semiconductor package according to the second embodiment seen through.
When the structure as shown in FIG. 14 and FIG. 15 is adopted for the monitor wiring 50 and sensitivity is given to stress in a plurality of directions, the monitor wiring 50 is arranged with a relatively simple route. Can do. For example, as shown in FIG. 16, the monitor wiring 50 is arranged so that a part thereof is along the corner portion of the mounting area AR of the semiconductor chip 20, and a simpler route than the arrangement shown in FIG. It can be. In FIG. 16, the direction of sensitivity of the monitor wiring 50 is indicated by arrows.

  According to the monitor wiring 50 that is sensitive to stress in a plurality of directions as shown in FIGS. 14 and 15, the area occupied by the monitor wiring 50 on the package substrate 10A can be kept small. It can also be said that the monitor wiring 50 can be arranged in a small area on the package substrate 10A. By giving the monitor wiring 50 sensitivity to stresses in a plurality of directions, the monitor wiring 50 can be arranged in a small area, and the disconnection can be detected with constant sensitivity.

  Here, the monitor wiring 50 including the circular hole 51a and the edge 52 and the edge 53 having an arcuate outer shape portion having a predetermined distance in a predetermined direction from the hole 51a is illustrated. In addition, for the monitor wiring 50 including the diamond-shaped hole 51b, similarly, the edge 52 and the edge 53 are formed to have a shape having an outer portion with a predetermined distance in the predetermined direction from the hole 51b, and are sensitive to stress in a plurality of directions. It can be made to have a structure.

Further, in order to give sensitivity to stresses in a plurality of directions, the monitor wiring 50 can be structured as shown in FIG.
FIG. 17 is a diagram illustrating a second configuration example of the monitor wiring according to the second embodiment. FIG. 17 is a schematic plan view of an essential part of a second configuration example of the monitor wiring according to the second embodiment.

  The monitor wiring 50 shown in FIG. 17 includes holes 51c having a plurality of vertices arranged on a center line C extending in the wiring length direction X. Here, as an example, a hole 51c having eight vertices is illustrated. In the monitor wiring 50 shown in FIG. 17, the distance d5 and the distance d6 from the apex of the hole 51c to the edges 52 and 53 on both sides in the direction D1 intersecting (orthogonal) with the wiring length direction X are the same or substantially the same. They have the same shape. Further, in the monitor wiring 50 shown in FIG. 17, the distance d7 and the distance d8 from the apex of the hole 51c to the edge 52 and the edge 53 on both sides in another direction D2 intersecting the wiring length direction X are the same or substantially the same. It has such a shape. Further, in the monitor wiring 50 shown in FIG. 17, the distance d9 and the distance d10 from the vertex of the hole 51c to the edge 52 and the edge 53 on both sides in another direction D3 intersecting the wiring length direction X are the same or substantially the same. The shape is such that In the monitor wiring 50 shown in FIG. 17, the edge 52 and the edge 53 have, for example, a shape such that the distance d5 and the distance d6, the distance d7 and the distance d8, and the distance d9 and the distance d10 are all the same or substantially the same. Is done.

Such a monitor wiring 50 is arranged on the package substrate 10A on which the semiconductor chip 20 is mounted in the same manner as described in the first embodiment.
Also with the monitor wiring 50 as shown in FIG. 17, it is possible to provide sensitivity to stresses in a plurality of directions generated on the package substrate 10A.

FIG. 18 is an explanatory diagram of the stress direction and stress concentration of the monitor wiring in the second configuration example according to the second embodiment.
Assume that a stress in the wiring length direction X (thick arrow in FIG. 18A) is applied to the monitor wiring 50 as shown in FIG. 17, for example, as shown in FIG. In this case, the monitor wiring 50 is surrounded by a portion 56 between the vertex of the hole 51c and the edge 52 in the direction D1 orthogonal to the wiring length direction X and between the vertex of the hole 51c and the edge 53 (dotted line in FIG. 18A). The stress tends to concentrate on the part), and the monitor wiring 50 is likely to break at this part 56.

  Further, it is assumed that, for example, as shown in FIG. 18B, a stress in the direction D2 intersecting the wiring length direction X (thick arrow in FIG. 18B) is applied to the monitor wiring 50. In this case, stress is applied to the portion 57 (the portion surrounded by the dotted line in FIG. 18B) between the apex and the edge 52 of the hole 51c in the direction D3 and between the apex and the edge 53 of the hole 51c in the monitor wiring 50. It is easy to concentrate, and the monitor wiring 50 is easily disconnected at this portion 57.

  In addition, for example, as shown in FIG. 18C, it is assumed that stress in a direction D3 intersecting with the wiring length direction X (thick arrow in FIG. 18C) is applied to the monitor wiring 50. In this case, stress is applied to the portion 58 (the portion surrounded by the dotted line in FIG. 18C) between the apex and the edge 52 of the hole 51c in the direction D2 and between the apex and the edge 53 of the hole 51c in the monitor wiring 50. It is easy to concentrate, and the monitor wiring 50 is easily disconnected at this portion 58.

  As described above, the monitor wiring 50 shown in FIG. 17 has a structure capable of obtaining sensitivity to stresses in a plurality of directions, similarly to the monitor wiring 50 shown in FIG. 14 and the like. The degree of freedom of arrangement on the package substrate 10A can be increased, such as 50 can be arranged.

  In the monitor wiring 50 according to the second embodiment described above, the size of the hole 51a, the hole 51b and the hole 51c, and the distance to the edge 52 and the edge 53 are adjusted, so that the disconnection due to stress of the monitor wiring 50 is caused. Sensitivity can be adjusted.

Next, a third embodiment will be described.
FIG. 19 is a diagram illustrating a configuration example of monitor wiring according to the third embodiment. FIG. 19 is a schematic plan view of an essential part of a configuration example of monitor wiring according to the third embodiment.

  The monitor wiring 50 shown in FIG. 19 has a structure in which a plurality of circular holes 51a are arranged in a certain direction D4. As shown in FIG. 19, it is assumed that stress in a direction D5 intersecting the direction D4 (thick arrow in FIG. 19) is applied to such a monitor wiring 50. In this case, stress tends to concentrate on the portion 59 (the portion surrounded by the dotted line in FIG. 19) in the direction D4 in which the plurality of holes 51a are arranged in the monitor wiring 50, and the monitor wiring 50 is likely to break at this portion 59.

  Such a monitor wiring 50 is disposed on the package substrate 10A on which the semiconductor chip 20 is mounted in the same manner as described in the first and second embodiments. In the monitor wiring 50, the direction D4 in which the holes 51a are arranged is, for example, the direction D in which the crack is easily generated in the package substrate 10A.

  When the direction D of the package substrate 10A in which cracks are likely to occur (direction of the generated stress) is known, by arranging the holes 51a in the direction D, the probability of disconnection of the monitor wiring 50 due to cracks is increased, and disconnection detection is performed. Sensitivity can be increased. Further, when a crack is likely to occur in a region between the bumps 30 adjacent to each other on the package substrate 10A, a plurality of holes 51a arranged in the direction D where the crack is likely to be generated in the portion of the monitor wiring 50 passing through the region. May be provided to increase the disconnection detection sensitivity.

  Note that, here, the monitor wiring 50 having a structure in which a plurality of circular holes 51a are arranged in the predetermined direction D4 is illustrated, but the plurality of arrangements in the predetermined direction D4 is similarly performed in the case of the diamond-shaped holes 51b. The monitor wiring 50 having the above structure can be obtained.

Next, a fourth embodiment will be described.
The monitor wiring 50 as described in the first to third embodiments is arranged on the package substrate 10A together with other wiring such as signal wiring and power supply wiring. Here, as the fourth embodiment, the arrangement of the monitor wiring 50 and other wiring will be described.

  FIG. 20 is a diagram illustrating an example of a semiconductor package according to the fourth embodiment. FIG. 20 is a schematic plan view of a main part of an example of a semiconductor package according to the fourth embodiment as seen through. FIG. 20 shows a configuration example of the corner portion of the semiconductor package according to the fourth embodiment.

  A semiconductor package 1A shown in FIG. 20 includes a package substrate 10A and a semiconductor chip 20 mounted thereon as described in the first embodiment (FIG. 2). The package substrate 10 </ b> A and the semiconductor chip 20 are electrically connected to each other (the terminals 12 b and the terminals 21 described above) at the bumps 30 in FIG. 20. The monitor wiring 50 (shown by a thick solid line in FIG. 20) is provided so as to pass through a region corresponding to the space between the adjacent bumps 30 of the package substrate 10A. The monitor wiring 50 and the monitor terminals 60 and 70 at both ends thereof are in the same layer as the uppermost wiring and terminals (the above-described wiring 12a and terminal 12b) on the semiconductor chip 20 mounting surface side provided on the package substrate 10A. Is provided.

  As shown in FIG. 20, the terminal (the above-mentioned terminal 12b) of the package substrate 10A to which the bump 30 is connected has signal wiring or power supply wiring as shown in FIG. The wiring 12c (shown by a dotted line in FIG. 20) is electrically connected. The uppermost layer wiring 12a is disposed on the surface layer of the package substrate 10A, avoiding the monitor wiring 50. The inner layer wiring 12c is drawn from the terminal to which the bump 30 is connected through the uppermost layer wiring 12d and the via hole 12e connected to the wiring 12d, and is arranged in the inner layer of the package substrate 10A.

  On the package substrate 10A, for example, as shown in FIG. 20, the monitor wiring 50 and other wiring 12a and wiring 12c used as signal wiring or power wiring are arranged.

Next, a fifth embodiment will be described.
Here, an example of a manufacturing method of the package substrate 10A will be described as a fifth embodiment.

  21 and 22 are views showing an example of a package substrate manufacturing method according to the fifth embodiment. 21 (A) to 21 (D), 22 (A), and 22 (B) schematically show a cross section of the main part of each process of manufacturing the package substrate.

  The package substrate 10A can be manufactured by a build-up method. In this case, first, a core substrate 11a as shown in FIG. A prepreg or the like can be used for the base material 11aa of the core substrate 11a. Each base material 11aa on which a predetermined pattern of wiring 12f is formed is laminated, and after drilling, via holes 12g are formed by plating, and further, a predetermined pattern of wiring 12h is formed on the front and back surfaces to form the core substrate 11a. Is done. For the wiring 12f, the via hole 12g, and the wiring 12h, copper (Cu) or a material containing Cu can be used.

  After the formation of the core substrate 11a, as shown in FIG. 21B, the insulating layer 11ab is formed so as to fill the cavity of the via hole 12g and cover the wiring 12h formed on the front and back surfaces of the core substrate 11a. For the insulating layer 11ab, a resin curable by heat or light can be used. In forming the insulating layer 11ab, the resin provided in the via hole 12g and the resin provided on the front and back surfaces of the core substrate 11a are not necessarily the same material.

  After the formation of the insulating layer 11ab, as shown in FIG. 21C, an opening 11ac that reaches a predetermined portion of the wiring 12h is formed in the insulating layer 11ab. The opening 11ac can be formed by laser processing.

  After the opening 11ac is formed, as shown in FIG. 21D, a via 12i that penetrates the insulating layer 11ab and reaches the wiring 12h, and a wiring 12j on the insulating layer 11ab are formed. The via 12i and the wiring 12j can be formed by using a plating process, a photolithography technique, and an etching technique. For the via 12i and the wiring 12j, Cu or a material containing Cu can be used.

  Thereafter, in the same manner as in the steps of FIGS. 21B to 21D, as shown in FIG. 22A, the upper insulating layer 11ad and the insulating layer 11ad are penetrated to reach the lower wiring 12j. A via 12k and a wiring 12m on the insulating layer 11ad are formed. For the via 12k and the wiring 12m, Cu or a material containing Cu can be used. Note that the same steps as in FIGS. 21B to 21D are repeated in accordance with the number of wiring layers provided on the package substrate 10A.

  Here, for convenience, the wiring 12m on the substrate 11 in FIG. 22A is assumed to be the uppermost wiring (the wiring 12a described above). In this case, in the process of FIG. 22A, the conductor pattern 50a to be the monitor wiring 50 is formed on the insulating layer 11ad on one side, using the same material as the wiring 12m, together with the wiring 12m on the uppermost layer. The The conductor pattern 50a is formed by using a photolithographic technique and an etching technique in a region sandwiched between both ends of the conductor pattern 50a having a predetermined shape as described above (the hole 51a, the hole 51b, or the hole 51c) and an edge (the edge described above). 52 and edge 53).

  After the formation of the uppermost wiring 12m and the conductor pattern 50a, as shown in FIG. 22B, a protective film 13 such as a solder resist is formed. In the protective film 13 on the side of the one surface 10Ac on which the semiconductor chip 20 is mounted, openings 13a are formed at portions of the wiring 12m to which the bumps 30 are connected and at both ends of the conductor pattern 50a. A portion of the wiring 12 m exposed from the opening 13 a becomes a terminal 12 b connected to the bump 30. Both end portions of the conductor pattern 50 a exposed from the opening 13 a become the monitor terminal 60 and the monitor terminal 70. A portion of the conductor pattern 50 a sandwiched between the monitor terminal 60 and the monitor terminal 70 becomes the monitor wiring 50. Further, in the protective film 13 on the opposite surface 10Ad side, an opening 13b is formed at a portion to which a member (bump) such as a solder ball is connected. A surface treatment layer, for example, a laminated film of nickel (Ni) and gold (Au) may be further formed on the exposed portions from the opening 13a and the opening 13b.

  The package substrate 10A is formed by the process as described above. As exemplified here, the monitor wiring 50, the monitor terminal 60, and the monitor terminal 70 are formed of the same material in the same layer when the uppermost wiring 12a and the terminal 12b of the package substrate 10A are formed. And can be formed.

  When the monitor wiring 50, the monitor terminal 60, and the monitor terminal 70 are provided on the back surface side (surface 10Ad side) of the substrate 11, they are similarly formed together with the wiring and terminals provided on the back surface side of the substrate 11. it can. Similarly, when the monitor wiring 50, the monitor terminal 60, and the monitor terminal 70 are provided in the inner layer of the substrate 11, they can be formed together with the wiring provided in the inner layer of the substrate 11.

Next, a sixth embodiment will be described.
The semiconductor chip 20 is mounted on the package substrate 10A including the monitor wiring 50, the monitor terminal 60, and the monitor terminal 70 as described above, and the semiconductor package 1A is obtained. In addition, an electronic device can be obtained by mounting such a semiconductor package 1A on another wiring board (board) using a connection member such as a solder ball. Furthermore, an electronic device in which a plurality of semiconductor packages 1A are mounted on a board can be obtained. Thus, in the case of an electronic device in which a plurality of semiconductor packages 1A are mounted on a board, the monitor wiring 50 of each semiconductor package 1A can be electrically connected using the board.

FIG. 23 is a diagram illustrating a first configuration example of an electronic device according to the sixth embodiment. FIG. 23 is a schematic plan view of a first configuration example of an electronic device according to the sixth embodiment.
An electronic device 90a illustrated in FIG. 23 includes a board 91 and a plurality (seven examples here) of semiconductor packages 1A mounted on the board 91. Each semiconductor package 1A is electrically connected to the board 91 using a connection member such as a solder ball.

  Each semiconductor package 1A includes a package substrate 10A provided with the monitor wiring 50, the monitor terminal 60, and the monitor terminal 70 as described above. In the electronic device 90 a, the monitor wiring 50 of each semiconductor package 1 </ b> A is connected in series using the connection wiring 92 provided on the board 91. That is, by connecting the monitor terminals (the monitor terminal 60 and the monitor terminal 70) of the monitor wires 50 of the plurality of semiconductor packages 1A mounted on the board 91 by the connection wires 92, the plurality of semiconductor packages 1A. Are connected in series.

  The monitor unit 80 as described in FIGS. 10 and 12 is connected to the monitor terminal 60 and the monitor terminal 70 at the end of the monitor wiring 50 group connected in series in this way. The monitor unit 80 supplies an electrical signal to the group of monitor wirings 50 connected in series, and the electrical signal is monitored to determine the presence or absence of disconnection in the monitor wiring 50 group.

  Thus, in the electronic device 90a in which the monitor wirings 50 of the plurality of semiconductor packages 1A are connected in series, the connection wiring 92 can be arranged in a relatively small area of the board 91, and the signal wiring and power supply wiring of the board 91 are arranged. A decrease in the degree of freedom can be suppressed.

FIG. 24 is a diagram illustrating a second configuration example of the electronic device according to the sixth embodiment. FIG. 24 is a schematic plan view of a second configuration example of the electronic device according to the sixth embodiment.
In the electronic device 90b shown in FIG. 24, the monitor wiring 50 of a plurality (seven as an example) of the semiconductor package 1A mounted on the board 91 using solder balls or the like is connected to the connection wiring 92 provided on the board 91. And connected in parallel.

  The monitor unit 80 as described in FIGS. 10 and 12 is connected to the monitor terminal 60 and the monitor terminal 70 of each monitor wiring 50 connected in parallel. The monitor unit 80 supplies an electrical signal to each monitor wiring 50, and the electrical signal is monitored to determine whether or not each monitor wiring 50 is disconnected.

  As described above, in the electronic device 90b in which the monitor wirings 50 of the plurality of semiconductor packages 1A are connected in parallel, it is relatively easy to determine which of the plurality of monitor wirings 50 is broken, that is, the semiconductor package 1A in which the possibility of failure is increased. Can be identified.

FIG. 25 is a diagram illustrating a third configuration example of the electronic device according to the sixth embodiment. FIG. 25 is a schematic plan view of a third configuration example of the electronic device according to the sixth embodiment.
The electronic device 90c shown in FIG. 25 is connected in parallel with the case in which the monitor wirings 50 of a plurality of (seven examples here) semiconductor packages 1A mounted on the board 91 are connected in series using the connection wiring 92. Have a mixed configuration.

  As shown in FIG. 10 and FIG. 12, the monitor terminal 60 and the monitor terminal 70 at the end of the monitor wiring 50 group connected in series and the monitor terminal 60 and the monitor terminal 70 of each monitor wiring 50 connected in parallel are connected. A monitor unit 80 is connected. The monitor unit 80 supplies an electrical signal to the monitor wiring 50 group connected in series, and the electrical signal is monitored to determine whether or not there is a disconnection in the monitor wiring 50 group. In addition, the monitor unit 80 supplies an electrical signal to the monitor wirings 50 connected in parallel, and the electrical signals are monitored to determine whether the monitor wirings 50 are disconnected.

  When a plurality of monitor wirings 50 are connected in series, the arrangement area of the connection wiring 92 can be reduced, and when a plurality of monitor wirings 50 are connected in parallel, the disconnected monitor wiring 50 can be easily identified. Become. Based on conditions such as the arrangement of the signal wiring and power supply wiring of the board 91, the area where the connection wiring 92 can be arranged, and the importance of identifying the semiconductor package 1A that may be defective, as in this electronic device 90c, Series and parallel connection forms of the monitor wiring 50 may be mixed. Further, based on such conditions, a combination of monitor wirings 50 connected in series and in parallel may be set.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) a first wiring board;
A first electronic component mounted on the first wiring board,
The first wiring board is:
A first substrate;
A first wiring disposed on the first substrate and having a first opening;
An electronic device comprising: a first terminal and a second terminal respectively disposed at both ends of the first wiring.

(Additional remark 2) The said 1st wiring is arrange | positioned in the 1st area | region facing the said 1st electronic component, The electronic device of Additional remark 1 characterized by the above-mentioned.
(Appendix 3) The first wiring is
A first wiring portion disposed in an end region of the first region;
The second wiring part, which is disposed in an inner region inside the end region of the first region, and is disconnected by a stress having a magnitude different from that of the first wiring portion. Electronic devices.

(Appendix 4) The first wiring board is:
A third terminal group to which the first electronic component is electrically connected;
4. The electronic device according to any one of appendices 1 to 3, wherein at least a part of the first wiring passes between adjacent third terminals in the third terminal group.

(Supplementary Note 5) The first opening includes a plurality of holes,
The electronic device according to any one of appendices 1 to 4, wherein the plurality of holes are juxtaposed in a longitudinal direction of the first wiring.

  (Additional remark 6) The said 1st wiring has a shape where the edge of the both sides which pinched | interposed each said hole of the 1st direction crossing the said longitudinal direction becomes the same or substantially the same distance from the said hole. The electronic device according to appendix 5, characterized in that:

(Supplementary Note 7) The first opening includes a plurality of holes,
The electronic device according to any one of appendices 1 to 4, wherein the plurality of holes are arranged in parallel in a first direction intersecting a longitudinal direction of the first wiring.

(Supplementary note 8) The electronic device according to any one of supplementary notes 1 to 7, wherein the first terminal and the second terminal are electrically connected to the first electronic component.
(Supplementary Note 9) Further includes a third wiring board on which the first wiring board is mounted,
The electronic device according to any one of appendices 1 to 7, wherein the first terminal and the second terminal are electrically connected to the third wiring board.

(Appendix 10) a second wiring board;
A second electronic component mounted on the second wiring board;
A third wiring board on which the first wiring board and the second wiring board are mounted;
The second wiring board is
A second substrate;
A second wiring disposed on the second substrate and having a second opening;
A fourth terminal and a fifth terminal respectively disposed at both ends of the second wiring;
The first wiring and the second wiring are connected in series or in parallel using the first terminal and the second terminal, the fourth terminal and the fifth terminal, and the third wiring board. 10. The electronic device according to any one of appendices 1 to 9, wherein

(Supplementary Note 11) A first wiring board and a first electronic component mounted on the first wiring board, wherein the first wiring board is disposed on the first board and the first board. An inspection method for inspecting an electronic device including a first wiring having one opening, and a first terminal and a second terminal respectively disposed at both ends of the first wiring,
Electrically connecting the first wiring to a monitor unit using the first terminal and the second terminal;
Supplying a first electrical signal to the first wiring by the monitoring unit;
And a step of monitoring the first electrical signal by the monitoring unit.

(Additional remark 12) The said 1st wiring is arrange | positioned in the 1st area | region facing the said 1st electronic component, The inspection method of Additional remark 11 characterized by the above-mentioned.
(Supplementary Note 13) The electronic device includes a second wiring board, a second electronic component mounted on the second wiring board, and a third wiring board on which the first wiring board and the second wiring board are mounted. And further including
The second wiring substrate includes a second substrate, a second wiring disposed on the second substrate and having a second opening, and a fourth terminal and a fifth terminal respectively disposed at both ends of the second wiring. And
The first wiring and the second wiring are connected in series or in parallel using the first terminal and the second terminal, the fourth terminal and the fifth terminal, and the third wiring board,
Electrically connecting the first wiring to the monitor unit includes electrically connecting the first wiring and the second wiring to the monitor unit;
13. The inspection according to appendix 11 or 12, wherein the step of supplying the first electric signal to the first wiring includes a step of supplying the first electric signal to the first wiring and the second wiring. Method.

(Supplementary note 14) a substrate;
A wiring disposed on the substrate and having an opening;
A wiring board comprising: a first terminal and a second terminal respectively disposed at both ends of the wiring.

(Additional remark 15) The said board | substrate has an area | region facing the electronic component mounted,
The wiring board according to appendix 14, wherein the wiring is disposed in the region.

1, 1A Semiconductor package 2, 90a, 90b, 90c Electronic device 3, 91 Board 3a, 12a, 12c, 12d, 12f, 12h, 12j, 12m, 22 Wiring 3b, 12b, 21 Terminal 10, 10A Package substrate 10Aa End Area 10Ab Internal area 10Ac, 10Ad surface 11 Substrate 11a Core substrate 11aa Base material 11ab, 11ad Insulating layer 11ac, 13a, 13b Opening 12 Conductive part 12e, 12g Via hole 12i, 12k Via 13 Protective film 20 Semiconductor chip 30, 31 Bump 40 Underfill resin 50 Monitor wiring 50a Conductor pattern 51a, 51b, 51c Hole 52, 53 Edge 54, 55, 56, 57, 58, 59 Site 60, 70 Monitor terminal 80 Monitor part 81 Electric signal supply part 82 Electric signal detection part 8 Conducting determination unit 84 disconnected information output unit 92 connection wiring 100 cracks X, Y, D, D1~D5 direction d1~d10 distance AR mounting region

Claims (8)

A first wiring board;
A first electronic component mounted on the first wiring board,
The first wiring board is:
A first substrate;
And said first substrate, a first wiring disposed on the first region facing the first electronic component,
A first terminal and a second terminal respectively disposed at both ends of the first wiring ;
The first wiring is
A first wiring portion disposed in an end region of the first region and having a first hole;
A second wiring portion disposed in an inner region of the first region inside the end region and having a second hole having a different size or shape from the first hole;
Electronic device according to claim Rukoto to have a. The first wiring board is:
A third terminal group to which the first electronic component is electrically connected;
Wherein at least a portion of the first wiring, the electronic device according to claim 1, characterized in that pass between third terminals adjacent in said third terminal group. Wherein the first hole and a plurality of said second holes of multiple,
Wherein the first hole of the multiple is arranged in the longitudinal direction of the first wiring, a plurality of the second holes, according to claim 1 or 2, characterized in that it is arranged in the longitudinal direction Electronic devices. The first wiring, the first direction crossing the longitudinal direction, the edges of both sides of each of the first hole, the Ri Do the same or substantially the same distance from the first hole, each of the first both edges across the 2 holes, electronic device according to claim 3, characterized in that it has a name Ru shape the same or substantially the same distance from the second hole. Wherein the first hole and a plurality of said second holes of multiple,
Wherein the first hole of the multiple is arranged in the first direction crossing the longitudinal direction of the first wiring, a plurality of said second holes, characterized in that it is arranged in the first direction electronic device according to claim 1 or 2. A second wiring board;
A second electronic component mounted on the second wiring board;
A third wiring board on which the first wiring board and the second wiring board are mounted;
The second wiring board is
A second substrate;
Disposed on the second substrate, a second wiring having an open mouth,
A fourth terminal and a fifth terminal respectively disposed at both ends of the second wiring;
The first wiring and the second wiring are connected in series or in parallel using the first terminal and the second terminal, the fourth terminal and the fifth terminal, and the third wiring board. electronic device according to any one of claims 1 to 5, characterized in that. A first wiring board, the first and a first electronic component mounted on a wiring substrate, the first wiring substrate is a first substrate, on the first substrate, the first electronic component and the counter a first wiring disposed on the first region, and a first terminal and a second terminal disposed at both ends of the first wiring, the first wiring in the end region of the first region A first wiring portion having a first hole, and a second hole having a size or shape different from that of the first hole, disposed in an inner region inside the end region of the first region. an inspection method for inspecting an electronic device that having a second wiring portion,
Electrically connecting the first wiring to a monitor unit using the first terminal and the second terminal;
Supplying a first electrical signal to the first wiring by the monitoring unit;
And a step of monitoring the first electrical signal by the monitoring unit. A substrate having a region facing an electronic component to be mounted ;
A wiring disposed on the region on the substrate,
A first terminal and a second terminal respectively disposed at both ends of the wiring ;
The wiring is
A first wiring portion disposed in an end region of the region and having a first hole;
A second wiring portion disposed in an inner region of the region inside the end region and having a second hole having a different size or shape from the first hole;
Wiring board, characterized in Rukoto to have a.

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