CN117629450A - Temperature detection control circuit and storage device - Google Patents
Temperature detection control circuit and storage device Download PDFInfo
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- 238000009529 body temperature measurement Methods 0.000 claims description 59
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
- G01K7/42—Circuits effecting compensation of thermal inertia; Circuits for predicting the stationary value of a temperature
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/81—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the disclosure provides a temperature detection control circuit and a storage device, the temperature detection control circuit includes: a first signal module configured to generate an enable signal in response to a power-on signal, the enable signal being a pulse signal; a mode control module configured to receive the test signal, perform segment transmission on the enable signal, output the enable signal as a first enable signal during a period when the test signal is invalid, and output the enable signal as a second enable signal during a period when the test signal is valid; wherein the test signal is valid in the test mode and invalid in the working mode; and the second signal module is configured to receive the first enabling signal, the second enabling signal and the temperature measuring ending signal, generate a temperature measuring enabling signal based on the first enabling signal and the temperature measuring ending signal, generate a temperature measuring enabling signal based on the second enabling signal and the temperature measuring ending signal, and control the temperature detecting module to detect the temperature.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a temperature detection control circuit and a storage device.
Background
Storage devices for storing data can be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices, such as Dynamic Random Access Memory (DRAM) devices, store data by charging or discharging capacitors in memory cells and lose the stored data when powered down. Nonvolatile memory devices, such as flash memory devices, maintain stored data even when powered down. Volatile memory devices are widely used as the main memory for various apparatuses, while non-volatile memory devices are widely used for storing program codes and/or data in various electronic devices such as computers, mobile devices, and the like.
The temperature of the memory device affects the memory performance of the memory device, and thus, it is necessary to perform temperature detection on the memory device. In addition, the storage device also has a working mode and a test mode, and the working mode and the test mode have the requirements of temperature detection.
Disclosure of Invention
The embodiment of the disclosure provides a temperature detection control circuit and a storage device, which are at least beneficial to generating a temperature measurement enabling signal in a working mode and a test mode.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a temperature detection control circuit, including: a first signal module configured to generate an enable signal in response to a power-on signal, the enable signal being a pulse signal; a mode control module configured to receive a test signal, perform segment transmission on the enable signal, output the enable signal during a period when the test signal is invalid, take the enable signal as a first enable signal, output the enable signal during the period when the test signal is valid, and take the enable signal as a second enable signal; wherein the test signal is valid in a test mode and invalid in a working mode; and the second signal module is configured to receive the first enabling signal, the second enabling signal and the temperature measuring ending signal, generate a temperature measuring enabling signal based on the first enabling signal and the temperature measuring ending signal, generate a temperature measuring enabling signal based on the second enabling signal and the temperature measuring ending signal, and control the temperature detecting module to detect the temperature.
In some embodiments, the first signal module comprises: an oscillating circuit configured to generate an oscillating signal in response to the power-on signal; an enable signal generating circuit configured to receive the oscillation signal and generate the enable signal based on the number of oscillations of the oscillation signal.
In some embodiments, the enable signal generation circuit includes: a counter configured to receive the oscillation signal and count the oscillation frequency of the oscillation signal, obtain a count value, and re-count the oscillation frequency of the oscillation signal after the count value returns to zero; and a pulse generating unit configured to receive the count value, generate the enable signal when the count value reaches a preset value, and control the count value of the counter to be zero.
In some embodiments, the pulse generating unit comprises: a decoding unit configured to receive the count value and generate a decoding signal when the count value reaches the preset value, the decoding signal being a pulse signal; and an output unit configured to generate the enable signal and a first reset signal in response to the decode signal, the enable signal having a pulse width greater than a pulse width of the decode signal, the first reset signal for controlling the count value of the counter to return to zero.
In some embodiments, the preset values include a first preset value and a second preset value, and the first preset value is less than the second preset value; the decoding unit includes; a first decoding unit configured to receive the count value and generate a first decoding signal for controlling first pulse generation of the enable signal when the count value reaches the first preset value; a second decoding unit configured to receive the count value and generate a second decoding signal for controlling generation of remaining pulses of the enable signal when the count value reaches the second preset value; the output unit is further configured to generate a shutdown signal in response to a first pulse of the enable signal, the shutdown signal controlling the first decoding unit to stop operating.
In some embodiments, the mode control module comprises: a first control unit having a first node configured to receive the test signal and the enable signal and output the enable signal through the first node during a period in which the test signal is invalid; during the valid period of the test signal, the transmission path of the enabling signal provided by the first signal module to the first node is turned off, or the first node is enabled to have a first preset level during the valid period of the test signal; a second control unit having a second node configured to receive the test signal and the enable signal and output the enable signal through the second node during a period in which the test signal is valid; and during the invalid period of the test signal, the transmission path of the enabling signal provided by the first signal module to the second node is turned off, or the second node is enabled to have a second preset level during the invalid period of the test signal.
In some embodiments, the first control unit comprises: the input end of the first inverter receives the test signal; the first NAND gate is provided with a first input end and a second input end, the first input end receives the enabling signal, and the second input end is connected with the output end of the first inverter; the input end of the second inverter is connected with the output end of the first NAND gate, and the output end of the second inverter is used as the first node; the second control unit includes: a second NAND gate having a third input receiving the enable signal and a fourth input receiving the test signal; and the input end of the third inverter is connected with the output end of the second NAND gate, and the output end of the third inverter is used as the second node.
In some embodiments, the second signal module comprises: a logic circuit configured to receive the first enable signal and the second enable signal, generate a trigger signal, and the trigger signal is a pulse signal; a reset circuit configured to receive the temperature measurement end signal to generate a second reset signal; wherein, the temperature measurement ending signal indicates that the temperature detection is not ended, and the second reset signal is invalid; the temperature measurement ending signal indicates that the temperature detection is ended, and the second reset signal is valid; a trigger circuit configured to receive the trigger signal and the second reset signal and generate the temperature measurement enable signal; wherein the second reset signal is inactive; the temperature measurement enabling signal is used for controlling the temperature detection module to detect the temperature, and the temperature measurement enabling signal is used for controlling the temperature detection module to end the temperature detection during the second reset effective period.
In some embodiments, the logic circuit comprises: a first logic circuit having a third node configured to receive the first enable signal and output a first trigger signal via the third node; wherein, during the valid period of the test signal, the first trigger signal has a third preset level, and during the invalid period of the test signal, the first trigger signal is a pulse signal; a second logic circuit having a fourth node configured to receive the second enable signal and output a second trigger signal via the fourth node; wherein, during the valid period of the test signal, the second trigger signal is a pulse signal, and during the invalid period of the test signal, the second trigger signal has a fourth preset level; and the two input ends of the AND gate circuit are respectively connected with the third node and the fourth node, and perform AND operation on the first trigger signal and the second trigger signal to output the trigger signals.
In some embodiments, the first logic circuit comprises: the third NAND gate is provided with a fifth input end and a sixth input end, the fifth input end receives the first enabling signal, the sixth input end is connected with the fifth input end through odd fourth inverters, and the output end of the third NAND gate is the third node; the second logic circuit includes: and a fourth NAND gate having a seventh input terminal and an eighth input terminal, wherein the seventh input terminal receives the second enable signal, the eighth input terminal and the seventh input terminal are connected through an odd number of fifth inverters, and the output terminal of the fourth NAND gate is the fourth node.
In some embodiments, the reset circuit comprises: and the fifth NAND gate is provided with a ninth input end and a tenth input end, the ninth input end receives the temperature measurement ending signal, the tenth input end and the ninth input end are connected through an odd number of sixth inverters, and the output end of the fifth NAND gate outputs the second reset signal.
In some embodiments, the trigger circuit includes an RS trigger, a trigger end of the RS trigger receives the trigger signal, a reset end of the RS trigger receives the second reset signal, and an output end of the RS trigger outputs the temperature measurement enable signal.
In some embodiments, the second signal module further comprises: a sixth nand gate having an eleventh input terminal connected to the output terminal of the RS flip-flop and a twelfth input terminal receiving the power-on signal; and the input end of the seventh inverter is connected with the output end of the sixth NAND gate, and the output end of the seventh inverter outputs the temperature measurement enabling signal.
According to some embodiments of the present disclosure, there is provided a storage device according to another aspect of the embodiments of the present disclosure, including: a memory array; a temperature detection control circuit as described above; and the temperature detection module is used for responding to the temperature measurement enabling signal to detect the temperature of the storage array and outputting a temperature detection value.
In some embodiments, a register for storing the temperature detection value; and the test circuit is used for outputting the temperature detection value to the test bonding pad.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
in the temperature detection control circuit provided by the embodiment of the disclosure, after receiving a power-on signal, the first signal module generates an enabling signal; the mode control module receives the enabling signal and the test signal, and when the test signal is invalid, the mode control module receives the enabling signal and takes the enabling signal corresponding to the invalid period of the test signal as a first enabling signal, and when the test signal is valid, the mode control module receives the enabling signal and takes the enabling signal corresponding to the valid period of the test signal as a second enabling signal, so that the mode control module can generate the first enabling signal corresponding to the working mode and the second enabling signal corresponding to the test mode; in the working mode, the second signal generation module receives the first enabling signal to generate a temperature measurement enabling signal, and in the test mode, the second signal generation module receives the second enabling signal to generate the temperature measurement enabling signal, so that the purpose of generating the temperature measurement enabling signal for controlling the temperature detection module to detect the temperature in both the test mode and the working mode is achieved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings do not depict a proportional limitation unless expressly stated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a block diagram of a temperature detection control circuit provided by an embodiment of the present disclosure;
FIG. 2 is a block diagram of a first signal module in a temperature detection control circuit according to an embodiment of the disclosure;
fig. 3 is a schematic circuit diagram of a first signal module in a temperature detection control circuit according to an embodiment of the disclosure;
fig. 4 is a signal timing diagram of each signal in the first signal module according to an embodiment of the disclosure;
Fig. 5 is a schematic circuit diagram of a mode control module and a second signal module 1 in the temperature detection control circuit according to the embodiment of the present disclosure;
FIG. 6 is a signal timing diagram of signals in the temperature detection control circuit according to the embodiment of the disclosure;
fig. 7 is a schematic circuit structure diagram of a specific circuit of a first logic circuit and a timing chart of each signal in the temperature detection control circuit according to the embodiment of the disclosure;
fig. 8 is a schematic diagram of a specific circuit structure of a second logic circuit and a timing chart of each signal in the temperature detection control circuit according to the embodiment of the disclosure;
fig. 9 is a schematic circuit diagram of a specific circuit structure of a reset circuit in a temperature detection control circuit and a timing chart of each signal according to an embodiment of the disclosure;
FIG. 10 is a block diagram of a memory device provided by an embodiment of the present disclosure;
fig. 11 is another block diagram of a storage device according to an embodiment of the present disclosure.
Detailed Description
Fig. 1 is a block diagram of a temperature detection control circuit according to an embodiment of the present disclosure.
Referring to fig. 1, a temperature detection control circuit provided in an embodiment of the present disclosure includes: a first signal module 101 configured to generate an enable signal TSEn0 in response to a power on signal, the enable signal being a pulse signal; a mode control module 102 configured to receive the test signal tmtsprot and segment-transmit the enable signal TSEn0, output the enable signal TSEn0 as the first enable signal TSEn during the test signal tmtsprot being inactive, output the enable signal TSEn0 as the second enable signal TmTSEn during the test signal tmtsprot being active; wherein the test signal TmTSProbe is active in the test mode and inactive in the operational mode; the second signal module 103 is configured to receive the first enable signal TSEn, the second enable signal TmTSEn, and the temperature measurement end signal TSDone, generate the temperature measurement enable signal TSCoreEn based on the first enable signal TSEn and the temperature measurement end signal TSDone, and generate the temperature measurement enable signal TSCoreEn based on the second enable signal TmTSEn and the temperature measurement end signal TSDone, where the temperature measurement enable signal TSCoreEn is used to control the temperature detection module to perform temperature detection.
In the above technical solution, after receiving the power on signal, the first signal module 101 generates the enable signal TSEn0; the mode control module 102 receives the enable signal TSEn0 and the test signal tmtswarp, and indicates that the operation mode is in a period where the test signal tmtswarp is inactive, the mode control module 102 receives the enable signal TSEn0 and takes the enable signal TSEn0 corresponding to the period where the test signal tmtswarp is inactive as a first enable signal TSEn, and indicates that the operation mode is in a period where the test signal tmtswarp is active, the mode control module 102 receives the enable signal TSEn0 and takes the enable signal TSEn0 corresponding to the period where the test signal tmtswarp is active as a second enable signal TmTSEn, so that the mode control module 102 can generate the first enable signal TSEn corresponding to the operation mode and the second enable signal corresponding to the test mode, respectively; in the working mode, the second signal generating module 103 receives the first enabling signal TSEn to generate the temperature measurement enabling signal TSCoreEn, and in the test mode, the second signal generating module 103 receives the second enabling signal TmTSEn to generate the temperature measurement enabling signal TSCoreEn, so that the generation of the test enabling signal is realized by utilizing different enabling signals in different modes, the influence of signal noise of the corresponding enabling signal on the operation of the other mode under the operation condition of one mode is avoided, that is, the influence of noise of one of the first enabling signal or the second enabling signal in the operation process on the effective operation of the other mode is avoided.
In addition, for the first enable signal TSEn corresponding to the operation mode and the second enable signal TmTSEn corresponding to the test mode, both the enable signal TSEn0 generated by the first signal module 101, that is, the enable signal TSEn0 generated by the same first signal module 101 may be used to generate the first enable signal and the second enable signal valid in different periods, which is beneficial to reducing the complexity of the circuit and saving the power consumption of the temperature detection control circuit.
The temperature detection control circuit provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In some embodiments, the temperature detection control circuit may be applied in temperature detection of the memory device. The first signal module 101 receives the power on signal, which indicates that the temperature detection control circuit needs to enable the temperature detection control function, and generates the temperature measurement enable signal TSCoreEn for controlling the temperature detection.
Fig. 2 is a block diagram of a first signal module in a temperature detection control circuit according to an embodiment of the disclosure, fig. 3 is a schematic circuit structure diagram of the first signal module in the temperature detection control circuit according to an embodiment of the disclosure, and fig. 4 is a signal timing diagram of each signal in the first signal module 101 according to an embodiment of the disclosure.
Referring to fig. 2, in some embodiments, the first signal module 101 may include: an oscillation circuit 111 configured to generate an oscillation signal OSC in response to a power-on signal Poweron; the enable signal generating circuit 121 is configured to receive the oscillation signal OSC and generate the enable signal TSEn0 based on the number of oscillations of the oscillation signal OSC.
The power-up signal Poweron is a high level signal, that is, the power-up signal Poweron is a logic "1" level, and the oscillation circuit 111 starts to oscillate. It will be appreciated that in some embodiments, the power on signal may be transmitted to both the first signal module 101 and the memory array of the memory device, indicating that the memory array is powered up to enter an operational state.
The oscillation circuit 111 is configured to generate a periodically varying voltage signal, i.e., an oscillation signal OSC, and the oscillation circuit 111 may be a sine wave oscillator or a non-sine wave oscillator. The waveform generated by the sine wave oscillator is very close to sine wave or cosine wave, and the oscillation frequency is relatively stable; the waveform generated by the non-sinusoidal oscillator is a non-sinusoidal pulse waveform, such as a square wave, a rectangular wave, a sawtooth wave, etc. The frequency stability of the non-sinusoidal oscillator is not high. Accordingly, the oscillation signal OSC may be a sine wave or a cosine wave, and the oscillation signal OSC may be a square wave, a rectangular wave, or a sawtooth wave. The oscillation signal OSC may have different waveforms according to the specific circuit configuration of the oscillation circuit 111.
Referring to fig. 3, in some embodiments, the oscillating circuit 111 may be an RC delay loop oscillator (RC delay based Ring oscillator) comprising: AN input end of the NAND gate AN receives the power-on signal; at least two resistors R and at least two inverters inv in cascade, the resistor R at the first position is connected with the output end of the NAND gate AN, the resistor at the tail stage is connected with the other end of the NAND gate AN through one inverter inv, and the two resistors R at the adjacent stages are connected through one inverter inv; and one end of the capacitor C is connected with the connecting node of the resistor R and the input end of the inverter inv, and the other end of the capacitor C is grounded. Note that, in fig. 3, only 2 resistors R, 2 inverters inv, and 2 capacitors C are illustrated, and in practice, the oscillating circuit 111 may include N resistors R, N inverters inv and N capacitors C, where N may be any even number greater than or equal to 2, such as 4, 6, 8, and so on.
In other examples, the oscillation circuit 111 may be an LC oscillator or a quartz crystal oscillator.
The oscillation signal OSC is transmitted to the enable signal generating circuit 121, and the enable signal generating circuit 121 obtains an oscillation period of the oscillation signal OSC, and generates a pulse when the oscillation period reaches a preset period; then, the oscillation period acquired by the enable signal generation circuit 121 is zeroed and the oscillation period is reacquired, and when the reacquired oscillation period reaches a preset period, the next pulse is generated; this cycle is repeated to generate a plurality of pulses to sequentially form the enable signal TSEn0.
With continued reference to fig. 3, in some embodiments, the enable signal generation circuit 121 may include: a counter 11 configured to receive the oscillation signal OSC and count the number of oscillations of the oscillation signal OSC, obtain a count value B < n:0>, and re-count the number of oscillations of the oscillation signal OSC after the count value B < n:0> is zeroed; the pulse generating unit 12 is configured to receive the count value B < n:0>, and generate the enable signal TSEn0 when the count value B < n:0> reaches a preset value, and control the count value B < n:0> of the counter 11 to be zeroed.
The counter 11 obtains the number of oscillation cycles of the oscillation circuit 111 by counting the number of oscillation times, and it can be understood that the count value B < n:0> is the number of oscillation cycles. The count value B < n:0> is used as an external trigger signal for generating the enable signal TSEn0 by the trigger pulse generating unit 12, the pulse generating unit 12 generates one pulse of the enable signal TSEn0 when the count value B < n:0> reaches a preset value, counts the oscillation signal of the oscillation signal OSC again after the count value B < n:0> of the counter 11 is zeroed, and generates a new count value B < n:0>; the pulse generating unit 12 generates the next pulse of the enable signal TSEn0 when the new count value B < n:0> reaches a preset value. The pulse generating unit 12 generates the required enable signal TSEn0 in such a cyclic reciprocation. Specifically, the pulse generating unit 12 may be further configured to generate the first reset signal CntRst if the pulse generating unit 12 generates one pulse of the enable signal TSEn0, and the counter 11 resets the count value B < n:0> to zero in response to the first reset signal CntRst.
It will be appreciated that the count value B < n:0> characterizes the number of periods of the oscillation period, and the duration of a single oscillation period of the oscillation circuit 111 may be known, the corresponding count value B < n:0> may also characterize the oscillation duration, the preset value may also correspondingly characterize the preset duration, the count value B < n:0> reaches the preset value, which indicates that the oscillation duration satisfies the preset duration, and the pulse generating unit 12 generates one pulse of the enable signal TSEn 0.
The counter 11 may be a trigger-based counting circuit. In one specific example, the counter 11 may be a 16-bit (bit) counter, and n in the corresponding count value B < n:0> is 15. It can be appreciated that the number of bits of the counter 11 may be determined according to actual needs, where the counter 11 has a maximum count value, and the maximum count value characterizes a maximum oscillation duration, as long as it is satisfied that the maximum oscillation duration characterized by the maximum count value of the counter 11 is less than or equal to a preset duration characterized by a preset value. For example, the counter 11 may be a 4-bit counter, an 8-bit counter, a 32-bit counter, or the like.
In addition, the counter 11 has a reset terminal, and the reset terminal of the counter 11 is also activated by receiving the power-on signal Poweron.
With continued reference to fig. 3, in some embodiments, the pulse generation unit 12 may include: a decoding unit 1201 configured to receive the count value B < n:0>, and generate a decoded signal when the count value B < n:0> reaches a preset value, the decoded signal being a pulse signal; the output unit 1202 is configured to generate an enable signal TSEn0 and a first reset signal CntRst in response to the decode signal, the pulse width of the enable signal TSEn0 being larger than the pulse width of the decode signal, the first reset signal CntRst being used to control the count value B < n:0> of the counter 11 to return to zero.
Specifically, when the count value B < n:0> reaches a preset value, the decoding unit 1201 generates one pulse of the decoded signal, and in a specific example, one pulse of the decoded signal generated by the decoding unit 1201 may be a high-level pulse, the decoded signal having a level rising edge and a level falling edge. The output unit 1202 may be triggered by a level rising edge of the decoded signal to generate one pulse of the enable signal TSEn0, and in a specific example, one pulse of the enable signal TSEn0 generated by the output unit 1202 may be a high level pulse. It will be appreciated that the output unit 1202 may also be triggered by the falling edge of the level of the decoded signal, generating a pulse of the enable signal TSEn 0. The counter 11, upon receiving the first reset signal CntRst, zeroes the count value B < n:0> so as to recount, thereby causing the decoding unit 1201 to generate the next pulse of the decoding signal, and the output unit 1202 outputs the next pulse of the enable signal TSEn 0.
Referring to fig. 3 and 4 in combination, in some embodiments, the time interval from the receipt of the power-on signal Poweron to the generation of the first pulse of the enable signal TSEn0 is a first interval t1, and the time interval between the remaining pulses of the enable signal TSEn0 is a second interval t2, and the first interval t1 may be smaller than the second interval t2. Correspondingly, the preset values can comprise a first preset value and a second preset value, and the first preset value is smaller than the second preset value; the decoding unit 1201 may include; a first decoding unit 21 configured to receive the count value B < n:0> and generate a first decoding signal En1ms when the count value B < n:0> reaches a first preset value, the first decoding signal En1ms being used for controlling a first pulse generation of the enable signal TSEn 0; a second decoding unit 22 configured to receive the count value B < n:0> and generate a second decoding signal En32ms for controlling the generation of the remaining pulses of the enable signal TSEn0 when the count value B < n:0> reaches a second preset value; the output unit 1202 is further configured to generate a shutdown signal En1msDis in response to the first pulse of the enable signal TSEn0, the shutdown signal En1msDis controlling the first decoding unit 21 to stop operating.
The output unit 1202 receives the first decoded signal En1ms and generates a first pulse of the enable signal TSEn 0; the output unit 1202 receives the second decoding signal En32ms and generates the remaining pulses of the enable signal TSEn 0.
In a specific example, the first interval t1 may be 1ms and the second interval t2 may be 32ms. It should be understood that, in other embodiments, the first interval t1 may be the same as the second interval t2, or, the time interval between adjacent pulses, that is, the second time interval, may also have different parameters, the decoding unit 1201 configures a plurality of corresponding sub-decoding units that generate different decoding signals, and the preset values corresponding to the sub-decoding units are different, that is, each sub-decoding unit generates a corresponding decoding signal when counting to reach the different preset values, and the corresponding output unit controls at least one sub-decoding unit of the plurality of sub-decoding units to be turned on based on a preset program, for example, according to the number of received pulse signals. It can be understood that, since the sub-decoding units with smaller corresponding preset values shield the sub-decoding units with larger corresponding preset values, at least one of the plurality of sub-decoding units is controlled to be turned on, which essentially means that the output unit needs to turn off other sub-decoding units with preset values smaller than the target preset value, and at least other sub-decoding units with preset values larger than the target preset value can judge whether to be turned on according to actual needs, such as current conditions; it should be further noted that, the start-up sequence of the sub-decoding units actually outputting the decoded signal may be independent of the corresponding preset value, i.e., the time interval of the enable signal TSEn0 is not necessarily from large to small.
Referring to fig. 3 and 4 in combination, after receiving the power-on signal Poweron, that is, the power-on signal Poweron is a high level signal, the oscillation circuit 111 generates a periodic oscillation signal OSC; the counter 11 starts counting, taking the counter 11 as a 16-bit counter, wherein a first preset value corresponding to a count value B <15:0> for the first time represents that the oscillation duration is 1ms, and a second preset value corresponding to a count value B <15:0> for the second time and later represents that the oscillation duration is 32ms as an example; generating a pulse of a first decoding signal En1ms when the first count value B <15:0> reaches a first preset value; when the first count value B <15:0> reaches a second preset value, a pulse of the second decoding signal En32ms is generated. The output unit 1202 generates a first pulse of the enable signal TSEn0 in response to the first decoding signal En1ms, and generates the off signal En1msDis after the first pulse of TSEn0 is generated, generates the remaining pulses of the enable signal TSEn0 in response to the second decoding signal En32ms, and generates the first reset signal CntRst during the pulse of the enable signal TSEn0, when the count value B <15:0> of the counter 11 is zeroed.
Referring to fig. 1, the mode control module 102 has a first node net1 and a second node net2, and in an operation mode, an enable signal TSEn0 is output through the first node net1, and the enable signal TSEn0 output by the first node net1 is used as a first enable signal TSEn; in the test mode, an enable signal is output through the second node net2, and the enable signal TSEn0 output by the second node net2 is taken as a second enable signal TmTSEn.
Specifically, in the working mode, the mode control module 102 may intercept a transmission path of the enable signal TSEn0 to the second node net2, or the mode control module 102 may have a function of pulling the potential of the second node net2 low, so that the enable signal TSEn0 output by the second node net2 is directly changed into a low level signal, that is, an invalid enable signal TSEn0. In the test mode, the mode control module 102 may intercept a transmission path of the enable signal TSEn0 to the first node net1, or the mode control module 102 may have a function of pulling the potential of the first node net1 low, so that the enable signal TSEn0 output by the first node net1 directly changes to a low level signal, i.e. an invalid enable signal TSEn0.
Fig. 5 is a schematic circuit diagram of a mode control module 102 and a second signal module 103 in the temperature detection control circuit according to the embodiment of the disclosure, and fig. 6 is a signal timing diagram of each signal in the temperature detection control circuit according to the embodiment of the disclosure.
Referring to fig. 5 and 6 in combination, in some embodiments, the mode control module 102 includes: a first control unit 112 having a first node net1 configured to receive the test signal TmTSProbe and the enable signal TSEn0 and output the enable signal TSEn0 through the first node net1 during a period in which the test signal TmTSProbe is inactive; the transmission path of the enable signal TSEn0 provided by the first signal module 101 to the first node net1 is turned off during the test signal TmTSProbe is active, or the first node net1 is made to have a first preset level during the test signal TmTSProbe is active.
During the period in which the test signal TmTSProbe is inactive, the first control unit 112 outputs the enable signal TSEn0 as the first enable signal TSEn through the first node net 1. During the period when the test signal TmTSProbe is active, the enable signal TSEn0 cannot be transmitted to the first node net1, and accordingly, the first enable signal TSEn is inactive; alternatively, the first control unit 112 may directly pull down the first node net1 to a first preset level, and accordingly, the first enable signal TSEn is inactive, and the first preset level may be a low level.
With continued reference to fig. 5 and 6, the mode control unit 102 may further include: a second control unit 122 having a second node net2 configured to receive the test signal TmTSProbe and the enable signal TSEn0 and output the enable signal TSEn0 through the second node net2 during the period in which the test signal TmTSProbe is active; the transmission path of the enable signal TSEn0 supplied from the first signal module 101 to the second node net2 is turned off during the test signal TmTSProbe is inactive, or the second node net2 is made to have a second preset level during the test signal TmTSProbe is inactive.
During the test signal TmTSProbe is active, the second control unit 122 outputs the enable signal TSEn0 through the second node net2 as the second enable signal TmTSEn. During the period in which the test signal TmTSProbe is inactive, the enable signal TSEn0 cannot be transmitted to the second node net2, and accordingly, the second enable signal TmTSEn is inactive; alternatively, the second control unit 122 may directly pull down the second node net2 to a second preset level, and accordingly, the second enable signal TmTSEn is inactive, and the second preset level may be a low level.
Referring to fig. 6, in some examples, the test signal TmTSProbe is a high level signal, i.e., the test signal TmTSProbe is a logic "1", then the test signal TmTSProbe is active, and the test signal TmTSProbe is a low level signal, i.e., the test signal TmTSProbe is a logic "0", then the test signal TmTSProbe is inactive. Where "high" and "low" are compared to active and inactive periods of level.
Referring to fig. 5, in some embodiments, the first control unit 112 may include: a first inverter inv1, an input terminal of the first inverter inv1 receiving a test signal TmTSProbe; the first NAND gate AN1 is provided with a first input end and a second input end, wherein the first input end receives AN enabling signal TSEn0, and the second input end is connected with the output end of the first inverter inv 1; the input end of the second inverter inv2 is connected with the output end of the first NAND gate AN1, and the output end of the second inverter inv2 serves as a first node net1.
Referring to fig. 5 and 6 in combination, in the operation mode, the test signal TmTSProbe is a low level signal, i.e. logic "0", the output end of the first inverter inv1 is a high level signal, i.e. logic "1", the second input end of the first nand gate AN1 is logic "1", and the output end of the first nand gate AN1 is inverted to the first input end, i.e. the output end of the first nand gate AN1 outputs AN inverted signal of the enable signal TSEn 0; the input terminal of the second inverter inv2 receives the inverted signal of the enable signal TSEn0, and correspondingly, the output terminal of the second inverter inv2 outputs the enable signal TSEn0, i.e. outputs the valid first enable signal TSEn0. In the test mode, the test signal TmTSProbe is a high-level signal, i.e. logic "1", the output end of the first inverter inv1 outputs a low-level signal, i.e. logic "0", and the output end of the first nand gate AN1 outputs a high-level signal, i.e. logic "1"; the input terminal of the second inverter inv2 receives the logic "1" and outputs the logic "0", i.e. the first node net1 outputs the low level signal, and the first enable signal TSEn output by the first node net1 is invalid.
With continued reference to fig. 5, in some embodiments, the second control unit 122 may include: a second nand gate AN2 having a third input terminal receiving the enable signal TSEn0 and a fourth input terminal receiving the test signal TmTSProbe; and the input end of the third inverter inv3 is connected with the output end of the second NAND gate AN2, and the output end of the third inverter inv3 is used as a second node net2.
Referring to fig. 5 and 6 in combination, in the operation mode, the test signal TmTSProbe is a low level signal, i.e. logic "0", and the fourth input terminal of the second nand gate AN2 is logic "0", so that the output terminal of the second nand gate AN2 outputs a high level signal, i.e. logic "1", and the input terminal of the third inverter inv3 receives logic "1", and correspondingly, the output terminal of the third inverter inv3 outputs a low level signal, i.e. logic "0", i.e. the second node net2 outputs a low level signal, and at this time, the second enable signal TmTSEn output by the second node net2 is invalid. In the test mode, the test signal TmTSProbe is a high level signal, i.e. a logic "1", and the output end of the second nand gate AN2 is inverted to the third input end, i.e. the output end of the second nand gate AN2 outputs AN inverted signal of the enable signal TSEn 0; the input terminal of the third inverter inv3 receives the inverted signal of the enable signal TSEn0, and correspondingly, the output terminal of the third inverter inv3 outputs the enable signal TSEn0, i.e. outputs the valid second enable signal TmTSEn.
During the period when the test signal TmTSProbe is inactive, the second signal module 103 receives the active first enable signal TSEn and generates the thermometric enable signal TSCoreEn; during the validity period of the test signal TmTSProbe, the second signal module 103 receives the valid second enable signal TmTSEn and generates the thermometric enable signal TSCoreEn. In one example, the rising edge of the level of the first enable signal TSEn may be used as a trigger edge for generating the start position of the pulse of the thermometric enable signal TSCoreEn; in another example, the falling edge of the first enable signal TSEn may be used as a trigger edge for generating the start position of the pulse of the thermometric enable signal TSCoreEn. In one example, the rising edge of the level of the second enable signal TmTSEn may be used as a trigger edge for generating the start position of the pulse of the thermometric enable signal TSCoreEn; in another example, the falling edge of the level of the second enable signal TmTSEn may be used as a trigger edge for generating the start position of the pulse of the thermometric enable signal TSCoreEn. In one example, the rising edge of the level of the thermometric end signal TSDone may be used as a trigger edge of the pulse end position of the thermometric enable signal TSCoreEn; in another example, the falling edge of the level of the thermometric receiving signal TSDone may be used as a trigger edge of the pulse end position of the thermometric enabling signal TSCoreEn.
In some embodiments, referring to fig. 5, the second signal module 103 may include: a logic circuit 113 configured to receive the first enable signal TSEn and the second enable signal TmTSEn, generate a trigger signal, the trigger signal being a pulse signal; a reset circuit 123 configured to receive the temperature measurement end signal TSDone to generate a second reset signal; wherein, the temperature measurement ending signal TSDone indicates that the temperature detection is not ended, and the second reset signal is invalid; the temperature measurement ending signal TSDone indicates that the temperature detection is ended, and the second reset signal is valid; a trigger circuit 133 configured to receive the trigger signal and the second reset signal, and generate a temperature measurement enable signal TSCoreEn; wherein the second reset signal is inactive; the temperature measurement enabling signal TSCoreEn is used for controlling the temperature detection module to detect the temperature, and the temperature measurement enabling signal TSCoreEn is used for controlling the temperature detection module to end temperature detection during the second reset effective period.
Referring to fig. 5 and 6 in combination, the level rising edge of the first enable signal TSEn and the level rising edge of the second enable signal TmTSEn are used as trigger edges for generating the level rising edge of the thermometric enable signal TSCoreEn; the rising edge of the level of the temperature measurement end signal TSDone serves as a trigger edge for generating the falling edge of the level of the temperature measurement enable signal TSCoreEn.
Referring to fig. 6, in some embodiments, logic 113 may include: a first logic circuit 31 having a third node na configured to receive the first enable signal TSEn and output a first trigger signal via the third node na; the first trigger signal has a third preset level in the effective period of the test signal TmTSProbe, and is a pulse signal in the ineffective period of the test signal TmTSProbe; a second logic circuit 32 having a fourth node nb configured to receive the second enable signal TmTSEn and output a second trigger signal via the fourth node nb; wherein, during the effective period of the test signal TmTSProbe, the second trigger signal is a pulse signal, and during the ineffective period of the test signal TmTSProbe, the second trigger signal has a fourth preset level; and an and circuit 33, two input terminals are respectively connected to the third node na and the fourth node nb, and perform an and operation on the first trigger signal and the second trigger signal, output a trigger signal, and output a trigger signal through the fifth node nc. The and circuit 33 may be formed of a nand gate and an inverter connected to an output terminal of the nand gate.
The third preset level may be a high level, the corresponding first trigger signal is a low level pulse, the fourth preset level may be a high level, and the corresponding second trigger signal is a low level pulse. During the test signal valid period, the first trigger signal is a high level signal, and then the second trigger signal is output as a trigger signal via the fifth node nc, that is, the trigger signal output by the fifth node nc is a low level pulse signal. During the test signal is inactive, the second trigger signal is a high level signal, and the first trigger signal is output as a trigger signal via the fifth node nc, that is, the trigger signal output by the fifth node nc is a low level pulse signal.
Fig. 7 is a schematic circuit structure diagram of a first logic circuit and a timing chart of each signal in the temperature detection control circuit according to the embodiment of the disclosure. Referring to fig. 7, in some examples, the pulse signal output by the fifth node nc may be a low level pulse. Accordingly, the first logic circuit 31 may include: the third nand gate AN3 has a fifth input terminal in1 and a sixth input terminal, the fifth input terminal in1 receives the first enable signal TSEn, the sixth input terminal is connected to the fifth input terminal in1 through AN odd number of fourth inverters inv4, and AN output terminal out1 of the third nand gate AN3 is a third node na. The first trigger signal output by the third node na is a low-level pulse signal.
Fig. 8 is a schematic circuit structure diagram of a second logic circuit in the temperature detection control circuit and a timing chart of each signal according to an embodiment of the disclosure. Referring to fig. 8, the second logic circuit 32 may include: the fourth nand gate AN4 has a seventh input terminal in2 and AN eighth input terminal, the seventh input terminal in2 receives the second enable signal TmTSEn, the eighth input terminal and the seventh input terminal in2 are connected through AN odd number of fifth inverters inv5, and AN output terminal out2 of the fourth nand gate AN4 is a fourth node nb. The second trigger signal output from the fourth node nb is a low-level pulse signal.
Fig. 9 is a schematic circuit structure diagram of a reset circuit and a timing chart of signals in the temperature detection control circuit according to an embodiment of the present disclosure. Referring to fig. 9, the reset circuit 123 may include: the fifth nand gate AN5 has a ninth input terminal in3 and a tenth input terminal, the ninth input terminal in3 receives the temperature measurement end signal TSDone, the tenth input terminal and the ninth input terminal in3 are connected through AN odd number of sixth inverters inv6, and the output terminal out3 of the fifth nand gate AN5 outputs the second reset signal.
With continued reference to fig. 5, the trigger circuit 133 may include an RS trigger, a trigger terminal S of which receives the trigger signal, a reset terminal R of which receives the second reset signal, and an output terminal of which outputs the temperature measurement enable signal TSCoreEn.
With continued reference to fig. 5, in some embodiments, the second signal module 103 may further include: a sixth nand gate AN6 having AN eleventh input terminal connected to the output terminal of the trigger circuit 133 and a twelfth input terminal receiving the power on signal Poweron; the input end of the seventh inverter inv7 is connected to the output end of the sixth nand gate AN6, and the output end of the seventh inverter inv7 outputs the temperature measurement enable signal TSCoreEn.
The sixth nand gate AN6 and the seventh inverter inv7 serve as a driving circuit on the transmission path of the temperature measurement enable signal TSCoreEn to improve the transmission capability of the temperature measurement enable signal TSCoreEn outputted from the output terminal of the trigger circuit 33 to the temperature detection module.
The working principle of the temperature measurement detection control circuit will be described with reference to fig. 5 to 9:
in the test mode, the test signal TmTSProbe is a logic "1", the first enable signal TSEn is an inactive signal, and the second enable signal TmTSEn is active, i.e., the second enable signal TmTSEn is a high level pulse signal; the level change edge of the second enable signal TmTSEn triggers the fourth node nb and the fifth node nc to output a low-level pulse signal, and the output end of the trigger circuit 133 outputs a temperature measurement enable signal TSCoreEn which is a high-level pulse signal; after the temperature detection is finished, the temperature measurement finishing signal TSDone has level change edges, and correspondingly generates a second reset signal which is a low-level pulse signal; after receiving the low level pulse of the second reset signal, the trigger circuit 133 resets the output terminal of the trigger circuit 133, so that the temperature measurement enable signal TSCoreEn is reset to an invalid signal.
In the operation mode, the test signal TmTSProbe is a logic "0", the first enable signal TSEn is valid, i.e. the first enable signal TSEn is a high level pulse signal, and the second enable signal TmTSEn is an inactive signal; the level change edge of the first enable signal TSEn triggers the third node na and the fifth node nc to output a low-level pulse signal, and the output end of the trigger circuit 133 outputs a temperature measurement enable signal TSCoreEn which is a high-level pulse signal; after the temperature detection is finished, the temperature measurement finishing signal TSDone has level change edges, and correspondingly generates a second reset signal which is a low-level pulse signal; after receiving the low level pulse of the second reset signal, the trigger circuit 133 resets the output terminal of the trigger circuit 133, so that the temperature measurement enable signal TSCoreEn is reset to an invalid signal.
The embodiment of the disclosure also provides a storage device, which comprises the temperature detection control circuit provided by the embodiment. The storage device provided in the embodiments of the present disclosure will be described in detail with reference to the drawings, and it should be noted that the same or corresponding parts as those of the foregoing embodiments may be referred to for description of the foregoing embodiments, and details are not repeated herein. Fig. 10 is a block diagram of a storage device according to an embodiment of the present disclosure, and fig. 11 is another block diagram of a storage device according to an embodiment of the present disclosure.
Referring to fig. 6, 10 and 11 in combination, the memory device includes: a memory array 300; a temperature detection control circuit 301; the temperature detection module 302 is configured to perform temperature detection on the storage array in response to the temperature measurement enable signal TSCoreEn, and output a temperature detection value TSOut.
The memory device may be a DRAM memory device, such as a DDR5 DRAM memory device or a DDR4 DRAM memory device. In other embodiments, the memory device may also be an SRAM memory device, an SDRAM memory device, a ROM memory device, or a flash memory device.
In some embodiments, the power-up signal received by temperature detection control circuit 301 and memory array 300 may be the same power-up signal poweron, and power-up signal poweron may also power temperature detection module 302. The temperature detection control circuit 301 generates a temperature measurement enable signal TSCoreEn, and the temperature detection module 302 performs temperature detection on the memory array 300 in response to the temperature measurement enable signal TSCoreEn, and obtains and outputs a temperature detection value TSOut. And the temperature detection module 302 generates a temperature measurement end signal TSDone after the temperature detection is completed, and the temperature measurement end signal TSDone is transmitted to the temperature detection control circuit 301, so that the temperature detection control circuit 301 controls the temperature measurement enable signal TSCoreEn to be in an inactive state.
Referring to fig. 11, the storage device may further include: the refresh module 303 responds to the temperature sensing value TSOut and generates a refresh signal Srefclk corresponding to the temperature sensing value TSOut, which the memory array 300 receives and adjusts the refresh frequency. In a specific example, if the temperature detection value TSOut is higher, the refresh control module 303 generates a refresh signal Srefclk for controlling the memory array 300 to reduce the refresh frequency; if the temperature detection value TSOut is within the allowable range, the refresh control module generates a refresh signal Srefclk that controls the refresh frequency of the memory array 300 to be unchanged.
In some embodiments, the first signal module 101 may be integrated with the refresh module 303, for example, both the first signal module 101 and the refresh module may be integrated together in a self-refresh module (not shown), so that it is beneficial to ensure that the first signal module 101, which initially generates the enable signal, can effectively drive the refresh module 303, in other words, when the first signal module 101 is normally powered up and enabled, the refresh module 303 may be considered to be normally powered up and enabled, and at this time, it is beneficial to ensure that the enable signal generated by the first signal module 101 is eventually effectively executed; if the two modules are integrated together, the situation that the first signal module 101 is normally powered up and the refresh module 303 is not normally powered up may occur, and then ineffective current consumption is caused, and if the two modules are integrated together, when the refresh module 303 is not normally powered up, the first signal module 101 is not normally powered up, so that ineffective current consumption of the mode control circuit 102, the second signal module 103 and the temperature detection module 302 is advantageously saved.
The storage device may further include: a register 305, the register 305 being for storing a temperature detection value TSOut; test circuit 306, test circuit 306 is used to output temperature sensing value TSOut to test pad 307.
The storage device may further include a decoder 304, the decoder 304 performs decoding processing on the temperature detection value TSOut, and the temperature detection value TSOut after the decoding processing is stored in the register 305. In one example, register 305 may be Mode Register 4 (Mode Register 4, MR4) and Decoder 304 may be a Decoder (MR 4 Decoder) corresponding to Mode Register 4.
Test circuit 306 transmits temperature sensing value TSOut to pad 307 to facilitate directly retrieving temperature sensing value TSOut from pad 307.
From the foregoing analysis, it can be seen that the storage device provided in the embodiments of the present disclosure can not only realize temperature detection of the storage array 300 in the test mode, but also realize temperature detection of the storage array 300 in the working mode.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.
Claims (15)
1. A temperature detection control circuit, characterized by comprising:
a first signal module configured to generate an enable signal in response to a power-on signal, the enable signal being a pulse signal;
a mode control module configured to receive a test signal, perform segment transmission on the enable signal, output the enable signal during a period when the test signal is invalid, take the enable signal as a first enable signal, output the enable signal during the period when the test signal is valid, and take the enable signal as a second enable signal; wherein the test signal is valid in a test mode and invalid in a working mode;
and the second signal module is configured to receive the first enabling signal, the second enabling signal and the temperature measuring ending signal, generate a temperature measuring enabling signal based on the first enabling signal and the temperature measuring ending signal, generate a temperature measuring enabling signal based on the second enabling signal and the temperature measuring ending signal, and control the temperature detecting module to detect the temperature.
2. The temperature detection control circuit of claim 1, wherein the first signal module comprises:
An oscillating circuit configured to generate an oscillating signal in response to the power-on signal;
an enable signal generating circuit configured to receive the oscillation signal and generate the enable signal based on the number of oscillations of the oscillation signal.
3. The temperature detection control circuit according to claim 2, wherein the enable signal generation circuit includes:
a counter configured to receive the oscillation signal and count the oscillation frequency of the oscillation signal, obtain a count value, and re-count the oscillation frequency of the oscillation signal after the count value returns to zero;
and a pulse generating unit configured to receive the count value, generate the enable signal when the count value reaches a preset value, and control the count value of the counter to be zero.
4. The temperature detection control circuit according to claim 3, wherein the pulse generation unit includes:
a decoding unit configured to receive the count value and generate a decoding signal when the count value reaches the preset value, the decoding signal being a pulse signal;
and an output unit configured to generate the enable signal and a first reset signal in response to the decode signal, the enable signal having a pulse width greater than a pulse width of the decode signal, the first reset signal for controlling the count value of the counter to return to zero.
5. The temperature detection control circuit of claim 4, wherein the preset values include a first preset value and a second preset value, and wherein the first preset value is less than the second preset value; the decoding unit includes;
a first decoding unit configured to receive the count value and generate when the count value reaches the first preset value
A first decoded signal for controlling a first pulse generation of the enable signal;
a second decoding unit configured to receive the count value and generate a second decoding signal for controlling generation of remaining pulses of the enable signal when the count value reaches the second preset value;
the output unit is further configured to generate a shutdown signal in response to a first pulse of the enable signal, the shutdown signal controlling the first decoding unit to stop operating.
6. The temperature detection control circuit of claim 1, wherein the mode control module comprises:
a first control unit having a first node configured to receive the test signal and the enable signal and output the enable signal through the first node during a period in which the test signal is invalid; during the valid period of the test signal, the transmission path of the enabling signal provided by the first signal module to the first node is turned off, or the first node is enabled to have a first preset level during the valid period of the test signal;
A second control unit having a second node configured to receive the test signal and the enable signal and output the enable signal through the second node during a period in which the test signal is valid; and during the invalid period of the test signal, the transmission path of the enabling signal provided by the first signal module to the second node is turned off, or the second node is enabled to have a second preset level during the invalid period of the test signal.
7. The temperature detection control circuit according to claim 6, wherein the first control unit includes:
the input end of the first inverter receives the test signal;
the first NAND gate is provided with a first input end and a second input end, the first input end receives the enabling signal, and the second input end is connected with the output end of the first inverter;
the input end of the second inverter is connected with the output end of the first NAND gate, and the output end of the second inverter is used as the first node;
the second control unit includes:
a second NAND gate having a third input receiving the enable signal and a fourth input receiving the test signal;
And the input end of the third inverter is connected with the output end of the second NAND gate, and the output end of the third inverter is used as the second node.
8. The temperature detection control circuit of claim 1, wherein the second signal module comprises:
a logic circuit configured to receive the first enable signal and the second enable signal, generate a trigger signal, and the trigger signal is a pulse signal;
a reset circuit configured to receive the temperature measurement end signal to generate a second reset signal; wherein, the temperature measurement ending signal indicates that the temperature detection is not ended, and the second reset signal is invalid; the temperature measurement ending signal indicates that the temperature detection is ended, and the second reset signal is valid;
a trigger circuit configured to receive the trigger signal and the second reset signal and generate the temperature measurement enable signal; wherein the second reset signal is inactive; the temperature measurement enabling signal is used for controlling the temperature detection module to detect the temperature, and the temperature measurement enabling signal is used for controlling the temperature detection module to end the temperature detection during the second reset effective period.
9. The temperature-sensing control circuit of claim 8, wherein the logic circuit comprises:
a first logic circuit having a third node configured to receive the first enable signal and output a first trigger signal via the third node; wherein, during the valid period of the test signal, the first trigger signal has a third preset level, and during the invalid period of the test signal, the first trigger signal is a pulse signal;
a second logic circuit having a fourth node configured to receive the second enable signal and output a second trigger signal via the fourth node; wherein, during the valid period of the test signal, the second trigger signal is a pulse signal, and during the invalid period of the test signal, the second trigger signal has a fourth preset level;
and the two input ends of the AND gate circuit are respectively connected with the third node and the fourth node, and perform AND operation on the first trigger signal and the second trigger signal to output the trigger signals.
10. The temperature-sensing control circuit of claim 9, wherein the first logic circuit comprises:
The third NAND gate is provided with a fifth input end and a sixth input end, the fifth input end receives the first enabling signal, the sixth input end is connected with the fifth input end through odd fourth inverters, and the output end of the third NAND gate is the third node;
the second logic circuit includes:
and a fourth NAND gate having a seventh input terminal and an eighth input terminal, wherein the seventh input terminal receives the second enable signal, the eighth input terminal and the seventh input terminal are connected through an odd number of fifth inverters, and the output terminal of the fourth NAND gate is the fourth node.
11. The temperature detection control circuit according to claim 8, wherein the reset circuit includes:
and the fifth NAND gate is provided with a ninth input end and a tenth input end, the ninth input end receives the temperature measurement ending signal, the tenth input end and the ninth input end are connected through an odd number of sixth inverters, and the output end of the fifth NAND gate outputs the second reset signal.
12. The temperature detection control circuit of claim 8, wherein the trigger circuit comprises an RS trigger, a trigger terminal of the RS trigger receives the trigger signal, a reset terminal of the RS trigger receives the second reset signal, and an output terminal of the RS trigger outputs the temperature measurement enable signal.
13. The temperature-sensing control circuit of claim 12, wherein the second signal module further comprises:
a sixth nand gate having an eleventh input terminal connected to the output terminal of the RS flip-flop and a twelfth input terminal receiving the power-on signal;
and the input end of the seventh inverter is connected with the output end of the sixth NAND gate, and the output end of the seventh inverter outputs the temperature measurement enabling signal.
14. A memory device, comprising:
a memory array;
a temperature detection control circuit as claimed in any one of claims 1 to 13;
and the temperature detection module is used for responding to the temperature measurement enabling signal to detect the temperature of the storage array and outputting a temperature detection value.
15. The storage device of claim 14, further comprising:
a register for storing the temperature detection value;
and the test circuit is used for outputting the temperature detection value to the test bonding pad.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210970506.XA CN117629450A (en) | 2022-08-12 | 2022-08-12 | Temperature detection control circuit and storage device |
| PCT/CN2022/124146 WO2024031817A1 (en) | 2022-08-12 | 2022-10-09 | Temperature measurement control circuit and storage device |
| TW111141235A TWI831448B (en) | 2022-08-12 | 2022-10-28 | Temperature detection control circuit and storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210970506.XA CN117629450A (en) | 2022-08-12 | 2022-08-12 | Temperature detection control circuit and storage device |
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| Publication Number | Publication Date |
|---|---|
| CN117629450A true CN117629450A (en) | 2024-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210970506.XA Pending CN117629450A (en) | 2022-08-12 | 2022-08-12 | Temperature detection control circuit and storage device |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN117629450A (en) |
| TW (1) | TWI831448B (en) |
| WO (1) | WO2024031817A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100522433B1 (en) * | 2003-04-29 | 2005-10-20 | 주식회사 하이닉스반도체 | Domain crossing circuit |
| JP2008141013A (en) * | 2006-12-01 | 2008-06-19 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP5255908B2 (en) * | 2008-05-27 | 2013-08-07 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit and operation method thereof |
| KR20130015940A (en) * | 2011-08-05 | 2013-02-14 | 에스케이하이닉스 주식회사 | Semiconductor memory device comprising teperature test circuit |
| US10006959B2 (en) * | 2014-08-20 | 2018-06-26 | Darryl G. Walker | Testing and setting performance parameters in a semiconductor device and method therefor |
| CN104749515B (en) * | 2015-03-31 | 2017-12-15 | 中国人民解放军国防科学技术大学 | A kind of low-power consumption sweep test method and device for dividing segmented based on order etc. |
| CN106771981A (en) * | 2017-01-18 | 2017-05-31 | 大唐微电子技术有限公司 | A kind of test control circuit, chip and test control method |
| CN108896903A (en) * | 2018-06-13 | 2018-11-27 | 天津大学 | The gradually verifying type security sweep chain apparatus and method of logic-based encryption |
| CN212909796U (en) * | 2020-07-08 | 2021-04-06 | 深圳市华盛昌科技实业股份有限公司 | Visual doorbell circuit with temperature measurement function and visual doorbell |
| US20220149762A1 (en) * | 2020-11-11 | 2022-05-12 | Global Mixed-Mode Technology Inc. | Motor controller |
| CN113472190B (en) * | 2021-06-11 | 2022-11-11 | 深圳欧陆通电子股份有限公司 | Low-temperature starting method of switching power supply and switching power supply |
-
2022
- 2022-08-12 CN CN202210970506.XA patent/CN117629450A/en active Pending
- 2022-10-09 WO PCT/CN2022/124146 patent/WO2024031817A1/en unknown
- 2022-10-28 TW TW111141235A patent/TWI831448B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| TW202407700A (en) | 2024-02-16 |
| TWI831448B (en) | 2024-02-01 |
| WO2024031817A1 (en) | 2024-02-15 |
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