TW201351410A - Semiconductor memory device with self-refresh timing circuit - Google Patents

Abstract

A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.

Description

Semiconductor memory component with self-renewing sequential circuit

The present invention relates to a semiconductor memory device having a self-renewing sequential circuit.

Semiconductor memory components have been widely used in many electronic products to store and read data. The semiconductor memory device includes a plurality of memory cells, each of which is composed of a transistor and a capacitor. A Dynamic Random Access Memory (DRAM) component stores data bits by storing charge in a capacitor. However, after a period of time, the charge stored in the capacitor will gradually leak through the substrate or other path, so that the data bit cannot be permanently stored therein. Therefore, it is necessary to periodically update the memory cells in the DRAM device to avoid data loss.

Several updates have been proposed for how to periodically update the memory cells in a DRAM cell, one of which is to operate the DRAM component in a self-refresh mode. In the self-updating mode, one of the addresses corresponding to the address generated by an internal address counter, after receiving a self-updating command, performs an update operation according to a predetermined period. The predetermined period is generally determined by the data retention time of the DRAM cell. After the update operation, the address counter is reinitialized to wait for the next self-update command.

In general, the self-renewal mode is set in the low power loss mode. The current consumption in self-renewal mode needs to be minimized. One method of reducing the power loss required for self-renewal in DRAM components is to change the predetermined update period based on the ambient temperature. That is, when the temperature is lower than a set value, the update operation is performed at a longer predetermined period; conversely, when the temperature is higher than the set value, the update operation is performed at a shorter predetermined period.

In order to detect the ambient temperature, a temperature sensing element is disposed in the DRAM component to provide a corresponding temperature signal, and a comparison component is provided to change the time of the predetermined period according to the temperature signal. However, in the prior art, the temperature sensing element and the comparison element remain in an activated state to continuously detect the temperature, thus increasing the total power loss of the DRAM element. In order to reduce power loss, it is necessary to propose a timing circuit to control the time of the predetermined period and provide a uniformity circuit to selectively enable the comparison element.

It is an object of the present invention to provide a semiconductor memory device having a self-refreshing sequential circuit. The semiconductor memory device can reduce power loss by the self-refreshing sequential circuit disclosed by the present invention.

To achieve the above object, an embodiment of the semiconductor memory device of the present invention includes a command decoder, a plurality of memory banks, a bank address generator, a self-updating counter, and a self-updating sequential circuit. The command decoder is configured to receive an external command to generate a self-updating control signal. The semiconductor memory component performs a self-updating operation in accordance with the self-renewal control signal. The library address generator is configured to generate a target library address to each memory bank, and the target library address points to a target library to perform a self-updating operation. The self-updating counter is used to specify a target in the memory banks Update the column. The self-refreshing sequence circuit includes a temperature sensor, a reference voltage source, a comparator, a uniformity circuit, and an oscillating circuit. The temperature sensor is configured to generate a voltage proportional to a sensing temperature. The reference voltage source is used to generate a fixed voltage that is independent of the sensed temperature. The comparator is configured to compare the voltage from the temperature sensor with the fixed voltage to generate a comparison signal. The enable circuit is operative to generate a consistent energy signal to actuate the comparator. The oscillating circuit is configured to generate a self-update clock signal according to the comparison signal and the enable signal, and the self-updating clock signal controls an operating frequency of the library address generator and the self-updating counter. The enable circuit generates the enable signal when at least one update column of all memory banks completes the self-updating operation.

Another embodiment of the semiconductor memory device of the present invention includes a command decoder, a plurality of memory banks, a bank address generator, a self-updating counter, and a self-updating sequential circuit. The command decoder is configured to receive an external command to generate a self-updating control signal. The semiconductor memory component performs a self-updating operation in accordance with the self-renewal control signal. The library address generator is configured to generate a target library address to each memory bank, and the target library address points to a target library to perform a self-updating operation. The self-updating counter is used to specify a target update column in the memory banks. The self-refreshing sequence circuit includes a temperature sensor, a reference voltage source, a comparator, a uniform energy clock circuit, and an oscillating circuit. The temperature sensor is configured to generate a voltage proportional to a sensing temperature. The reference voltage source is used to generate a fixed voltage that is independent of the sensed temperature. The comparator is configured to compare the voltage from the temperature sensor with the fixed voltage to generate a comparison signal. The enable clock circuit is configured to generate a uniform energy signal to actuate according to a fixed time interval The comparator. The oscillating circuit is configured to generate a self-refreshing clock signal according to the comparison signal and the enable signal. The self-update clock signal controls the operating frequency of the library address generator and the self-updating counter.

1 shows a block diagram of a semiconductor memory device 10 incorporating an embodiment of the present invention, wherein the semiconductor memory device 10 includes a self-updating controller 12 to adjust the update period of the memory device 10. The self-updating controller 12 can adjust the update frequency of an update clock signal SCLK, and the update clock signal SCLK is used to control the operating frequency of the update counter.

Referring to Figure 1, the semiconductor memory device 10 includes a plurality of banks of memory, each memory bank having a plurality of memory cells (not shown). For the sake of brevity, FIG. 1 illustrates a semiconductor memory device 10 having four memory banks 24A, 24B, 24C, and 24D as an example. However, the present invention is equally applicable to semiconductor memory elements having a plurality of memory banks.

Referring to FIG. 1, the self-updating controller 12 includes a command decoder 122 and a self-updating sequence circuit 124. The command decoder 122 receives a plurality of external command and clock signals from a memory controller 11 during operation of the memory component 10, and generates a plurality of control and timing signals to control the components 12-24. For example, when receiving a self-updating command from the memory controller 11, the command decoder 122 issues a self-updating control signal SRF. The memory component 10 performs a self-updating operation based on the self-update control signal SRF.

Referring to FIG. 1, after receiving the self-update control signal SRF, the self-update timing circuit 124 generates the update clock signal SCLK to control a location. The address generator 14 and a self-updating counter 16. The self-updating counter 16 is used to generate a target column address to indicate a column to be updated. The library address generator 14 is configured to generate a target library address to indicate that a particular library containing one of the columns to be updated is included.

Referring to FIG. 1, a bit latch 22 receives a plurality of external addresses ADD and a plurality of external bank addresses BA from the memory controller 11, and generates a column address RADD to a column address multiplexer 20. And a bank address ABA to a bank control logic circuit 18. The column address multiplexer 20 is actuated by the self-update control signal SRF from the command decoder 122, receives the column address RADD in a normal mode operation, and receives a self-update mode operation. The self-update column address SRA is used to generate an internal column address IRA.

The bank control logic circuit 18 is actuated by the self-updating control signal SRF from the command decoder 122 for receiving the bank address ABA and a self-updating library address SBA. When the control signal SRF is at a low logic level, the bank address ABA is transmitted by the circuit 18 as an internal bank address IBA. When the control signal SRF is at a high logic level, the self-updating library address SBA is transmitted by the circuit 18 as the internal bank address IBA.

2 shows a detailed circuit diagram of the self-refresh counter 16 in connection with an embodiment of the present invention. Referring to FIG. 2, the self-updating counter 16 includes a column of up-counters 162 and a column of address counters 164. The column increment counter 162 is used to increment the column address counter 164 when the self-updating mode is operational. The column address counter 164 outputs a target column address to indicate a column to be updated. The column address counter 164 will point to the same column in all of the memory banks 24A, 24B, 24C, and 24D.

3 is a timing chart showing the operation of the semiconductor memory device 10 having the self-renewal controller 12 in accordance with an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2 for the following description. It is assumed that the bank addresses of the memory banks 24A, 24B, 24C, and 24D are 00, 01, 10, and 11, respectively. Referring to FIG. 3, upon receiving a self-updating command from the memory controller 11, the command decoder 122 issues a self-updating control signal SRF having a logic high level at the beginning of the time interval T1. The memory component 10 performs a self-updating operation based on the signal SRF. The self-update timing circuit 124 generates a first SCLK pulse to the bank address generator 14 and the self-updating counter 16 based on the signal SRF. When the memory component 10 performs the self-updating operation, a target column address SRA generated from the self-updating counter 16 and a target bank address SBA generated from the library address generator 14 are used to update a confirmation. One of the specific columns in the memory. In this example, a current update column address SRA having a value of 0...001 is stored in the self-updating counter 16, and a first self-updating library address SBA having a value of 00 is stored in the location. In the address generator 14. Therefore, during the time interval T1, the memory bank 24A is selected as the target bank and the columns 0...001 in the memory bank 24A are updated.

Then, a second update bank address SBA having a value of 01, a third update bank address SBA having a value of 10, and a fourth update bank address SBA having a value of 11 are respectively in a second pulse of the signal SCLK. The rising edges of the wave, a third pulse, and a fourth pulse are sequentially latched. Therefore, the memory 24B, the memory 24C, and the memory 24D are sequentially selected as the target library, and the same columns 0...001 in the different target banks 24B, 24C, and 24D are between the time intervals T2 and T4. Updated during consecutive SCLK cycles.

All memory banks 24A, 24B, 24C and 24D after 4 SCLK pulses The column 0...001 in the column will be updated. Thus, the column increment counter 162 generates a count signal cnt to the column address counter 164. Next, the count signal cnt is incremented by the column address counter 164 to move the current update column address to the next update column address. In an embodiment of the invention, an initial value stored in the column increment counter 162 is set to zero, and the column increment counter 162 increases the initial value by one after the end of the time interval T4. Therefore, the column address counter 164 updates the current update column address SRA having a value of 0...001 to the next update column address SRA having a value of 0...010. Through the approximate processing, new columns 0...010 in all banks 24A, 24B, 24C, and 24D will be updated during successive SCLK cycles.

In order to reduce the power loss of the semiconductor memory device 10 during the self-refresh operation, the update frequency of the update clock signal SCLK may vary according to different temperatures. 4 shows a circuit diagram of the self-updating sequence circuit 124 that produces a temperature dependent update clock signal SCLK in conjunction with an embodiment of the present invention. Referring to FIG. 4, the self-renewal timing circuit 124 includes a temperature sensor 1242, a reference voltage source 1244, a comparator 1246, a logic circuit 1248, and an oscillator 1250. The temperature sensor 1242 is disposed adjacent to a memory cell in the semiconductor memory device 10. The temperature sensor 1242 produces a signal V1 that is proportional to the sensed temperature. The reference voltage source 1244 produces a fixed voltage V2 that is independent of temperature. The comparator 1246 is for comparing the signals V1 and V2 and generating a signal VC based on the comparison result and the coincidence signal EN. The logic circuit 1248 generates a signal SC based on the self-update control signal SRF and the enable signal EN. The oscillator 1250 generates the updated clock signal SCLK oscillated at different predetermined frequencies according to the logic level of the signal SC.

The operation of the self-renewal timing circuit 124 is explained below. When the temperature sensed by the temperature sensor 1242 is lower than a predetermined temperature, the voltage value of the voltage V2 is higher than the voltage value of the voltage V1. After receiving the enable signal EN, the comparator 1246 outputs a signal VC having a low logic level. The logic circuit 1248 transmits a signal SC having a low logic level when the signals EN and SRF are both at a high logic level. After receiving the signal SC having the low logic level, the oscillator 1250 generates the clock signal SCLK oscillated at a lower frequency, thereby reducing the operating frequency of the library address generator 14 and the self-updating counter 16.

Referring to FIG. 4, the comparator 1246 and the logic circuit 1248 are actuated according to an enable signal EN generated by the coincidence circuit 1542. In particular, the comparator 1246 and the logic circuit 1248 are only activated when the enable circuit 1542 generates an enable signal EN having a high logic level. The enable signal EN generates a high logic level when at least one update column in all memory banks completes the self-updating operation. Figure 5 shows a timing diagram of an enable signal EN incorporating an embodiment of the present invention. Referring to FIG. 5, when the update column address SRA having a value of 0...001 is selected, and the same column 0...001 in the four memory banks 24A, 24B, 24C, and 24D are in consecutive SCLK cycles When updated, the enable signal EN transitions from a low logic level to a high logic level, thereby preparing to actuate the comparator 1246 and the logic circuit 1248. The comparator 1246 and the logic circuit 1248 are actuated after a short delay. In the present embodiment, since the comparator 1246 is only actuated by the fourth SCLK pulse, the power loss of the semiconductor memory device 10 is thereby reduced.

To further reduce the power loss of the semiconductor memory device 10, the comparator 1246 and the logic circuit 1248 are activated when two or more of the particular columns of all of the memory banks 24A, 24B, 24C, and 24D are updated. . In an embodiment of the invention, the column address counter 164 updates the current update column having a value of 0...001 when the same column 0...001 in all memory banks completes the self-updating operation. Address SRA to the next update column address SRA with a value of 0...010. The enable circuit 1542 is ready to actuate the comparator 1246 and the logic circuit 1248 when the new columns 0...010 in all memory banks complete the self-updating operation. In another embodiment of the invention, the column address counter 164 updates the current update column address SRA in a continuous manner. If each of the memory banks 24A, 24B, 24C, and 24D has 512 columns, the enable circuit 1542 may only perform self-updating operations in all columns (all 512 columns) in all memory banks. The comparator 1246 and the logic circuit 1248 are ready to be actuated.

Another embodiment of the present invention provides another method of reducing the power loss of the semiconductor memory device 10. In this embodiment, the consistent circuit is only actuated at fixed time intervals. Figure 6 shows a circuit diagram of the self-refreshing sequence circuit 124' which produces a temperature dependent update clock signal SCLK in connection with an embodiment of the present invention. Referring to FIG. 6, the self-renewal sequence circuit 124' includes a temperature sensor 1242', a reference voltage source 1244', a comparator 1246', a logic circuit 1248', an oscillator 1250', and a uniform energy clock circuit. 1543. Elements in FIG. 6 that are similar to FIG. 4 are shown with like reference numerals, and details of the circuits will not be described again.

Figure 7 shows a timing diagram when the self-renewal timing circuit 124' operates in conjunction with an embodiment of the present invention. Referring to Figures 6 and 7, the oscillator 1250' produces an oscillating signal SCLK' having a fixed 4 μs period at the beginning of the self-refresh operation. Therefore, the update operation is performed in successive SCLK cycles. In this embodiment, the enable clock circuit 1543 generates a uniform energy signal ENT, which is weekly The period is an integer multiple of the period of the oscillation signal SCLK', for example, 64 ms. Therefore, the comparator 1246' and the logic circuit 1248' are actuated once every 64 ms.

Referring to Figures 6 and 7, when the enable clock circuit 1543 first generates an enable signal ENT having a high logic level, the comparator 1246' is actuated to output a comparison signal VC'. Since the temperature sensed by the temperature sensor 1242' is above a predetermined temperature, the comparator 1246' outputs a signal VC' having a high logic level such that the clock period of the oscillating signal SCLK' remains unchanged. After 64 ms, the enable clock circuit 1543 again generates an enable signal ENT' having a high logic level such that the comparator 1246' and the logic circuit 1248' are actuated again. Since the temperature sensed by the temperature sensor 1242' is lower than the predetermined temperature at this time, the comparator 1246' outputs a signal VC' having a low logic level, so that the oscillator 1250' generates a oscillation with a longer period. Signal SCLK' (8μs in this example). Since the self-renewal operation is performed after a long period, the power loss of the semiconductor memory element 10 is thus reduced.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

10‧‧‧Semiconductor memory components

11‧‧‧ memory controller

12‧‧‧ Self-updating controller

122‧‧‧Command decoder

124‧‧‧ Self-renewal sequential circuit

1242, 1242' ‧ ‧ temperature sensor

1244, 1244' ‧ ‧ reference voltage source

1246, 1246'‧‧‧ comparator

1248, 1248'‧‧‧ logic circuit

1250, 1250'‧‧‧ oscillator

14‧‧‧Library Address Generator

1542‧‧‧Enable circuit

1543‧‧‧Enable clock circuit

16‧‧‧ Self-updating counter

162‧‧‧ column increment counter

164‧‧‧ column address counter

18‧‧‧Library Control Logic Circuit

20‧‧‧Row Address Multiplexer

22‧‧‧ address bolt

24A~24D‧‧‧ memory bank

1 is a block diagram showing the structure of a semiconductor memory device in accordance with an embodiment of the present invention; and FIG. 2 is a view showing the self-updating counter in combination with an embodiment of the present invention. FIG. 3 is a timing diagram showing the operation of the semiconductor memory device having the self-updating controller in conjunction with an embodiment of the present invention; FIG. 4 is a diagram showing a temperature-dependent update clock in combination with an embodiment of the present invention. A schematic diagram of the self-renewing timing circuit of the signal; FIG. 5 shows a timing diagram of an enable signal in connection with an embodiment of the present invention; and FIG. 6 shows the self generating a temperature-dependent updated clock signal in connection with an embodiment of the present invention. A circuit diagram for updating a sequential circuit; and FIG. 7 shows a timing diagram when the self-updating sequential circuit is operated in conjunction with an embodiment of the present invention.

10‧‧‧Semiconductor memory components

11‧‧‧ memory controller

12‧‧‧ Self-updating controller

122‧‧‧Command decoder

124‧‧‧ Self-renewal sequential circuit

14‧‧‧Library Address Generator

16‧‧‧ Self-updating counter

18‧‧‧Library Control Logic Circuit

20‧‧‧Row Address Multiplexer

22‧‧‧ address bolt

24A~24D‧‧‧ memory bank

Claims (10)

A semiconductor memory device, comprising: a command decoder for receiving an external command to generate a self-updating control signal, the semiconductor memory device performing a self-updating operation according to the self-updating control signal; a plurality of memory banks, Each memory bank has a plurality of memory cells; a library address generator for generating a target library address to each memory bank, the target library address pointing to a target library to perform a self-updating operation; a self-updating counter for specifying a target update column in the memory banks; and a self-updating sequence circuit comprising: a temperature sensor for generating a voltage proportional to a sensing temperature; a reference a voltage source for generating a fixed voltage independent of the sensing temperature; a comparator for comparing the voltage from the temperature sensor and the fixed voltage to generate a comparison signal; a uniform energy circuit for generating a coincidence signal to actuate the comparator; and an oscillating circuit for generating a self-refreshing clock signal based on the comparison signal and the enable signal, When the clock signal controlling the self-renewal repository address generator and the frequency of operation of self-renewal counter; After wherein, when all of the at least one memory database update column updated itself operation, the enable circuit generates the enable signal. The semiconductor memory component of claim 1, wherein the self-updating counter includes a column address counter and a column up counter, the column address counter is used to provide the target update column to the memory banks, and the column increment counter Used to control the column address counter. The semiconductor memory component of claim 1, wherein the enable circuit generates the enable signal to actuate the comparator when the target update column in all of the memory banks completes a self-updating operation. According to the semiconductor memory component of claim 1, wherein the target update column is updated to a new update column when the target update column in all the memory banks completes the self-update operation, and when the new update in all the memory banks After the update column completes the self-updating operation, the enable circuit generates the enable signal to actuate the comparator. According to the semiconductor memory component of claim 1, wherein the target update column is updated in a continuous manner, when the target update column is updated to the last column in the memory banks and the last column in all memory banks is completed. After the self-renewal operation, the enable circuit generates the enable signal to actuate the comparator. The semiconductor memory device of claim 1, wherein the oscillating circuit generates the self-refreshing clock signal having a first frequency when the sensing temperature is higher than a predetermined temperature, when the sensing temperature is lower than the predetermined temperature The oscillating circuit generates the self-updated clock signal having a second frequency, wherein the value of the first frequency is greater than the value of the second frequency. A semiconductor memory component comprising: a command decoder for receiving an external command to generate an self a new control signal, the semiconductor memory component performs a self-updating operation according to the self-updating control signal; a plurality of memory banks each having a plurality of memory cells; and a library address generator for generating a The target library address is to each memory bank, the target library address points to a target library to perform a self-updating operation; a self-updating counter is used to specify a target update column in the memory banks; and a self-updating The sequential circuit includes: a temperature sensor for generating a voltage proportional to a sensing temperature; a reference voltage source for generating a fixed voltage independent of the sensing temperature; and a comparator for comparing The voltage from the temperature sensor and the fixed voltage to generate a comparison signal; a uniform energy clock circuit for generating a uniform energy signal to actuate the comparator according to a fixed time interval; and an oscillating circuit for And generating a self-update clock signal according to the comparison signal and the enable signal, the self-update clock signal controlling the library address generator and the self-updating counter The operation frequency. The semiconductor memory component of claim 7, wherein the self-updating counter includes a column address counter and a column increment counter for providing the target update column to the memory banks, and the column incrementing counter Used to control the column address counter. A semiconductor memory device according to claim 7, wherein the sensing temperature is high The oscillating circuit generates the self-refreshing clock signal having a first period when the sensing temperature is lower than the predetermined temperature, and the oscillating circuit generates the self-refreshing clock having a second period a signal, wherein the first period is less than the second period. The semiconductor memory component of claim 7, wherein the enable clock circuit activates the comparator by an integer multiple of a period of the self-refreshing clock signal.