CN117614440A - Buffer circuit, chip and electronic equipment - Google Patents

Buffer circuit, chip and electronic equipment Download PDF

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Publication number
CN117614440A
CN117614440A CN202311634769.4A CN202311634769A CN117614440A CN 117614440 A CN117614440 A CN 117614440A CN 202311634769 A CN202311634769 A CN 202311634769A CN 117614440 A CN117614440 A CN 117614440A
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CN
China
Prior art keywords
current
output
circuit
voltage
field effect
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Pending
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CN202311634769.4A
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Chinese (zh)
Inventor
兰云鹏
王凯
张燚
尚林林
潘溯
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STMicroelectronics Shenzhen R&D Co Ltd
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STMicroelectronics Shenzhen R&D Co Ltd
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Priority to CN202311634769.4A priority Critical patent/CN117614440A/en
Publication of CN117614440A publication Critical patent/CN117614440A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Abstract

A buffer circuit, a chip and electronic equipment belong to the technical field of electronic circuits, and a first bias voltage is accessed through a ramp voltage output circuit, and a ramp voltage is output according to the first bias voltage; the operational amplification circuit is connected with an input signal and follows the target voltage to output an output voltage; the target voltage is the smaller voltage of the input signal and the slope voltage; therefore, when the power-on is performed, the output voltage firstly follows the slope voltage, so that the possibility of overshoot generated at the output in the starting or power-on process of the buffer circuit is reduced; the load capacity and the voltage precision of the buffer circuit are ensured, the integration level is improved, and the layout area is reduced; and the circuit has simple structure and low cost.

Description

Buffer circuit, chip and electronic equipment
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to a buffer circuit, a chip and electronic equipment.
Background
The buffer circuit is a circuit for transmitting voltage, and in the integrated circuit, the transmission of analog signals is influenced by the transmission distance, the driving load and the later-stage circuit, so that signal attenuation, fluctuation and loss are easy to generate, and larger errors occur in the analog signals received by the later-stage circuit, and the functions and the performances of the circuit are influenced; the buffer circuit can avoid the attenuation of analog signals, reduce signal errors, increase the sampling precision of signals, increase the driving capability of signals, has the characteristics of high input impedance and low output impedance, and can realize front-back stage impedance matching, voltage follow-up, low-resistance load driving and the like; buffer circuits are widely used as important application circuits in operational amplifiers in analog or digital-to-analog integrated circuit designs, and are an indispensable part of various chips.
With the development of semiconductors and integrated circuits, the size of devices is continuously reduced, the voltage and the power consumption of chips are lower and lower, and based on the great development of portable wireless equipment, high-performance sensors and high-speed high-precision communication systems, the requirements of the chips on signal acquisition are higher and higher, and the influence of loss and fluctuation generated during signal transmission on the chips is larger and higher, so that the buffer circuit has higher requirements on keeping the stability of signals, preventing power-on overshoot, precision, carrying capacity and other performance parameters.
Fig. 1 is a schematic diagram of a related buffer (buffer circuit), which includes two input ends VDD and VIN, an output end VOUT and a ground end, wherein VDD is a power supply of the circuit, and is connected with an external power supply, the VIN end is a signal input end, VOUT is a signal output end, the signal output end is fed back to another input end of the buffer, the signal output end VOUT is ensured to be consistent with the signal input end VIN through the virtual break characteristic of an operational amplifier, a voltage following function is realized, and an output signal through buffer output is consistent with an input signal, and meanwhile, the buffer circuit has a strong driving capability.
However, the buffer circuit is limited by the response speed of the circuit, and overshoot is generated in the process of starting up and powering up, which brings about larger signal amplitude loss, larger fluctuation to output, unstable output signals and serious influence on signal precision. In order to solve the problems, the related method is that the output end of the buffer circuit is connected with the filter circuit, and the output end of the buffer circuit is connected with the resistor and the capacitor to form an RC filter circuit, so that overshoot generated in output when power-on is started can be filtered; however, the use of components outside the chip to construct the RC filter greatly increases the application complexity, increases the cost, has limited application range and low integration level; the integrated RC filter circuit manufactured in the chip has higher integration level, but the integrated filter resistor and capacitor consume large layout area, so that the manufacturing cost of the chip is increased; the filter resistor is introduced in the method for constructing the filter, so that the voltage buffer loses the carrying capacity and the circuit performance is influenced; meanwhile, the input impedance of the post-stage circuit is increased due to the introduction of the filter resistor, the pole of the post-stage circuit is reduced, the stability of the circuit is influenced, and the design of the post-stage circuit is difficult.
Therefore, the related buffer circuit has the defects of power-on overshoot, large output impedance, low integration level and large layout area.
Disclosure of Invention
The purpose of the application is to provide a buffer circuit, a chip and electronic equipment, and aims to solve the problems of power-on overshoot, large output impedance, low integration level and large layout area of the related buffer circuit.
The embodiment of the application provides a buffer circuit, which comprises:
the slope voltage output circuit is configured to be connected to a first bias voltage and output the slope voltage according to the first bias voltage;
the operational amplification circuit is connected with the slope voltage output circuit, is configured to be connected with an input signal, and follows the target voltage to output an output voltage; the target voltage is the smaller voltage of the input signal and the ramp voltage.
In one embodiment, the operational amplifier circuit includes:
the input circuit is connected with the slope voltage output circuit, is configured to be connected with the input signal and outputs a first current according to the target voltage;
a first current mirror coupled to the input circuit and configured to mirror the first current to output a second current;
a feedback circuit connected to the first current mirror and configured to adjust a voltage drop generated by the second current according to a sampling voltage to output a first voltage;
a first current source connected to the input circuit and the feedback circuit and configured to provide a bus current in accordance with a second bias voltage to provide a current source for the first current and the second current;
a switching circuit coupled to the feedback circuit and the first current mirror and configured to output a third current in accordance with the first voltage;
a second current mirror connected to the switching circuit and configured to mirror the third current to output a fourth current;
and the output sampling circuit is connected with the switching circuit and the second current mirror, and is configured to output the output voltage according to the voltage drop of the fourth current, and sample the output voltage to output the sampling voltage.
In one embodiment, the input circuit includes a first field effect transistor and a second field effect transistor;
the grid electrode of the first field effect transistor is used as an input signal input end of the input circuit so as to be connected with an input signal;
the grid electrode of the second field effect transistor is used as a slope voltage input end of the input circuit and is connected with the slope voltage output circuit so as to be connected with the slope voltage;
the source electrode of the first field effect transistor and the source electrode of the second field effect transistor are used as bus current input ends of the input circuit and are connected with the first current source so as to be connected with the bus current;
the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor are used as a first current output end of the input circuit and are connected with the first current mirror so as to output the first current.
In one embodiment, the first current mirror includes a third field effect transistor and a fourth field effect transistor;
the drain electrode of the third field effect transistor, the grid electrode of the third field effect transistor and the grid electrode of the fourth field effect transistor are used as a first current input end of the first current mirror together and are connected with the input circuit so as to be connected with the first current;
the drain electrode of the fourth field effect transistor is used as a second current output end of the first current mirror and is connected with the feedback circuit so as to output the second current;
and the source electrode of the third field effect transistor and the source electrode of the fourth field effect transistor are commonly connected with the power ground.
In one embodiment, the feedback circuit includes a fifth field effect transistor;
the source electrode of the fifth field effect transistor is used as a bus current input end of the feedback circuit and is connected with the first current source so as to be connected with the bus current;
the drain electrode of the fifth field effect transistor is used as a second current input end of the feedback circuit and a first voltage output end of the feedback circuit, and is connected with the first current mirror and the switch circuit so as to be connected with the second current and output a first voltage;
and the grid electrode of the fifth field effect transistor is used as a sampling voltage input end of the feedback circuit and is connected with the output sampling circuit so as to be connected with the sampling voltage.
In one embodiment, the switching circuit includes a sixth field effect transistor;
the source electrode of the sixth field effect transistor is connected with the power ground;
the drain electrode of the sixth field effect transistor is used as a third current output end of the switching circuit and is connected with the second current mirror so as to output a third current;
and the grid electrode of the sixth field effect transistor is used as a first voltage input end of the switching circuit and is connected with the feedback circuit and the first current mirror so as to be connected with the first voltage.
In one embodiment, the second current mirror includes a seventh field effect transistor and an eighth field effect transistor;
the drain electrode of the seventh field effect transistor, the grid electrode of the seventh field effect transistor and the grid electrode of the eighth field effect transistor are used as a third current input end of the second current mirror together and are connected with the switch circuit so as to be connected with the third current;
the drain electrode of the eighth field effect transistor is used as a fourth current output end of the second current mirror and is connected with the output sampling circuit so as to output the fourth current;
and the source electrode of the seventh field effect transistor and the source electrode of the eighth field effect transistor are commonly connected with a first power supply.
In one embodiment, the output sampling circuit comprises a first resistor and a second resistor;
the first end of the first resistor is used as a fourth current input end of the output sampling circuit and an output voltage output end of the output sampling circuit and is connected with the second current mirror so as to be connected with the fourth current and output an output voltage;
the second end of the first resistor and the first end of the second resistor are used as sampling voltage output ends of the output sampling circuit together and are connected with the feedback circuit so as to output the sampling voltage;
the second end of the second resistor is connected with power ground.
In one embodiment, the first current source includes a ninth field effect transistor;
the source electrode of the ninth field effect transistor is connected with the power ground;
the grid electrode of the ninth field effect transistor is used as a second bias voltage input end of the first current source so as to be connected with the second bias voltage;
and the drain electrode of the ninth field effect transistor is used as a bus current output end of the first current source and is connected with the input circuit and the feedback circuit so as to output the bus current.
In one embodiment, the ramp voltage output circuit includes:
the second current source is configured to be connected with the first bias voltage and output charging current according to the first bias voltage;
and the energy storage circuit is connected with the second current source and the operational amplification circuit and is configured to charge according to the charging current so as to output a slope voltage.
In one embodiment, the second current source is specifically configured to access the first bias voltage and the switching signal, and output a charging current according to the first bias voltage and the switching signal.
In one embodiment, the second current source includes n first switching tubes and n second switching tubes;
the drain electrode of the ith first switching tube is connected with the source electrode of the ith second switching tube;
the sources of the n first switching tubes are commonly connected with a first power supply;
the grid electrodes of the n first switching tubes are used as first bias voltage input ends of the second current sources together so as to be connected with the first bias voltages;
the drains of the n second switching tubes are used as charging current output ends of the second current sources together so as to output the charging currents;
the grid electrodes of the n second switching tubes are jointly used as switching signal input ends of the second current sources so as to be connected with the switching signals;
wherein n is an integer greater than 1, and i is a positive integer less than or equal to n.
In one embodiment, the second current source includes a third switching tube;
the source electrode of the third switching tube is connected with a first power supply;
the grid electrode of the third switching tube is used as a first bias voltage input end of the second current source so as to be connected with the first bias voltage;
and the drain electrode of the third switching tube is used as a charging current output end of the second current source so as to output the charging current.
The embodiment of the invention also provides a chip, which comprises the buffer circuit.
The embodiment of the invention also provides electronic equipment, which comprises the buffer circuit.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: the slope voltage output circuit is connected with the first bias voltage and outputs the slope voltage according to the first bias voltage; the operational amplification circuit is connected with an input signal and follows the target voltage to output an output voltage; the target voltage is the smaller voltage of the input signal and the slope voltage; therefore, when the power-on is performed, the output voltage firstly follows the slope voltage, so that the possibility of overshoot generated at the output in the starting or power-on process of the buffer circuit is reduced; the load capacity and the voltage precision of the buffer circuit are ensured, the integration level is improved, and the layout area is reduced; and the circuit has simple structure and low cost.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic diagram of a related buffer circuit;
FIG. 2 is a schematic diagram of a buffer circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of an operational amplifier circuit in a buffer circuit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a configuration of a ramp voltage output circuit in a buffer circuit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a portion of an exemplary circuit of a snubber circuit provided in an embodiment of the present application;
FIG. 6 is a schematic diagram of another example circuit of a portion of a snubber circuit provided in an embodiment of the present application;
fig. 7 is a signal waveform diagram of a buffer circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 2 is a schematic diagram of a buffer circuit according to a preferred embodiment of the present application, and for convenience of explanation, only the portion related to the present embodiment is shown, which is described in detail below:
the buffer circuit includes a ramp voltage output circuit 01 and an operational amplifier circuit 02.
The ramp voltage output circuit 01 is configured to switch in the first bias voltage Vb1 and output a ramp voltage Vx according to the first bias voltage Vb 1.
An operational amplifier circuit 02, connected to the second current source 11 and the tank circuit 12, configured to be connected to the input signal SIG and follow the target voltage to output an output voltage VOUT; the target voltage is the smaller of the voltage of the input signal SIG and the ramp voltage Vx.
The ramp voltage Vx is a voltage with a fixed rising slope.
As shown in fig. 3, the operational amplification circuit 02 includes an input circuit 21, a first current mirror 22, a feedback circuit 23, a first current source 24, a switching circuit 25, a second current mirror 26, and an output sampling circuit 27.
The input circuit 21 is connected to the ramp voltage output circuit 01, configured to be connected to the input signal SIG, and output a first current according to a target voltage.
A first current mirror 22, coupled to the input circuit 21, is configured to mirror the first current to output a second current.
And a feedback circuit 23 connected to the first current mirror 22 and configured to adjust a voltage drop generated by the second current according to the sampling voltage VFB, so as to output a first voltage.
A first current source 24, coupled to the input circuit 21 and the feedback circuit 23, is configured to provide a bus current in accordance with the second bias voltage to provide a current source for the first current and the second current.
The switching circuit 25, connected to the feedback circuit 23 and the first current mirror 22, is configured to output a third current according to the first voltage.
A second current mirror 26, connected to the switching circuit 25, is configured to mirror the third current to output a fourth current.
An output sampling circuit 27, connected to the switching circuit 25 and the second current mirror 26, configured to output an output voltage VOUT according to a voltage drop of the fourth current, and sample the output voltage VOUT to output a sampling voltage VFB.
The output sampling circuit 27 is used for sampling the output voltage VOUT to output a sampling voltage VFB, and feeding back the sampling voltage VFB to the feedback circuit 23, so that the feedback circuit 23 regulates the voltage drop generated by the second current according to the sampling voltage VFB to output a first voltage, the switch circuit 25 outputs a third current according to the first voltage, the second current mirror 26 mirrors the third current to output a fourth current, the output sampling circuit 27 outputs the output voltage VOUT according to the voltage drop of the fourth current, a negative feedback loop of the output voltage is established, and stable output of the output voltage is realized; meanwhile, the input circuit 21 outputs a first current according to the target voltage; the first current mirror 22 mirrors the first current to output a second current; therefore, it is realized that the operational amplifier circuit 02 follows the target voltage, which is the minimum value of the voltage of the input signal SIG and the ramp voltage Vx, so that it is realized that the output voltage will follow the smaller voltage variation in the voltage of the input signal SIG and the ramp voltage Vx.
As shown in fig. 4, the ramp voltage output circuit 01 includes a second current source 11 and a tank circuit 12.
The second current source 11 is configured to switch in the first bias voltage Vb1 and output a charging current according to the first bias voltage Vb 1.
And a tank circuit 12 connected to the second current source 11 and the operational amplifier circuit 02 and configured to be charged according to the charging current to output a ramp voltage Vx.
The ramp voltage Vx is output through the second current source 11 and the energy storage circuit 12, so that the circuit is simple and reliable, and the output stability is high.
In particular, the second current source 11 is specifically configured to switch in the first bias voltage Vb1 and the switching signal, and output the charging current according to the first bias voltage Vb1 and the switching signal.
The second current source 11 outputs charging current according to the first bias voltage Vb1 and the switch signal, and charging currents with different magnitudes can be obtained by adjusting the switch signal, so that the slope of the ramp voltage Vx is adjustable.
Fig. 5 shows a partial example circuit structure of a buffer circuit provided by an embodiment of the present invention, fig. 6 shows another partial example circuit structure of a buffer circuit provided by an embodiment of the present invention, and for convenience of explanation, only the portions related to the embodiment of the present invention are shown, and the details are as follows:
as shown in fig. 5 and 6, the input circuit 21 includes a first fet M1 and a second fet M2; the gate of the first field effect transistor M1 is used as an input signal input end of the input circuit 21 to be connected with the input signal SIG; the grid electrode of the second field effect transistor M2 is used as a slope voltage input end of the input circuit 21 and is connected with the slope voltage output circuit 01 so as to be connected with the slope voltage Vx; the source electrode of the first field effect transistor M1 and the source electrode of the second field effect transistor M2 are used as bus current input ends of the input circuit 21 and are connected with the first current source 24 so as to be connected with bus current; the drain of the first fet M1 and the drain of the second fet M2 are connected to the first current mirror 22 as the first current output terminal of the input circuit 21 to output the first current.
As shown in fig. 5 and 6, the first current mirror 22 includes a third fet M3 and a fourth fet M4; the drain electrode of the third field effect transistor M3, the grid electrode of the third field effect transistor M3 and the grid electrode of the fourth field effect transistor M4 are used as a first current input end of the first current mirror 22 together and are connected with the input circuit 21 so as to be connected with first current; the drain electrode of the fourth field effect transistor M4 is used as a second current output end of the first current mirror 22 and is connected with the feedback circuit 23 so as to output a second current; the source of the third fet M3 and the source of the fourth fet M4 are commonly connected to the power ground.
As shown in fig. 5 and 6, the feedback circuit 23 includes a fifth fet M5; the source electrode of the fifth field effect transistor M5 is used as a bus current input end of the feedback circuit 23 and is connected with the first current source 24 so as to be connected with bus current; the drain electrode of the fifth field effect transistor M5 is used as a second current input end of the feedback circuit 23 and a first voltage output end of the feedback circuit 23, and is connected with the first current mirror 22 and the switch circuit 25 to access the second current and output the first voltage; the gate of the fifth fet M5 is connected to the output sampling circuit 27 as a sampling voltage input terminal of the feedback circuit 23 to be connected to the sampling voltage VFB.
As shown in fig. 5 and 6, the switching circuit 25 includes a sixth field effect transistor M6; the source electrode of the sixth field effect transistor M6 is connected with the power ground; the drain electrode of the sixth field effect transistor M6 is used as a third current output end of the switching circuit 25 and is connected with the second current mirror 26 to output a third current; the gate of the sixth fet M6 is connected to the feedback circuit 23 and the first current mirror 22 as a first voltage input terminal of the switching circuit 25 to be connected to the first voltage.
As shown in fig. 5 and 6, the second current mirror 26 includes a seventh fet M7 and an eighth fet M8; the drain electrode of the seventh field effect transistor M7, the gate electrode of the seventh field effect transistor M7 and the gate electrode of the eighth field effect transistor M8 are used as a third current input end of the second current mirror 26 together and are connected with the switch circuit 25 so as to be connected with a third current; the drain electrode of the eighth field effect transistor M8 is used as a fourth current output end of the second current mirror 26 and is connected with the output sampling circuit 27 so as to output a fourth current; the source of the seventh fet M7 and the source of the eighth fet M8 are commonly connected to the first power supply VDD.
As shown in fig. 5 and 6, the output sampling circuit 27 includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is used as a fourth current input end of the output sampling circuit 27 and an output voltage output end of the output sampling circuit 27, and is connected with the second current mirror 26 to access a fourth current and output an output voltage VOUT; the second end of the first resistor R1 and the first end of the second resistor R2 are used together as a sampling voltage output end of the output sampling circuit 27, and are connected with the feedback circuit 23 to output a sampling voltage VFB; the second terminal of the second resistor R2 is connected to power ground.
As shown in fig. 5 and 6, the first current source 24 includes a ninth fet M9;
the source electrode of the ninth field effect transistor M9 is connected with power ground; the gate of the ninth fet M9 is used as the second bias voltage input terminal of the first current source 24 to be connected to the second bias voltage VB2; the drain of the ninth fet M9 is connected to the input circuit 21 and the feedback circuit 23 as a bus current output terminal of the first current source 24 to output a bus current.
As shown in fig. 5 and 6, the tank circuit 12 includes a first capacitor C1;
a first end of the first capacitor C1 is used as a charging current input end of the tank circuit 12 and a ramp voltage output end of the tank circuit 12, and is connected with the second current source 11 and the operational amplifier circuit 02 to access charging current and output a ramp voltage Vx; the second terminal of the first capacitor C1 is connected to the power ground.
The energy storage circuit 12 is used for storing charges, ensuring that the rising slope of the voltage at the upper end of the first capacitor C1 is constant when the charging current is constant, providing a ramp voltage Vx which rises from zero and has constant rising slope to the second field effect transistor M2, and continuously increasing the ramp voltage Vx after the output voltage reaches a predetermined value, so that the voltage is close to the power supply voltage (the voltage of the first power supply VDD) to turn off the second field effect transistor M2 without affecting the signal output of the buffer circuit.
As shown in fig. 5, the second current source 11 includes n first switching transistors Q1i and n second switching transistors Q2i.
The drain electrode of the ith first switching tube Q1i is connected with the source electrode of the ith second switching tube Q2 i; the sources Q1i of the n first switching tubes are commonly connected with a first power supply VDD; the grid electrodes of the n first switching tubes Q1i are commonly used as a first bias voltage input end of the second current source 11 so as to be connected with a first bias voltage Vb1; the drains of the n second switching tubes Q2i are commonly used as the charging current output ends of the second current source 11 to output charging current; the gates of the n second switching transistors Q2i are commonly used as the switching signal input terminals of the second current source 11 to access the switching signals. Wherein n is an integer greater than 1, and i is a positive integer less than or equal to n.
The ith first switching tube Q1i forms a sub-current source, any sub-current source in a plurality of sub-current sources which are connected in parallel can be opened through n second switching tubes Q2i, and the flexibility of regulating the output slope of the buffer circuit is improved.
By connecting a plurality of sub-current sources in parallel, wherein the width-to-length ratio of the (i+1) th first switching tube Q1i+1 is 2 times that of the (i) th first switching tube Q1i, 0 to (2) is realized n -1) regulation of charging current in the I range, wherein the minimum step size is I.
The second current source is used for generating a charging current with a fixed magnitude so as to maintain a rising slope of a certain ramp voltage Vx, and the magnitude of the charging current can be controlled by a second switch tube Q2i switch. The working principle is as follows: generating a plurality of branch currents through n first switching tubes Q1i, wherein each branch current corresponds to one second switching tube Q2i, controlling the on and off of the second switching tube Q2i can control the connected current branch,thereby controlling the magnitude of the input charging current, injecting a capacitor to generate a slope of a fixed ramp voltage Vx, and generating different slopes of different input charging currents; the second current source 11 can generate n paths of current, each path of current is arranged in a binary multiple of the minimum current, and 2 is added in total n Seed switch selection, ultimately yielding 2 n Seed current output, output current is 0-2 n -within a minimum unit current range of 1 times, the magnitudes are all multiples of the minimum unit current;
in the following description, four-way current is taken as an example.
The proportion of the generated current is controlled by controlling the size of the four first switching tubes, each first switching tube generates one path of current, the proportion of the four first switching tubes (Q11-Q14) is 1:2:4:8, the proportion of the generated current through the four first switching tubes Q1i is 1:2:4:8, the specific size of the generated current depends on the provided first bias voltage Vb1, and the first bias voltage is generally generated by an externally provided reference voltage; the charging current to the tank circuit 12 is controlled by n second switching transistors Q2i.
The n second switching tubes Q2i are used for controlling the magnitude of the charging current connected to the energy storage circuit 12, each second switching tube Q2i is connected in series with the corresponding first switching tube Q1i, that is, each second switching tube Q2i corresponds to one current, and the input total current can be controlled by controlling the opening and closing of different second switching tubes Q2 i; the four second switching tubes Q21-Q24 are controlled by switching signals, wherein the switching signals comprise n control signals (S1-S4) for controlling four paths of currents generated by the four first switching tubes Q11-Q14 correspondingly; in this example, the four paths of currents are arranged according to a binary multiple of the minimum current, the charging current is equal to the product of decimal corresponding to the binary arrangement of n control signals S4-S1 and the minimum unit current, for example, when the minimum unit current is I and the binary number corresponding to n control signals S4-S1 is 1100, the corresponding total current is the sum of the currents of the third branch and the fourth branch, and the magnitude is 8i+4i, namely 12I, and the decimal number corresponding to 1100 is consistent with the product of 12 times the minimum unit current; the input current combination with the size of I-15I can be obtained by selecting four paths of access currents.
As shown in fig. 6, the second current source 11 includes a third switching transistor Q3.
The source electrode of the third switching tube Q3 is connected with a first power supply VDD; the grid electrode of the third switching tube Q3 is used as a first bias voltage input end of the second current source 11 to be connected with a first bias voltage Vb1; the drain of the third switching tube Q3 serves as a charging current output terminal of the second current source 11 to output a charging current.
The second current source 11 is implemented by a single switching tube, and the charging current can be changed by adjusting the magnitude of the first bias voltage Vb1, so that the circuit is simple and reliable.
The following further describes the operation of the device shown in fig. 5 and 6:
in fig. 5, the operational amplifier circuit 02 is used for comparing the target voltage with the sampling voltage VFB, and the sampling voltage VFB is adjusted to be consistent with the target voltage through the feedback network.
The feedback network includes a first resistor R1 and a second resistor R2, which are used for sampling the output voltage and feeding it back to the feedback circuit 23, and the output voltages with different magnitudes can be obtained by adjusting the ratio of the resistors in the feedback network, and vout= (1+r1/R2) vfb=k·vfb, K is the feedback coefficient.
The buffer circuit is electrified and started, n first switching tubes Q1i generate n currents which are arranged in a binary multiple mode according to the first bias voltage Vb1, n second switching tubes Q2i control whether n branch currents are connected into the first capacitor C1 or not, and the input total current (charging current) is equal to the sum of currents of the selected connected branches. When the power-on is started, no charge exists on the first capacitor C1, the upper polar plate voltage is zero, the gate end voltage of the second field effect transistor M2 is zero, and the sampling voltage VFB will follow the minimum voltage change of the two ramp voltages Vx and the voltage of the input signal SIG because the second field effect transistor M2 is connected in parallel with the input tube (the first field effect transistor M1) of the input signal SIG.
When the second field effect transistor M2 is powered on, the input of the second field effect transistor M2 is zero, the sampling voltage VFB follows the ramp voltage Vx, the output voltage VOUT is also zero, after the buffer circuit is powered on, the second switching transistor Q2I is turned on, the second current source 11 will generate a current with a fixed magnitude to charge the first capacitor C1, the upper plate voltage of the first capacitor C1 rises with a fixed slope, and according to cv=it (where C is the capacitance value of the first capacitor; the ramp voltage Vx of V; I is the charging current; T is the charging duration), the rising slope of the ramp voltage Vx is I/C.
In the buffer time when the ramp voltage Vx does not reach the voltage of the input signal SIG, the sampling voltage VFB will follow the ramp voltage Vx, i.e. rise from zero with the same slope, the output voltage is VFB which is K times as high as the output voltage, and also rise with a fixed slope, the rising slope of the ramp voltage Vx which is K times as high as the rising slope, i.e. KI/C, and the required rising slope and buffer time of the output signal can be obtained by controlling the input current, the proportion of the feedback resistor (the first resistor R1 and the second resistor R2), the size of the first capacitor C1 and different switching signals.
When the voltage (ramp voltage Vx) on the first capacitor C1 reaches the voltage of the input signal SIG, the ramp voltage Vx is equal to the voltage of the input signal SIG, VFB is equal to the input voltage, and since the second switching tube is still turned on, the second current source 11 continuously charges the first capacitor C1, the upper plate voltage of the first capacitor C1 continuously rises, the ramp voltage Vx continuously rises and is no longer smaller than the voltage of the input signal SIG, the voltage of the input signal SIG becomes the smaller voltage of the two input voltages, the sampling voltage VFB does not change along with the ramp voltage Vx, and begins to follow the voltage of the input signal SIG, namely, the output begins to follow the input signal SIG after slowly rising for a period of time, so that overshoot generated in the power-on process of the output is avoided, and the stability of the output signal is ensured.
After the output voltage VOUT follows the voltage of the input signal SIG, the second switching tube Q2i is not immediately turned off, the second current source 11 continues to charge the first capacitor C1, so that the voltage of the upper plate of the capacitor continuously rises, the ramp voltage Vx continuously rises, the opening degree of the second field effect tube M2 continuously decreases, the voltage of the upper plate of the capacitor reaches the turn-off voltage of the second field effect tube M2, the second field effect tube M2 is turned off, as the voltage of the upper plate of the capacitor approaches the power voltage, the current source tube enters the linear region, the output current is slowly reduced until zero, the second current source 11 stops charging the first capacitor C1, and the ramp voltage output circuit 01 and the second field effect tube M2 are turned off after completing the functions, so that the operation of the buffer circuit is not affected.
Note that, the snubber circuit in fig. 6 is different from the snubber circuit in fig. 5 only in the point that the second current source 11, the second current source 11 in fig. 6, is implemented by the third switching transistor Q3, and the third switching transistor Q3 outputs a charging current according to the first bias voltage Vb1 to charge the first capacitor C1. The remaining circuit fig. 6 is the same as fig. 5, and will not be described again here.
Fig. 7 is an output waveform diagram of the buffer circuit of the present application, where at time 0, the ramp voltage Vx is zero, which is smaller than the voltage of the input signal SIG, and the output voltage VOUT follows the ramp voltage Vx; at the time 0 to T, the ramp voltage Vx rises with a certain slope, still smaller than the voltage of the input signal SIG, the output voltage VOUT changes along with the ramp voltage Vx, according to the analysis, the rising slope of the ramp is I/C, and the rising slope of the output voltage VOUT is KI/C; at time T, the ramp voltage Vx is equal to the voltage of the input signal SIG, and the rising buffer time T is V SIG C/I (wherein V SIG For the voltage of the input signal SIG), different input currents and the size of the first capacitor C1 can be designed according to different input signals SIG to obtain a desired buffer time; after the time T, the ramp voltage Vx is greater than the voltage of the input signal SIG, the output voltage VOUT starts to follow the voltage change of the input signal SIG, the ramp voltage Vx continues to rise, but the output voltage is not affected any more, until the ramp voltage Vx rises to the voltage of the first power supply, and the second fet M2 is completely turned off.
The embodiment of the invention also provides a chip, which comprises the buffer circuit.
The buffer circuit has small application limit and wide application range, and can be applied to an operational amplifier chip, a linear power supply chip, a reference chip and the like.
The embodiment of the invention also provides electronic equipment which comprises the buffer circuit.
For example, the buffer circuit may also be applied in a signal acquisition system or the like.
According to the embodiment of the invention, the first bias voltage is accessed through the slope voltage output circuit, and the slope voltage is output according to the first bias voltage; the operational amplification circuit is connected with an input signal and follows the target voltage to output an output voltage; the target voltage is the smaller voltage of the input signal and the slope voltage; therefore, when the power-on is performed, the output voltage firstly follows the slope voltage, so that the possibility of overshoot generated at the output in the starting or power-on process of the buffer circuit is reduced; the load capacity and the voltage precision of the buffer circuit are ensured, the integration level is improved, and the layout area is reduced; and the circuit has simple structure and low cost.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (15)

1. A snubber circuit, comprising:
the slope voltage output circuit is configured to be connected to a first bias voltage and output the slope voltage according to the first bias voltage;
the operational amplification circuit is connected with the slope voltage output circuit, is configured to be connected with an input signal, and follows the target voltage to output an output voltage; the target voltage is the smaller voltage of the input signal and the ramp voltage.
2. The buffer circuit of claim 1, wherein the operational amplification circuit comprises:
the input circuit is connected with the slope voltage output circuit, is configured to be connected with the input signal and outputs a first current according to the target voltage;
a first current mirror coupled to the input circuit and configured to mirror the first current to output a second current;
a feedback circuit connected to the first current mirror and configured to adjust a voltage drop generated by the second current according to a sampling voltage to output a first voltage;
a first current source connected to the input circuit and the feedback circuit and configured to provide a bus current in accordance with a second bias voltage to provide a current source for the first current and the second current;
a switching circuit coupled to the feedback circuit and the first current mirror and configured to output a third current in accordance with the first voltage;
a second current mirror connected to the switching circuit and configured to mirror the third current to output a fourth current;
and the output sampling circuit is connected with the switching circuit and the second current mirror, and is configured to output the output voltage according to the voltage drop of the fourth current, and sample the output voltage to output the sampling voltage.
3. The buffer circuit of claim 2, wherein the input circuit comprises a first field effect transistor and a second field effect transistor;
the grid electrode of the first field effect transistor is used as an input signal input end of the input circuit so as to be connected with an input signal;
the grid electrode of the second field effect transistor is used as a slope voltage input end of the input circuit and is connected with the slope voltage output circuit so as to be connected with the slope voltage;
the source electrode of the first field effect transistor and the source electrode of the second field effect transistor are used as bus current input ends of the input circuit and are connected with the first current source so as to be connected with the bus current;
the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor are used as a first current output end of the input circuit and are connected with the first current mirror so as to output the first current.
4. The buffer circuit of claim 2, wherein the first current mirror comprises a third field effect transistor and a fourth field effect transistor;
the drain electrode of the third field effect transistor, the grid electrode of the third field effect transistor and the grid electrode of the fourth field effect transistor are used as a first current input end of the first current mirror together and are connected with the input circuit so as to be connected with the first current;
the drain electrode of the fourth field effect transistor is used as a second current output end of the first current mirror and is connected with the feedback circuit so as to output the second current;
and the source electrode of the third field effect transistor and the source electrode of the fourth field effect transistor are commonly connected with the power ground.
5. The buffer circuit of claim 2, wherein the feedback circuit comprises a fifth field effect transistor;
the source electrode of the fifth field effect transistor is used as a bus current input end of the feedback circuit and is connected with the first current source so as to be connected with the bus current;
the drain electrode of the fifth field effect transistor is used as a second current input end of the feedback circuit and a first voltage output end of the feedback circuit, and is connected with the first current mirror and the switch circuit so as to be connected with the second current and output a first voltage;
and the grid electrode of the fifth field effect transistor is used as a sampling voltage input end of the feedback circuit and is connected with the output sampling circuit so as to be connected with the sampling voltage.
6. The buffer circuit of claim 2, wherein the switching circuit comprises a sixth field effect transistor;
the source electrode of the sixth field effect transistor is connected with the power ground;
the drain electrode of the sixth field effect transistor is used as a third current output end of the switching circuit and is connected with the second current mirror so as to output a third current;
and the grid electrode of the sixth field effect transistor is used as a first voltage input end of the switching circuit and is connected with the feedback circuit and the first current mirror so as to be connected with the first voltage.
7. The buffer circuit of claim 2, wherein the second current mirror comprises a seventh field effect transistor and an eighth field effect transistor;
the drain electrode of the seventh field effect transistor, the grid electrode of the seventh field effect transistor and the grid electrode of the eighth field effect transistor are used as a third current input end of the second current mirror together and are connected with the switch circuit so as to be connected with the third current;
the drain electrode of the eighth field effect transistor is used as a fourth current output end of the second current mirror and is connected with the output sampling circuit so as to output the fourth current;
and the source electrode of the seventh field effect transistor and the source electrode of the eighth field effect transistor are commonly connected with a first power supply.
8. The buffer circuit of claim 2, wherein the output sampling circuit comprises a first resistor and a second resistor;
the first end of the first resistor is used as a fourth current input end of the output sampling circuit and an output voltage output end of the output sampling circuit and is connected with the second current mirror so as to be connected with the fourth current and output an output voltage;
the second end of the first resistor and the first end of the second resistor are used as sampling voltage output ends of the output sampling circuit together and are connected with the feedback circuit so as to output the sampling voltage;
the second end of the second resistor is connected with power ground.
9. The buffer circuit of claim 2, wherein the first current source comprises a ninth field effect transistor;
the source electrode of the ninth field effect transistor is connected with the power ground;
the grid electrode of the ninth field effect transistor is used as a second bias voltage input end of the first current source so as to be connected with the second bias voltage;
and the drain electrode of the ninth field effect transistor is used as a bus current output end of the first current source and is connected with the input circuit and the feedback circuit so as to output the bus current.
10. A buffer circuit as claimed in any one of claims 1 to 9, wherein the ramp voltage output circuit comprises:
the second current source is configured to be connected with the first bias voltage and output charging current according to the first bias voltage;
and the energy storage circuit is connected with the second current source and the operational amplification circuit and is configured to charge according to the charging current so as to output a slope voltage.
11. The buffer circuit of claim 10, wherein the second current source is specifically configured to tap in the first bias voltage and the switching signal and output a charging current in accordance with the first bias voltage and the switching signal.
12. The buffer circuit of claim 11, wherein the second current source comprises n first switching tubes and n second switching tubes;
the drain electrode of the ith first switching tube is connected with the source electrode of the ith second switching tube;
the sources of the n first switching tubes are commonly connected with a first power supply;
the grid electrodes of the n first switching tubes are used as first bias voltage input ends of the second current sources together so as to be connected with the first bias voltages;
the drains of the n second switching tubes are used as charging current output ends of the second current sources together so as to output the charging currents;
the grid electrodes of the n second switching tubes are jointly used as switching signal input ends of the second current sources so as to be connected with the switching signals;
wherein n is an integer greater than 1, and i is a positive integer less than or equal to n.
13. The buffer circuit of claim 10, wherein the second current source comprises a third switching tube;
the source electrode of the third switching tube is connected with a first power supply;
the grid electrode of the third switching tube is used as a first bias voltage input end of the second current source so as to be connected with the first bias voltage;
and the drain electrode of the third switching tube is used as a charging current output end of the second current source so as to output the charging current.
14. A chip comprising a buffer circuit according to any one of claims 1 to 13.
15. An electronic device comprising a buffer circuit as claimed in any one of claims 1 to 13.
CN202311634769.4A 2023-11-30 2023-11-30 Buffer circuit, chip and electronic equipment Pending CN117614440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311634769.4A CN117614440A (en) 2023-11-30 2023-11-30 Buffer circuit, chip and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311634769.4A CN117614440A (en) 2023-11-30 2023-11-30 Buffer circuit, chip and electronic equipment

Publications (1)

Publication Number Publication Date
CN117614440A true CN117614440A (en) 2024-02-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311634769.4A Pending CN117614440A (en) 2023-11-30 2023-11-30 Buffer circuit, chip and electronic equipment

Country Status (1)

Country Link
CN (1) CN117614440A (en)

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