CN117611977B - Signal processing circuit in visual recognition system - Google Patents
Signal processing circuit in visual recognition system Download PDFInfo
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- CN117611977B CN117611977B CN202410093030.5A CN202410093030A CN117611977B CN 117611977 B CN117611977 B CN 117611977B CN 202410093030 A CN202410093030 A CN 202410093030A CN 117611977 B CN117611977 B CN 117611977B
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- 230000000007 visual effect Effects 0.000 title claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 230000002708 enhancing effect Effects 0.000 claims abstract description 3
- 239000003990 capacitor Substances 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/94—Hardware or software architectures specially adapted for image or video understanding
- G06V10/955—Hardware or software architectures specially adapted for image or video understanding using specific electronic processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/20—Image preprocessing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/20—Image preprocessing
- G06V10/25—Determination of region of interest [ROI] or a volume of interest [VOI]
Abstract
The invention discloses a signal processing circuit in a visual identification system, which comprises a marking unit, a processing circuit and a conversion unit, wherein the marking unit is connected with the processing circuit, the processing circuit is connected with the conversion unit, the marking unit is used for marking and converting interesting features in an image, the processing circuit is used for selectively enhancing the image based on marking signals, and the conversion unit is used for receiving signals fed back by the processing circuit and converting the signals.
Description
Technical Field
The invention relates to the field of visual identification, in particular to a signal processing circuit in a visual identification system.
Background
Along with the development of industry automation, the visual recognition system is widely applied to various fields, provides more efficient production and better product quality for enterprises and users, enhances the contrast between the image signal and the pixels with the interesting features in the image after the image signal is acquired, and facilitates the work expansion of other working modules in the recognition system.
Disclosure of Invention
Aiming at the technical problems, the invention aims to provide a signal processing circuit in a visual recognition system, which comprises a marking unit, a processing circuit and a conversion unit, wherein the marking unit is connected with the processing circuit, the processing circuit is connected with the conversion unit, the marking unit is used for marking and signal conversion of interesting features in an image, the processing circuit is used for selectively enhancing the image based on marking signals, the conversion unit is used for receiving signals fed back by the processing circuit and carrying out signal conversion on the signals, so as to facilitate the work expansion of other working modules in the visual recognition system, the processing circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first diode D1, a first MOS tube Q1, a first connecting terminal P1 and a second connecting terminal P2, the same phase end of a first operational amplifier U1 is connected with the first connecting terminal P1, the reverse end of the first operational amplifier U1 is connected with one end of a first resistor R1, the output end of the first operational amplifier U1 is connected with the other end of the first resistor R1, one end of a second resistor R2 is connected with a power supply, one end of a third resistor R3 is connected with the other end of the second resistor R2, the in-phase end of the second operational amplifier U2 is connected between the output end of the first operational amplifier U1 and the first resistor R1, one end of a fourth resistor R4 is connected with the in-phase end of the second operational amplifier U2, the reverse end of the second operational amplifier U2 is connected between the second resistor R2 and the third resistor R3, the source electrode of the first MOS tube Q1 is connected between the in-phase end of the second operational amplifier U2 and the fourth resistor R4, the drain electrode of the first MOS tube Q1 is connected with one end of a fifth resistor R5, the anode electrode of the first diode D1 is connected between the drain electrode of the first MOS tube Q1 and the fifth resistor R5, the cathode of the first diode D1 is connected with one end of the sixth resistor R6, a second connecting terminal P2 is arranged between the cathode of the first diode D1 and the sixth resistor R6, and the other ends of the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are connected with the ground terminal.
Further, the processing circuit further includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a second MOS transistor Q2, a third triode Q3, a fourth triode Q4, and a first capacitor C1, one end of the seventh resistor R7 is connected to the power supply, one end of the eighth resistor R8 is connected to the other end of the seventh resistor R7, the gate of the second MOS transistor Q2 is connected to the output end of the second operational amplifier U2, the source of the second MOS transistor Q2 is connected to the other end of the eighth resistor R8, the base of the third triode Q3 is connected between the source of the second MOS transistor Q2 and the eighth resistor R8, one end of the ninth resistor R9 is connected to the power supply, the collector of the third triode Q3 is connected to the other end of the ninth resistor R9, one end of the tenth resistor R10 is connected between the ninth resistor R9 and the third triode Q3, the base of the fourth triode Q4 is connected to the other end of the tenth resistor R10, the fourth triode Q4 is connected between the seventh resistor R7 and the drain of the eighth resistor R8, the drain of the third triode Q3 is connected to the other end of the eleventh resistor R11, the drain of the third triode Q3 is connected to the fourth resistor Q3, and the other end of the eleventh resistor is connected between the drain of the fourth resistor Q3 and the fourth resistor Q3.
Further, the processing circuit further comprises a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a third operational amplifier U3, a second diode D2 and a fifth triode Q5, wherein one end of the twelfth resistor R12 is connected with a power supply, one end of the thirteenth resistor R13 is connected with the other end of the twelfth resistor R12, the same phase end of the third operational amplifier U3 is connected between a collector of the fourth triode Q4, a seventh resistor R7 and an eighth resistor R8, the reverse end of the third operational amplifier U3 is connected between the twelfth resistor R12 and the thirteenth resistor R13, the output end of the third operational amplifier U3 is connected with one end of the fourteenth resistor R14, the emitter of the fifth triode Q5 is connected between the output end of the third operational amplifier U3 and the fourteenth resistor R14, the base electrode of the fifth triode Q5 is connected with one end of the fifteenth resistor R15, the fifth triode Q5 is connected with one end of the sixteenth resistor R16, the cathode of the second diode D2 is connected between the fifth triode Q5 and the collector of the fifteenth resistor R2, the other end of the sixteenth resistor R14 is connected with the sixteenth resistor R2, and the other end of the sixteenth resistor R14 is connected between the drain of the thirteenth resistor R2 and the thirteenth resistor R2.
Further, the processing circuit further comprises a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a fourth operational amplifier U4 and a sixth MOS tube Q6, wherein one end of the seventeenth resistor R17 is connected with a power supply, one end of the eighteenth resistor R18 is connected with the other end of the seventeenth resistor R17, one end of the nineteenth resistor R19 is connected between the seventeenth resistor R17 and the eighteenth resistor R18, one end of the twenty-second resistor R20 is connected with the output end of the first operational amplifier U1, the other end of the twenty-first resistor R20 is connected with the other end of the nineteenth resistor R19, the in-phase end of the fourth operational amplifier U4 is connected between the nineteenth resistor R19 and the twenty-first resistor R20, the output end of the fourth operational amplifier U4 is connected with one end of the twenty-first resistor R21, the other end of the twenty-first resistor R21 is connected with the reverse end of the fourth operational amplifier U4, one end of the twenty-second resistor R22 is connected with the reverse end of the seventeenth resistor R4, one end of the twenty-second resistor R22 is connected with the twenty-second MOS tube Q6, one end of the twenty-second resistor Q4 is connected between the twenty-first resistor R21 and the drain electrode Q6, the twenty-second MOS tube Q1 is connected with the twenty-second Q1.
Further, the processing circuit further includes a fifth operational amplifier U5, a twenty-third resistor R23, a twenty-fourth resistor R24, and a third diode D3, where the in-phase end of the fifth operational amplifier U5 is connected between the collector of the fifth triode Q5 and the sixteenth resistor R16, the reverse end of the fifth operational amplifier U5 is connected between the second resistor R2 and the third resistor R3, the output end of the fifth operational amplifier U5 is connected between the gate of the first MOS transistor Q1 and the gate of the sixth MOS transistor Q6, one end of the twenty-third resistor R23 is connected between the output end of the fifth operational amplifier U5, the gate of the first MOS transistor Q1, the gate of the sixth MOS transistor Q6, one end of the twenty-fourth resistor R24 is connected with the source of the sixth MOS transistor Q6, the anode of the third diode D3 is connected between the source of the sixth MOS transistor Q6 and the twenty-fourth resistor R24, the cathode of the third diode D3 is connected between the sixth resistor R6 and the cathode of the first diode D1, and the other ends of the twenty-third resistor R23 and the fourth resistor R24 are connected to the ground.
Further, the processing circuit further includes a twenty-fifth resistor R25, one end of the twenty-fifth resistor R25 is connected between the gate of the second MOS transistor Q2, the output end of the second operational amplifier U2, and the anode of the second diode D2, and the other end of the twenty-fifth resistor R25 is connected to the ground end.
Further, the eighteenth resistor R18 is an adjustable potentiometer.
Compared with the prior art, the invention has the beneficial effects that:
the invention can automatically identify the marked pixel signals in the image and enhance the non-marked pixel signals after the marked pixel signals, and simultaneously, the enhancement processing of the current pixel is finished in time when the feedback times of the marked pixel signals are even.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the prior art and the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is an overall structure diagram provided by the present invention.
Fig. 2 is a block diagram of a processing circuit according to the present invention.
Detailed Description
In order that the objects and advantages of the invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, it being understood that the following text is only intended to describe one or more specific embodiments of the invention and is not intended to limit the scope of the invention as defined in the appended claims.
Referring to fig. 1 and fig. 2, in this embodiment, an image signal is fed back to a marking unit, the marking unit performs frame selection marking on a feature of interest, the number of marked pixels in each row and each column in an image is even, the marking unit converts the image signal into an electric signal after marking, meanwhile, the marking unit feeds back the converted image to a processing circuit based on orderly pixel arrangement, the pixel signal is fed back to a first operational amplifier in-phase end through a first connection terminal, the first operational amplifier reverse end is connected with a first operational amplifier output end through a first resistor and a first operational amplifier negative feedback to prevent interference of a lower-stage circuit signal, a signal between a second resistor and a third resistor is fed back to a second operational amplifier reverse end, the signal between the second resistor and the third resistor is the brightness amplitude of a marked pixel signal, the brightness amplitude of the marked pixel is higher than the brightness amplitude of any pixel in the image, a fourth resistor is a second operational amplifier in-phase end pull-down resistor, a first operational amplifier output end signal is fed back to a ground end loop through a fourth resistor, a first operational amplifier output end and a fourth operational amplifier output end is connected with a first MOS signal between the first MOS (MOS) through a first diode and a first diode, a second signal is connected with a second MOS (MOS) output end through a first diode and a first diode, a second signal is connected with a second MOS (metal oxide semiconductor) output end, a second signal is connected with a second MOS (metal oxide semiconductor) through a second MOS (MOS) output end, and a second MOS signal is connected with a fifth MOS signal.
Referring to fig. 2, in this embodiment, a power signal is forward biased via a ninth resistor, a tenth resistor, a base of a fourth triode, an emitter of the fourth triode, and a ground loop, the fourth triode is turned on, while a signal between the ninth resistor and the tenth resistor is fed back to a drain of a second MOS transistor via an eleventh resistor, a potential of a first capacitor rises, a signal between the ninth resistor and the tenth resistor is reduced in amplitude via a seventh resistor, a collector of the fourth triode, an emitter of the fourth triode, and a ground loop, the signal between the seventh resistor and the fourth triode is increased in amplitude, a second operational amplifier is output when a pixel signal fed back is a marked pixel signal, an output signal of the second operational amplifier is fed back to a gate of the second MOS transistor, a difference between the gate of the second MOS transistor and a source of the second MOS transistor is higher than an on threshold, a signal between the ninth resistor and the tenth resistor is increased in amplitude via a third resistor, a fourth transistor, a third transistor, a fourth transistor, and a third transistor is turned-off, and a fourth transistor is increased in amplitude via a fourth resistor, a fourth transistor, and a fourth transistor is fed back to a ground loop, and a signal between the fourth operational amplifier is fed back to a gate of the fourth operational amplifier is output when a pixel signal fed back is marked pixel signal, the signal amplitude between the seventh resistor and the fourth triode collector is reduced, so that when the marked pixel signals are fed back through the first connecting terminal, the signal amplitude between the seventh resistor and the fourth triode collector is increased when the feedback times are odd, and the signal amplitude between the seventh resistor and the fourth triode collector is reduced when the feedback times are even, and the unmarked pixel signals of the interest feature in the marking frame are identified.
Referring to fig. 2, in this embodiment, a signal between the collector of the seventh resistor and the collector of the fourth transistor is fed back to the in-phase end of the third operational amplifier, a signal between the twelfth resistor and the thirteenth resistor is fed back to the inverting end of the third operational amplifier, when the first connection terminal feeds back the marked pixel signal for the first time, the third operational amplifier outputs, the signal between the output end of the third operational amplifier and the fourteenth resistor is fed back to the ground loop through the fourteenth resistor, the signal between the output end of the third operational amplifier and the fourteenth resistor is fed back to the emitter of the fifth transistor, and at the same time, the signal between the output end of the second operational amplifier and the output end of the fourth transistor is fed back to the ground loop through the second diode and the fifteenth resistor, when the marked pixel signal ends the feedback, the second operational amplifier is turned off, the emitter signal of the fifth transistor is fed back to the ground loop through the base of the fifth transistor, the emitter of the fifth transistor and the base of the fifth transistor are forward biased, the fifth transistor is turned on, the signal between the output end of the third operational amplifier and the emitter of the fourteenth resistor is fed back to the ground loop through the fifth transistor, and the sixteenth resistor is fed back to the ground loop, so that the pixel signal is processed only after the pixel signal is marked.
Referring to fig. 2, in this embodiment, the signal amplitude between the seventeenth resistor and the eighteenth resistor is the enhanced amplitude of the pixel signal, the enhancement amplitude can be changed by adjusting the eighteenth resistor, the signal between the seventeenth resistor and the eighteenth resistor is fed back to the in-phase end of the fourth operational amplifier through the nineteenth resistor, the signal at the output end of the first operational amplifier is fed back to the in-phase end of the fourth operational amplifier through the twentieth resistor, the output end of the fourth operational amplifier, the twenty first resistor and the twenty second resistor form a negative feedback connection, so that the signal between the output end of the fourth operational amplifier and the twenty first resistor is the enhanced pixel signal, the signal between the fourth operational amplifier output end and the twenty first resistor is fed back to the drain electrode of the sixth MOS transistor, the signal between the second resistor and the third resistor is fed back to the inverting end of the fifth operational amplifier, the signal between the collector of the fifth triode and the sixteenth resistor is fed back to the same phase end of the fifth operational amplifier, when the feedback of the pixel signal marked for the first time is finished, the fifth operational amplifier outputs, the signal of the output end of the fifth operational amplifier is fed back to a grounding end loop through a twenty-third resistor, meanwhile, the signal between the output end of the fifth operational amplifier and the twenty-third resistor is fed back to the grid of the first MOS tube and the grid of the sixth MOS tube, the pressure difference between the grid of the first MOS tube and the source of the first MOS tube is higher than a conducting threshold value, the first MOS tube is cut off, the pressure difference between the grid of the sixth MOS tube and the source of the sixth MOS tube is higher than the conducting threshold value, the sixth MOS tube is conducted, the signal between the output end of the fourth operational amplifier and the twenty-first resistor is fed back to the grounding end loop through the drain of the sixth MOS tube, the source of the sixth MOS tube and the twenty-fourth resistor, and the twenty-fourth resistor are fed back to the grounding end loop through the third diode and the sixth resistor, the enhanced pixel signals are fed back to the conversion unit through the second connection terminal, when the first connection terminal obtains the pixel signal feedback again, the fifth operational amplifier is cut off, so that the enhancement processing of the current pixel can be timely ended when the number of times of the marked pixel signal feedback is even, and the processing circuit only carries out the enhancement processing on the pixel signals of the interest feature in the marked frame.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (5)
1. The signal processing circuit in the visual recognition system comprises a marking unit, a processing circuit and a conversion unit, and is characterized in that the marking unit is connected with the processing circuit, the processing circuit is connected with the conversion unit, the marking unit is used for marking and converting the interesting characteristic in an image, the processing circuit is used for selectively enhancing the image based on marking signals, the conversion unit is used for receiving signals fed back by the processing circuit and converting the signals, the processing circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first diode, a first MOS (metal oxide semiconductor) tube, a first connecting terminal and a second connecting terminal, a first operational amplifier in-phase end and a first connecting terminal are connected, a first operational amplifier reverse end is connected with one end of the first resistor, a first operational amplifier output end is connected with the other end of the first resistor, a second resistor in one end is connected with a power supply, a second operational amplifier in-phase end is connected between the first operational amplifier output end and the first resistor, a fourth resistor in-phase end and the second operational amplifier in the second end is connected with the second resistor, a second operational amplifier in the first MOS tube in the first end of the second resistor in the first resistor, a second operational amplifier in the second MOS end is connected with the second MOS end and the second MOS end is connected with the second MOS end in the second resistor in the first resistor, a positive-phase end of the first operational amplifier in the second operational amplifier in the first MOS end and the first MOS end is connected with the second MOS end, the second operational amplifier in the first MOS end and the second MOS end is connected with the second MOS end in the first MOS end, the first MOS end and the first MOS end is connected with the first MOS end in the first MOS end and the first MOS end in the first resistor and the second resistor in the first resistor and the second MOS circuit. The image signal is fed back to the marking unit, the marking unit carries out frame selection marking on the interest feature, meanwhile, the marking unit feeds back the converted image to the processing circuit based on the pixel arrangement order, the processing circuit further comprises a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a second MOS tube, a third triode, a fourth triode and a first capacitor, one end of the seventh resistor is connected with a power supply, one end of the eighth resistor is connected with the other end of the seventh resistor, the grid electrode of the second MOS tube is connected with the output end of a second operational amplifier, the source electrode of the second MOS tube is connected with the other end of the eighth resistor, the base electrode of the third triode is connected between the source electrode of the second MOS tube and the eighth resistor, one end of the ninth resistor is connected with the power supply, the collector electrode of the third triode is connected with the other end of the ninth resistor, one end of a tenth resistor is connected between a ninth resistor and a third triode collector, the other end of a fourth triode base is connected with the other end of the tenth resistor, the fourth triode collector is connected between a seventh resistor and an eighth resistor, one end of an eleventh resistor is connected between the ninth resistor, the tenth resistor and the third triode collector, the drain electrode of a second MOS tube is connected with the other end of the eleventh resistor, one end of a first capacitor is connected between the drain electrode of the second MOS tube and the eleventh resistor, the emitter electrode of the third triode, the emitter electrode of the fourth triode, the other end of the first capacitor and the ground end are connected, the processing circuit further comprises a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a fourth operational amplifier and a sixth MOS tube, one end of the seventeenth resistor is connected with a power supply, one end of the eighteenth resistor is connected with the other end of the seventeenth resistor, one end of a nineteenth resistor is connected between a seventeenth resistor and an eighteenth resistor, one end of the twentieth resistor is connected with the output end of the first operational amplifier, the other end of the twentieth resistor is connected with the other end of the nineteenth resistor, the in-phase end of the fourth operational amplifier is connected between the nineteenth resistor and the twentieth resistor, the output end of the fourth operational amplifier is connected with one end of the twenty first resistor, the other end of the twenty first resistor is connected with the reverse end of the fourth operational amplifier, one end of the twenty second resistor is connected between the reverse end of the fourth operational amplifier and the twenty first resistor, the drain electrode of the sixth MOS tube is connected between the output end of the fourth operational amplifier and the twenty first resistor, the grid electrode of the sixth MOS tube is connected with the grid electrode of the first MOS tube, the eighteenth resistor, the other end of the twenty second resistor is connected with the ground, and the fourth operational amplifier output end, the twenty first resistor and the twenty second resistor form negative feedback connection to enable signals between the fourth operational amplifier and the twenty first resistor to be enhanced pixel signals.
2. The signal processing circuit in a visual recognition system according to claim 1, wherein the processing circuit further comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a third operational amplifier, a second diode, and a fifth triode, wherein one end of the twelfth resistor is connected to a power supply, one end of the thirteenth resistor is connected to the other end of the twelfth resistor, the same phase end of the third operational amplifier is connected between a collector of the fourth triode, a seventh resistor, and an eighth resistor, the reverse end of the third operational amplifier is connected between the twelfth resistor and the thirteenth resistor, the output end of the third operational amplifier is connected to one end of the fourteenth resistor, the emitter of the fifth triode is connected between the output end of the third operational amplifier and the fourteenth resistor, the base of the fifth triode is connected to one end of the fifteenth resistor, the collector of the fifth triode is connected to one end of the sixteenth resistor, the cathode of the second diode is connected between the base of the fifth triode and the fifteenth resistor, the anode of the second diode is connected between the output end of the second operational amplifier and the gate of the second MOS, the thirteenth resistor, the sixteenth resistor, and the other end of the sixteenth resistor are connected to the ground.
3. The signal processing circuit in the visual recognition system according to claim 1, wherein the processing circuit further comprises a fifth operational amplifier, a twenty-third resistor, a twenty-fourth resistor, and a third diode, the in-phase end of the fifth operational amplifier is connected between the collector of the fifth triode and the sixteenth resistor, the reverse end of the fifth operational amplifier is connected between the second resistor and the third resistor, the output end of the fifth operational amplifier is connected between the gate of the first MOS transistor and the gate of the sixth MOS transistor, one end of the third resistor is connected between the output end of the fifth operational amplifier, the gate of the first MOS transistor, the gate of the sixth MOS transistor, one end of the twenty-fourth resistor is connected with the source of the sixth MOS transistor, the anode of the third diode is connected between the source of the sixth MOS transistor and the sixteenth resistor, the cathode of the third diode is connected between the sixth resistor and the cathode of the first diode, and the other end of the twenty-third resistor is connected with the ground.
4. The signal processing circuit in a visual recognition system according to claim 1, wherein the processing circuit further comprises a twenty-fifth resistor, one end of the twenty-fifth resistor is connected between the gate of the second MOS transistor, the output end of the second operational amplifier, and the anode of the second diode, and the other end of the twenty-fifth resistor is connected to the ground.
5. A signal processing circuit in a visual recognition system according to claim 1, wherein the eighteenth resistor is an adjustable potentiometer.
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| CN202410093030.5A CN117611977B (en) | 2024-01-23 | 2024-01-23 | Signal processing circuit in visual recognition system |
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