CN117595863A - Frequency adjustment device and electronic equipment - Google Patents

Abstract

The device comprises a master chip and at least one connected slave chip, wherein the master chip sends a trigger signal at a first time and obtains a first clock signal by frequency division according to a phase-locked loop clock signal generated by a phase-locked loop after delaying for a first delay time relative to the first time; and after the secondary chip delays a second delay time period at a second moment when the secondary chip relatively receives the trigger signal, frequency division is carried out according to the phase-locked loop clock signal to obtain a second clock signal, wherein the first delay time period is the sum of the second delay time period and a preset time period, and the preset time period is the signal transmission time period of the primary chip and the secondary chip. According to the embodiment of the disclosure, the frequency adjustment of the clock signals obtained by the master chip and the slave chip according to the frequency division of the PLL clock signals can be realized, the normal operation of the noise interference device is avoided, and the working efficiency of the device is improved.

Description

Frequency adjustment device and electronic equipment

Technical Field

The disclosure relates to the technical field of integrated circuits, and in particular relates to a frequency adjusting device and electronic equipment.

Background

A master chip and a plurality of slave chips for realizing different functions are configured in the multifunctional electronic device. In the present cascade chip, the master chip and the slave chip use the PLL clock generated by the PLL clock generator (PLL-based Clock Generator) as the master clock in order to keep the frequency and phase of the master clock consistent. Although the frequency and the phase of the master clock can be kept consistent between the master chip and the slave chip, the clock after the frequency division of the PLL clock can only be consistent in frequency and cannot be consistent in phase, which easily causes inconsistent analog timing, thereby causing noise generation, abnormal operation of electronic equipment and the like.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a frequency adjustment device comprising a master chip and at least one slave chip connected thereto, wherein,

the main chip sends a trigger signal at a first time, delays the trigger signal for a first delay time period relative to the first time, and divides the frequency according to a phase-locked loop clock signal generated by a phase-locked loop to obtain a first clock signal;

the slave chip delays a second delay time length at a second moment relatively receiving the trigger signal, and then obtains a second clock signal according to the frequency division of the phase-locked loop clock signal,

the first time delay time length is the sum of the second time delay time length and a preset time length, and the preset time length is the signal transmission time length of the master chip and the slave chip.

In one possible implementation, the master chip includes a first frequency divider and a first delay that are connected, and the slave chip includes a second frequency divider and a second delay that are connected, wherein,

the first delayer is used for starting clock counting from the first moment and outputting a first trigger signal when the counting time length reaches the first delay time length;

the first frequency divider is used for dividing the frequency according to the phase-locked loop clock signal to obtain the first clock signal under the condition that the first trigger signal is received;

the second delayer is used for starting clock counting from the second moment and outputting a second trigger signal when the counting time length reaches the second time delay time length;

the second frequency divider is configured to divide the frequency according to the phase-locked loop clock signal to obtain the second clock signal when the second trigger signal is received.

In one possible implementation, the main chip is further configured to:

performing multiple times of signal transmission duration tests with the slave chip to obtain multiple test durations;

and determining the average value of the plurality of test durations, and obtaining the preset duration according to the average value.

In one possible embodiment, the signaling duration test includes:

the master chip sends a test signal to the slave chip at a third moment and starts clock counting from the third moment;

and stopping clock counting after the master chip receives the response signal from the slave chip to obtain the test duration, wherein the preset duration is one half of the average value.

In a possible implementation, the test signal is a high level signal, the answer signal is the high level signal, wherein,

the master chip is further configured to send the high-level signal as a test signal to the slave chip at the third time, and start clock counting from the third time;

the slave chip is further configured to directly transmit the high-level signal back to the master chip as the response signal after receiving the high-level signal;

the master chip is further used for stopping clock counting after the master chip receives the high-level signal returned from the slave chip, and the test duration is obtained.

In a possible embodiment, the master chip further comprises a time difference counter for:

and starting to count the clock from the third moment, and stopping counting the clock after receiving the high-level signal returned from the slave chip to obtain the test duration.

In a possible implementation, the master chip comprises a first delay parameter setting unit, the slave chip comprises a second delay parameter setting unit, wherein,

the second delay parameter setting unit is used for setting delay parameters of a second delay device in the slave chip according to the second delay time length;

the first delay parameter setting unit is used for obtaining the first delay time according to the second delay time and the preset time, and setting delay parameters of a first delay device in the main chip.

In one possible implementation manner, the master chip comprises any one of an application processor, a microprocessor, a central processing unit, an FPGA processor and a DSP processor, and the slave chip comprises any one of a touch control chip, a fingerprint identification chip, a display driving chip and a TDDI chip.

According to an aspect of the present disclosure, there is provided an electronic apparatus including the frequency adjustment device.

In one possible embodiment, the electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an integrated computer, an access control device, and an electronic door lock.

The embodiment of the disclosure provides a frequency adjusting device, which comprises a master chip and at least one connected slave chip, wherein the master chip sends a trigger signal at a first time and delays a first delay time relative to the first time, and then the first clock signal is obtained according to frequency division of a phase-locked loop clock signal generated by a phase-locked loop; the slave chip delays a second delay time period at a second moment when the slave chip relatively receives the trigger signal, and frequency division is carried out according to the phase-locked loop clock signal to obtain a second clock signal, wherein the first delay time period is the sum of the second delay time period and a preset time period, and the preset time period is the signal transmission time period of the master chip and the slave chip.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.

Fig. 1a shows a schematic diagram of a cascade chip in the related art, and fig. 1b shows an operation timing diagram of the cascade chip in the related art.

Fig. 2 shows a schematic diagram of a frequency adjustment device according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a frequency adjustment device according to an embodiment of the present disclosure.

Fig. 4 shows an operation timing chart of the frequency adjustment device according to the embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

In the description of the present disclosure, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Referring to fig. 1a and 1b, fig. 1a shows a schematic diagram of a cascaded chip in the related art, and fig. 1b shows a timing diagram of the cascaded chip in the related art.

As shown in fig. 1a, the main chip may be an application processor 1a, and a first clock module 11a and a first frequency dividing module 12a are disposed therein. On the other hand, the slave chip may be a touch and display driving integrated (Touch and Display Driver Integration, TDDI) chip, and the slave chip includes a second clock module 21a, a second frequency dividing module 22a, a touch module 23a, and a display driving module 24a. The first clock module 11a and the second clock module 21a are phase locked loop clock generators (PLL-based Clock Generator), i.e. phase locked loops, for generating PLL clock signals.

Wherein there is a routing delay between the application processor 1a and the slave chip 2a, such as a TDDI chip. Therefore, as shown in fig. 1b, the TDDI chip divides the second clock signal from the PLL clock signal after receiving the touch enable signal, and the application processor 1a divides the first clock signal from the PLL clock signal after sending the touch enable signal, which may cause phase inconsistency between the second clock signal and the first clock signal, as shown in the operation timing diagram of fig. 1 b. This phase mismatch between the second clock signal and the first clock signal can produce noise that affects the operation of the cascaded chip.

In view of this, the embodiment of the disclosure provides a frequency adjustment device, which includes a master chip and at least one slave chip connected to the master chip, where the master chip sends a trigger signal at a first time, delays a first delay time period relative to the first time, and divides a frequency according to a phase-locked loop clock signal generated by a phase-locked loop to obtain a first clock signal; the slave chip delays a second delay time period at a second moment when the slave chip relatively receives the trigger signal, and frequency division is carried out according to the phase-locked loop clock signal to obtain a second clock signal, wherein the first delay time period is the sum of the second delay time period and a preset time period, and the preset time period is the signal transmission time period of the master chip and the slave chip.

Referring to fig. 2, fig. 2 is a schematic diagram of a frequency adjustment device according to an embodiment of the disclosure.

As shown in fig. 2, the device comprises a master chip 10 and at least one slave chip 20 connected thereto, wherein,

the main chip 10 sends a trigger signal at a first time, delays the trigger signal for a first delay time period relative to the first time, and divides the frequency according to a phase-locked loop clock signal generated by a phase-locked loop to obtain a first clock signal;

after being delayed by a second delay time period relative to the second time point of receiving the trigger signal, the slave chip 20 divides the frequency according to the phase-locked loop clock signal to obtain a second clock signal,

the first delay time length is the sum of the second delay time length and a preset time length, and the preset time length is the signal transmission time length of the master chip 10 and the slave chip 20.

The specific types of the master chip 10 and the slave chips 20 are not limited, the number of the slave chips 20 is not limited, and those skilled in the art can set the specific types according to practical situations and needs, wherein the master chip 10 is, for example, an application processor and a CPU, the slave chips 20 are, for example, a touch chip, a fingerprint identification chip, a display driving chip, a TDDI chip, etc., and the master chip 10 is cascaded with the plurality of slave chips 20 through at least one transmission interface (for example, IIC, SPI, MIPI).

The embodiment of the present disclosure is not limited to a specific manner of cascading the master chip 10 with the plurality of slave chips 20, and it should be noted that the connection manner of the master chip 10 and the plurality of slave chips 20 shown in fig. 2 is exemplary and should not be construed as limiting the embodiment of the present disclosure. Illustratively, the cascade connection may include a parallel connection manner of the master chip 10 and the plurality of slave chips 20 (as shown in fig. 2); the cascade connection mode may be a serial connection mode of the master chip 10 and the plurality of slave chips 20, that is, the master chip 10 and the plurality of slave chips 20 are connected end to end in sequence, and the master chip 10 is respectively connected to each slave chip 20; the cascade connection may be a mixture of the parallel connection and the series connection. It should be understood that, in the cascade combination of the master chip 10 and the plurality of slave chips 20, the routing of the power lines, the signal lines, the data lines, etc. of the master chip 10 and the plurality of slave chips 20 may be set in reference to the cascade manner, and those skilled in the art do not limit the specific arrangement manner of the routing between the master chip 10 and the plurality of slave chips 20.

The embodiment of the disclosure does not limit the specific sizes of the first time delay duration, the second time delay duration and the preset time duration, and the person skilled in the art can set the time delay duration according to actual situations and needs.

The sources of the phase-locked loop clock signals of the master chip 10 and the slave chip 20 are not limited, and the phase-locked loop clock signals of the master chip 10 and the slave chip 20 can be derived from the same phase-locked loop clock generator, so that the frequency and the phase of the phase-locked loop clock signals of the master chip 10 and the slave chip 20 can be ensured to be consistent, for example, the phase-locked loop clock generator is arranged in the master chip 10, and the PLL clock generated by the phase-locked loop clock generator is directly transmitted to the slave chip 20; of course, the PLL clock generators may be derived from the respective PLL clock generators, so long as the PLL clock signals and phases thereof can be ensured to be identical, for example, the PLL clock generators are provided in both the master chip 10 and the slave chip 20, but PLL clocks generated by the PLL clock generators of the master chip 10 and the slave chip 20 are identical in frequency and phase.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating a frequency adjustment apparatus according to an embodiment of the disclosure.

In one possible implementation, as shown in fig. 3, the master chip 10 may include a first divider 120, a first delay 110 connected, and the slave chip 20 may include a second divider 220, a second delay 210 connected, where,

the first delay unit 110 is configured to start clock counting from the first time, and output a first trigger signal when a counting duration reaches the first delay duration;

the first frequency divider 120 is configured to divide the frequency according to the phase-locked loop clock signal to obtain the first clock signal when the first trigger signal is received;

the second delay unit 210 is configured to start clock counting from the second time, and output a second trigger signal when the counting duration reaches the second delay duration;

the second frequency divider 220 is configured to divide the frequency according to the phase-locked loop clock signal to obtain the second clock signal when the second trigger signal is received.

The specific implementation manners of the first frequency divider 120, the first delay unit 110, the second frequency divider 220, and the second delay unit 210 are not limited in the embodiments of the present disclosure, and a person skilled in the art may adopt a suitable technical scheme according to actual situations and needs.

For example, the master chip 10 sends a trigger signal when the PLL frequency-divided clocks of the master chip 10 and the slave chip 20 need to be synchronized (i.e., at a first time), and the first delayer 110 of the master chip 10 starts counting from the first time, and the first delayer 110 outputs the first trigger signal when the counting duration reaches the first delay duration, so that the first frequency divider 120 divides the frequency according to the PLL clock signal to obtain the first clock signal.

Illustratively, from a first time, a trigger signal is transmitted from the master chip 10 to the slave chip 20, when the slave chip 20 receives the trigger signal (a second time), the second delayer 210 of the slave chip 20 starts to count clocks from the second time, and outputs a second trigger signal when the count duration reaches the second delay duration, so that the second frequency divider 220 divides the clock signal according to the phase-locked loop to obtain the second clock signal.

Since the first delay time length of the first delay unit 110 is the sum of the second delay time length and the preset time length, and the preset time length is the signal transmission time length of the master chip 10 and the slave chip 20, the first delay unit 110 and the second delay unit 210 finish timing synchronously, the first delay unit 110 of the master chip 10 outputs the first trigger signal and the second delay unit 210 of the slave chip 20 outputs the second trigger signal synchronously, and in this case, the phases of the first clock signal and the second clock signal obtained by frequency division by the first frequency divider 120 and the second frequency divider 220 are the same, so that alignment of PLL frequency division clocks is realized.

The method for determining the signal transmission duration between the master chip 10 and the slave chip 20 according to the embodiments of the present disclosure is not limited, and a person skilled in the art may implement the method by adopting a suitable technical means according to actual situations and needs, and the following exemplary description will be given for a preferred implementation.

In one possible embodiment, the main chip 10 may also be used to:

performing a plurality of signal transmission duration tests with the slave chip 20 to obtain a plurality of test durations;

and determining the average value of the plurality of test durations, and obtaining the preset duration according to the average value.

In one possible implementation, the signaling duration test may include:

the master chip 10 transmits a test signal to the slave chip 20 at a third time and starts clock counting from the third time;

and stopping counting the clock after the master chip 10 receives the response signal from the slave chip 20 to obtain the test duration, wherein the preset duration is one half of the average value.

For example, the master chip 10 of the embodiment of the present disclosure may start counting time after transmitting a test signal to the slave chip 20 and stop counting time after receiving a response signal from the slave chip 20, thereby obtaining a time difference T; repeating the steps N-1 times to obtain N time differences T1, T2, … and TN; after calculating an average value of the N time differences, dividing the average value by 2 to obtain the signal transmission duration between the master chip 10 and the slave chip 20, that is, the routing delay time between the master chip 10 and the slave chip 20.

In a possible implementation, the test signal is a high level signal, the answer signal is the high level signal, wherein,

the master chip 10 may be further configured to send the high level signal as a test signal to the slave chip 20 at the third time, and start clock counting from the third time;

the slave chip 20 may be further configured to directly transmit the high-level signal back to the master chip 10 as the response signal after receiving the high-level signal;

the master chip 10 may also be configured to stop clock counting after the master chip 10 receives the high level signal returned from the slave chip 20, to obtain the test duration.

In one possible implementation, the master chip 10 further includes a time difference counter (Delta counter) 130, the time difference counter 130 being operable to:

and starting to count the clock from the third moment, and stopping counting the clock after receiving the high-level signal returned from the slave chip 20 to obtain the test duration.

Illustratively, the master chip 10 may issue a measurement request, pull up the level of the test signal (i.e., form a high signal), while the time difference counter 130 inside the master chip 10 starts counting while the level of the test signal is pulled up. The high level signal is then routed to the slave chip 20 and the slave chip 20 loops the high level signal directly back to the connection pins of the master chip 10. After the response signal (i.e., high signal) of the slave chip 20 is transmitted to the connection pin, the response signal passes through the two-stage synchronizer at the master chip 10. After that, the time difference counter 130 stops counting after seeing the rising edge of the synchronized response signal. Thus, the time difference counter 130 inside the main chip 10 counts the time difference T.

The specific implementation of the time difference counter 130 is not limited in the embodiments of the present disclosure, and those skilled in the art may implement the time difference counter by using appropriate technical means according to actual situations and needs.

In one possible implementation, the master chip 10 includes a first delay parameter setting unit 140, and the slave chip 20 includes a second delay parameter setting unit 230, wherein,

the second delay parameter setting unit 230 is configured to set a delay parameter of the second delay 210 in the slave chip 20 according to the second delay duration;

the first delay parameter setting unit 140 is configured to obtain the first delay time according to the second delay time and the preset time, and set a delay parameter of the first delay 110 in the main chip 10.

The specific implementation manners of the first delay parameter setting unit 140 and the second delay parameter setting unit 230 are not limited in the embodiments of the present disclosure, and those skilled in the art may adopt suitable technical means according to actual situations and needs. Illustratively, the delay parameter of the second delayer 210 may be the second delay time period, and the delay parameter of the first delayer 110 may be the first delay time period.

Referring to fig. 4, fig. 4 shows an operation timing diagram of the frequency adjustment device according to an embodiment of the disclosure.

Illustratively, the master chip 10 of the embodiment of the present disclosure may send a test signal to the slave chip 20 at a third time (may be a time earlier than the first time, i.e. a preset time period is measured in advance), and start counting clocks from the third time; stopping counting the clock after the master chip 10 receives the response signal from the slave chip 20 to obtain the test duration, obtaining a plurality of test durations by executing more than one signal transmission duration test with the slave chip 20, determining an average value of the plurality of test durations, obtaining the preset duration according to the average value, and setting delay parameters of the first delayer 110 and the second delayer 210 through the first delay parameter setting unit 140 and the second delay parameter setting unit 230.

As shown in fig. 4, the second Delay duration delay_s is equal to 3 PLL clocks, and the preset duration is equal to 6 PLL clocks, so that the preset duration is the signal transmission duration of the master chip and the slave chip according to the sum of the second Delay duration and the preset duration, where the first Delay duration delay_m is equal to 9 PLL clocks.

For example, as shown in fig. 4, the first Delay parameter setting unit 140 and the second Delay parameter setting unit 230 respectively set the corresponding first Delay time delay_m and second Delay time delay_s for the master chip 10 and the slave chip 20, and then the master chip 10 sends out a trigger signal, and at the same time, the first Delay unit 110 inside the master chip 10 starts counting the Delay time (delay_m) of the master chip 10.

Illustratively, as shown in fig. 4, after the trigger signal reaches the corresponding pin port of the slave chip 20, the second delayer 210 inside the slave chip 20 starts counting the Delay time (delay_s) of the slave chip 20 after seeing the rising edge.

Illustratively, as shown in fig. 4, the first delay 110 and the second delay 210 finish counting simultaneously (for example, in a countdown manner, they count to 0 simultaneously), so that the first frequency-divided signal and the second frequency-divided signal are pulled high at the same time point, and the first frequency divider 120 and the second frequency divider 220 are enabled to operate simultaneously.

Illustratively, as shown in fig. 4, the first frequency divider 120 divides the PLL clock signal to obtain a first clock signal and the second frequency divider 220 divides the PLL clock signal to obtain a second clock signal (clock phase alignment).

In one possible implementation, the master chip 10 includes any one of an application processor, a microprocessor, a central processing unit, an FPGA processor, and a DSP processor, and the slave chip 20 includes any one of a touch chip, a fingerprint recognition chip, a display driving chip, and a TDDI chip. Of course, the master chip 10, the slave chip 20 may also be other processing components, including, but not limited to, a separate processor, or a discrete component, or a combination of a processor and a discrete component in one example. The processor may include a controller in an electronic device having the functionality to execute instructions, and may be implemented in any suitable manner, for example, by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers.

The frequency adjustment device of the embodiment of the present disclosure is performed by the master chip 10 and the slave chip 20 cascaded with the master chip 10, so that the first clock signal obtained by dividing the frequency of the master chip 10 according to the PLL clock signal and the second clock signal obtained by dividing the frequency of the slave chip 20 according to the PLL clock signal are mutually frequency-adjusted.

For example, when the slave chip 20 is a TDDI chip, if the touch function needs to be performed, the master chip 10 sends a touch enable signal to the touch module of the slave chip 20, and the first frequency divider inside the master chip 10 divides the PLL clock signal into a first clock signal. And, after receiving the touch enable signal, the second frequency divider inside the slave chip 20 divides the PLL clock signal into a second clock signal.

For example, the touch device integrated in the electronic apparatus may include: a touch panel and a touch chip. When the electronic device carries the TDDI chip, the touch control chip is the touch control module inside the TDDI chip. Further, the touch module may include a control unit, and a driving circuit and a readout circuit controlled by the control unit, where the readout circuit includes a plurality of Analog Front End (AFE) units for performing touch sampling. Thus, the second clock signal is transmitted to the readout circuit, so that the readout circuit performs touch sampling according to the frequency of the second clock signal. In contrast, the first clock signal inside the main chip 10 is used to receive and process the touch data transmitted by the TDDI chip. Because the frequencies and phases of the first clock signal and the second clock signal are calibrated and aligned, in the application, the main chip can synchronously realize the receiving and processing of the touch data transmitted by the TDDI, noise is not generated, and the processing accuracy is improved.

The frequency adjustment device may be applied to an electronic device, and the electronic device may be any one of a multimedia information display device (KIOSK), a head-mounted display device with a touch function and/or a biometric function, a smart television with a touch function and/or a biometric function, a smart phone, a smart watch with a touch function and/or a biometric function, a tablet computer, an integrated computer, a notebook computer, a vehicle-mounted entertainment device, a digital camera, a video door phone, and an electronic door lock with a touch function and/or a biometric function, and may also be a terminal device, where the terminal device may be a User Equipment (UE), a mobile device, a User terminal, a handheld device, a computing device, or a vehicle-mounted device, and some terminals are exemplified by: a Mobile Phone, a tablet, a notebook, a palm, a Mobile internet device (Mobile Internetdevice, MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in unmanned driving (Selfdriving), a wireless terminal in teleoperation (Remote medical Surgery), a wireless terminal in Smart Grid (Smart Grid), a wireless terminal in transportation security (Transportation Safety), a wireless terminal in Smart City (Smart City), a wireless terminal in Smart Home (Smart Home), a wireless terminal in the internet of vehicles, and the like. For example, the server may be a local server or a cloud server.

It will be appreciated that the above embodiments mentioned in the present disclosure may be combined with each other to form a combined embodiment without departing from the principle logic, and are limited to the descriptions of the embodiments are omitted. Those skilled in the art will appreciate that in particular embodiments, the particular order of execution of the steps should be determined by their function and possible inherent logic.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A frequency adjusting device is characterized in that the device comprises a master chip and at least one slave chip connected with the master chip, wherein,

the main chip sends a trigger signal at a first time, delays the trigger signal for a first delay time period relative to the first time, and divides the frequency according to a phase-locked loop clock signal generated by a phase-locked loop to obtain a first clock signal;

the slave chip delays a second delay time length at a second moment relatively receiving the trigger signal, and then obtains a second clock signal according to the frequency division of the phase-locked loop clock signal,

the first time delay time length is the sum of the second time delay time length and a preset time length, and the preset time length is the signal transmission time length of the master chip and the slave chip.

2. The apparatus of claim 1, wherein the master chip comprises a first frequency divider and a first delay coupled thereto, and the slave chip comprises a second frequency divider and a second delay coupled thereto, wherein,

the first delayer is used for starting clock counting from the first moment and outputting a first trigger signal when the counting time length reaches the first delay time length;

the first frequency divider is used for dividing the frequency according to the phase-locked loop clock signal to obtain the first clock signal under the condition that the first trigger signal is received;

the second delayer is used for starting clock counting from the second moment and outputting a second trigger signal when the counting time length reaches the second time delay time length;

the second frequency divider is configured to divide the frequency according to the phase-locked loop clock signal to obtain the second clock signal when the second trigger signal is received.

3. The apparatus of claim 1, wherein the master chip is further configured to:

performing multiple times of signal transmission duration tests with the slave chip to obtain multiple test durations;

and determining the average value of the plurality of test durations, and obtaining the preset duration according to the average value.

4. The apparatus of claim 3, wherein the signaling duration test comprises:

the master chip sends a test signal to the slave chip at a third moment and starts clock counting from the third moment;

and stopping clock counting after the master chip receives the response signal from the slave chip to obtain the test duration, wherein the preset duration is one half of the average value.

5. The apparatus of claim 4, wherein the test signal is a high signal and the reply signal is the high signal, wherein,

the master chip is further configured to send the high-level signal as a test signal to the slave chip at the third time, and start clock counting from the third time;

the slave chip is further configured to directly transmit the high-level signal back to the master chip as the response signal after receiving the high-level signal;

the master chip is further used for stopping clock counting after the master chip receives the high-level signal returned from the slave chip, and the test duration is obtained.

6. The apparatus of claim 5, wherein the master chip further comprises a time difference counter to:

and starting to count the clock from the third moment, and stopping counting the clock after receiving the high-level signal returned from the slave chip to obtain the test duration.

7. The apparatus according to any one of claims 1 to 6, wherein the master chip comprises a first delay parameter setting unit and the slave chip comprises a second delay parameter setting unit, wherein,

the second delay parameter setting unit is used for setting delay parameters of a second delay device in the slave chip according to the second delay time length;

the first delay parameter setting unit is used for obtaining the first delay time according to the second delay time and the preset time, and setting delay parameters of a first delay device in the main chip.

8. The apparatus of any one of claims 1 to 6, wherein the master chip comprises any one of an application processor, a microprocessor, a central processing unit, an FPGA processor, and a DSP processor, and the slave chip comprises any one of a touch chip, a fingerprint recognition chip, a display driver chip, and a TDDI chip.

9. An electronic device, characterized in that the electronic device comprises a frequency adjustment device according to claims 1-8.

10. The electronic device of claim 9, wherein the electronic device comprises any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an integrated computer, an access control device, and an electronic door lock.