TWI342477B - - Google Patents

Description

1342477. Nine, invention description: [Technical field of the invention] The present invention relates to a signal system and method, relating to a signal generation system and method for extracting a clock signal by one or more wafers In order to use, the signal generating system is in the second process; when the method is in the process, the at least one or more wafers can be set according to the operating mode and the output frequency of the nickname generating system. Store the working mode and output frequency set value in the signal production: EEPROM mode of the system ★ and f female · ^. The old 5^, 、, 〒 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄[Prior Art] The digital signal is the binary information represented by the state of the voltage amplitude of the recovery of the U/, U/, U, and 丨 by the recovery]tTi -ίί π λα Γ-. When the digital signal is received on the transfer tray between the two components, there is a zero indicated by low power, or it is represented by high power! Two kinds of complaints, digital devices should maintain normal operation, the transmitting end and the receiving end must send and read data at the same time to ensure the correctness of the data, otherwise the transmitting end has transmitted the next data status, and the receiving end Only when you start receiving the data will cause an error. Therefore, whether it is between the digital device and the component, between the processor CPU, or between the two electronic devices, a mechanism for simultaneously operating the two ends is required, so that the digital signal can be processed normally. . m For all seQuential circuits, the avoidance action is related to the clock, and the system clock provides a periodic timing clock for the basic 4-sequence unit. As the same as 5 19197 1342477 • Step signal. There must be an electronic component called a clock generator (clock ge 槪 ) ) in the digital product. This component will continuously generate a stable interval of electrical waste pulses. All the electronic components in the product will follow this time. Pulse to synchronize = advance: operation action. Simply put, digital products must be controlled by time to accurately process digital signals. If the clock is unstable, the error in the digital signal transmission will cause the digital device to malfunction. ... For the A motherboard, the central processing unit ((10), memory (Memory) and many peripheral devices on the computer motherboard must be divided into the same work: when the material exchange or mutual contact, it is even more difficult to make mistakes. ==!Common timing specification for correction or coordination reference, this rule is the clock generator. The frequency is set and the frequency is used to make the c-key;: = : = the reference frequency in MHz. (megahertz). In the early days: the speed of synchronous operation between the memory and the motherboard is equal to the FSB, and: I can be understood as the CP[], the synchronization between the two parties. The connected limbs are connected, and the two can not be phased by π β H (four). The two are not the same. But the meaning of the FSB still exists on the basis of the FSB, multiplied by two. Zhongda now 'this multiple can be greater than', can also be counted in the early PC era, for example, PC_XT, t:. The system frequency is basically generated by the quartz vibration inside the brain. Quartz in the 诵When the electrons of the wave of UrystaI oscuiator shrink Will generate (4) ... motherboard circuit and then convert the sine wave into a digital position] 9] 97 6 丄 · 34 Ζ 4 / /, the heart and 1 pulse, gp 4, also become a clock signal in the far road. Because of the vibration of quartz The frequency of the soup frequency is fixed, the helmet method, the vibration frequency of the vibration source 1 need to be used in a wide range of frequencies, and when the circuit is practical. The frequency of the sheep, the use of multiple quartz oscillator crystals, some do not deal with the motherboard, cry, Β 4 4 ^ pieces have 苴工竹. 0 Θ film group and main memory and other major meta-laws [Μ, / pulse, CPU, cpu external frequency according to Moer Formally coming. CP;:: Where T_z is above the FSB multiplied by the multiplier to produce the processor internal frequency, which is directly provided by the processing of the crying and parallel circuit board clock. "°. (7) The chips are connected by a front-end bus bar (FSB) to the CPU.

The FSB is the benchmark, and the monthly slash... Two A and two are reversed to the fourth (four) s data outside the CPU (four), so the 2 Hz ^ multiplier can get the FSB speed of _MHz. Memories Qiu also follows the footsteps of the CPU, and the work is also the same as the month. / Yu Nan 2; 7 speed advance to 2 〇〇 MHz right basin m:, PCI, USB and other bus bars are _ and so on. If the PCI is 3, the maximum advantage of the crystal oscillator is the correct reliability of the frequency. The correct frequency can be obtained by multi-vibrating the quartz crystal components of the h core. However, because the manufacture of the vibrator is a mechanical process, the manufacturer will mass-produce the standard at a specific working rate, and then add new frequencies to the standard catalog according to market demand. If a product requires a non-standard frequency, the use of a crystal resonator may cause serious delays in the development plan, as it takes longer for the manufacturer to crack the sample and production schedule. J9]97 7 1342477· • ———— _6τν *7^-. - Again, the clock generator can only generate a fixed clock frequency, which is fixed at the frequency of generating a certain frequency, so the FSB is supplied. The frequency of the FSB is fixed at a certain value. Even when the CPU needs a higher FSB to speed up the work processing speed, or when the demand for the hage is reduced, the work can be reduced and the lower external frequency can be used. Crystal 7 power consumption _ 'Because the clock generator can only generate a fixed clock frequency, it is still impossible to do.' So how to find a signal generation system that can provide multiple clock frequencies as external frequencies for the chip, for example, Cpu, is a problem to be solved. SUMMARY OF THE INVENTION The main object of the present invention is to provide a signal generating system and method for use in a chip working environment, which can provide multiple clocks for external frequency for use in a wafer. ,

Another object of the present invention is to provide a signal generating system and method for use in a chip working environment in which at least one of the chips can be set via the serial signal interface to set the operating mode and output frequency of the signal generating system. And storing the working mode and the output frequency setting value in the EEPROM module of the signal generating system, the signal generating system can provide different frequencies of the FSB for the wafer according to the working condition of the chip, and can be used according to the chip. The actual working conditions' can provide external frequencies of different clock frequencies for the wafer to use. Another object of the present invention is to provide a signal generating system and method for applying to a wafer working environment. When a wafer requires a higher FSB to speed up the processing speed, a higher clock frequency can be provided. The external 19197 8 1342477 frequency-providing chip to use the present invention is to provide a signal generating system and method for applying to the working area of the chip, and when the wafer processing operation needs to be reduced, the lower one can be supplied. The daily pulse frequency is used as an external frequency for the wafer to use, and the power consumption of the chip is reduced. Root ί urine above, eight 』 one? The system and method of generating a clock (cl0ck) signal is provided to one or more = B slices. The signal generation system uses at least one or more chips for the signal generation method: The working mode and output frequency of the system 2 can be set via the serial signal interface, and the output mode setting value of the working mode 2 is stored in the EE mode of the signal generating system: the actual working condition of the chip 'And can provide different frequency of the external frequency transmission 'solid above the chip use '俾 let this signal to generate system conditions, day and day, this work in the effective energy and / or power saving, for the wafer , does not control to the work ^θ port is limited to the early working frequency relationship; work this and / or increase the power consumption when unnecessary. The signal poisoning & module of the present invention generates a secondary system and an output group by frequency generation, and outputs two or more frequencies and outputs to an output mode or a wired transmission mode, and transmits more than 5 frequencies to wirelessly transmit and / Used as a FSB. One or more wafers, and for the purpose of familiarizing themselves with the inclusions, the following features and functions of the invention are described in detail by the following: "column" and With the attached drawing 'on the hair 19' 97 9 i^2477f • » »

[Embodiment J 1f Deduction Application The system architecture of the production system of the present invention and the cooperation with the signal generation system are:: not intended. As shown in the figure], the signal generation system! Package 2 and output module 3. Frequency generation sub-system, into a variety of clock frequencies, spleen sputum, Besun module 3. Output, /μ Γ: A variety of time-frequency transmission to the output ^ is responsible for a variety of clock frequencies as FSB transmission to the younger brother] The picture shows a system block or more of the chip, for example, CPU, single chip, w also 廿 + use Here, if the clock frequency transmission side ~, the group 3 will use its helmet line as the ... spring transmission, then the output mode μ mountain ... output - the human group 31 will give the clock frequency to the $ chip end, if For the wired transmission mode, the transmission::: is transferred to the crystal line mode to replace the clock frequency, and the output group 3 can use the transmission method of the pin number, and the ^^ chip end is the end clock frequency signal. The 2', 疋.,,, reel demand for the module 31 is not. The picture of the younger brother is the sub-system of the system to generate the sub-system. The structure of the sub-system is not as good as the frequency of the sub-system. The configuration structure of the instance is known; 2 contains, ^ mouth armor does not, system 21, at least one gentry more than one PLL phase-locked circuit sub-system 22, at least one of the day of the pulse setting (coniiguration) module vibration I module 24. ^ _ _ group 23, and at least one or more frequency generation sub-system frequency generating device, ',, with one or more kinds of synchronization output on the vibration module 24, square, frequency generation sub-system 2 has at least one to face the frequency through the serial interface: no need to: connect any oscillating components to work, can be sub-system 2 to generate the secondary system 2 for dynamic programming, frequency generation μ bandwidth, can be from several hundred kHz to a few GHz range, for example 19197 10 1342477, eg, ΙΟΟΚΗζ~2GHz. At least one of the thoughts y / Japanese film 4 can be serialized via SCL (c 1 ock) input line (for editing, 彳) human SDAT serial data (serial data), input line (for Chiang ^ α ) For the frequency generation sub-system 2 clock setting module 2 2 working mode is known to the mountain, know the frequency to be set 'and the working mode and output frequency set value to save ^ ^ ' 仔 万 'frequency The EEPR0M module 23 of the secondary system 2 is generated, and the EEPR0M is only in the Wu group 23. Gentry. The working mode of the 1 inch pulse state and the output frequency setting value allow the frequency w ## I, 成人糸2 to quickly switch between multiple clock states during startup and operation. By at least one of the above-mentioned Japanese and Japanese 4 pairs of the % pulse setting module 22, the squeaking of the yoke can be determined as follows: the current i's _^#^, _^ phase-locked loop subsystem 21 __ module 23 = The value in the setting module 22 is stored in the Japanese 士士*., Therefore, only the output frequency and the working mode are changed, and the clock setting module 22 is re-programmed + t # π can be derived from at least one of a Heavy: Wide and the reprogramming is completed, and the SDAT and SCL signals of the Japanese film 4 are here. SDAT is serialized. (...data), and SCL For the sen 才 ( (senal ci〇ck). : The clock signal ακ generated by the group 24 can directly UT UT0 and the clock signal n! is the PLL phase-locked loop 対 eight ♦ 卜 '% pulse signal CLK via the milk to do the round frequency processing and then send to the time Pulse CLK. Frequency generation A / / "唬(1) is the main oscillation clock signal 3 connection, ^^ round output 0UT〇, 〇UT1 and output module Π1, and ^/吴, group 3 will come from the output pin _ The output signal "from the output signal 222 of the output pin 0UT1 is transmitted to at least one of the wafers 4 by using 19197 11 1342477 lines and/or wireless transmission patterns. The f / 3 picture is a block diagram for displaying as The configuration architecture of one embodiment of the phase-locked loop secondary system in Fig. 2; as shown in Fig. 3, the PLL phase-locked loop subsystem 21 includes a pFD phase/frequency detector 211 (Phase Fre ( Luency Detect〇r), charge pump 2l2 (charge

Pump), LPF loop filter 213 (Lo〇p Filter), VCO voltage control oscillator 214 (v〇ltage Controled Oscillator), frequency divider. ZbCDwider, l/N), number q counter (qc〇unter) 2l6, and the number • P counter 217 (P Counter). The pll phase-locked loop subsystem 21 only needs to provide a reference frequency signal Fref by the oscillating module 24, for example, a main oscillating clock signal (^) (and using a phase-locked loop, combined with a frequency-dividing circuit module, can generate a plurality of The frequency of the clock, and the various clock frequencies are transmitted to the output module 3 for use by at least one of the solar modules 4. The PLL phase-locked loop (PhaseLockedLoop) can precisely control the clock frequency, the user can The PLL phase-locked loop is used to design the #frequency control loop, which simplifies the circuit complexity and increases the accuracy. As shown in Figure 3, the PLL phase-locked loop subsystem 21 is basically an op amp-like negative feedback electronic circuit. Structure, PLL phase-locked loop - the input terminals of the system 21 respectively input Fref and Ffb frequency signals, where 'Fref is the reference reference frequency provided by the oscillation module 24, and Fib is the return frequency, the two input signals Before Fref and Ffb are input to the PFD Phase/Frequency Detector 211 (Phase Frequency Detector), the reference CFC frequency Fref will be input to the Q-counter 216 first, and will be (Fref /q) after being processed by Q. The signal, and the feedback frequency 卩丨匕 is processed by 12 19197 1342477 (Ffb/P) first input to the number P counter 217, and is divided by the clock signal. The charge pump 212 is used to receive the phase/frequency by the PFD. Detector 2 ιι 幸 两 两 卯 卯 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 10 10 10 10 10 /frequency detector 211 will compare the difference between the reference reference frequency (=/Q) and the feedback frequency b/P), and detect the difference between the == and the fresh, when the reference reference frequency is added (4)) When the frequency is higher than the return frequency (m/P), that is, when (Fre(10)) leads (Ffb/p), the up 冋 potential output speeds up the Fout frequency. The upper end of the pFD phase/frequency detector 211 outputs Up. If the reference reference frequency is lower than the feedback frequency (Ffb/P), the PFD phase/frequency detector 2D will output the Dn pulse, that is, when (Fref/Q) is behind (Fvc〇/p) When (10) the potential is turned out to slow down the Fout frequency; the charge pump 212 converts the difference of the phase virtual frequency into an analog voltage output signal And suddenly wave LPF circuit 213 using a control voltage required for 214 -m 'example' low-pass filter, and the high frequency wave signals in addition to suddenly and provides a voltage controlled oscillator vco disc. The charge pump 212 is used to receive the 卯 and DN (d〇Wn) signals output by the PFD phase/frequency detector 2U. If the two signals are high level signals at the same time, the charging pump 21 2 circuit will be faulty. action. The clock signal generated by the PFD phase/frequency detector 211 is then passed through a charge pump 212 (Charge Pump) and an LPF loop filter 213 (L〇〇p

After the action of Filter), it is converted into the control voltage of the last-order Vc〇 Voltage Controlled Oscillator 2l4 (Voltage Controled Oscillator), VC0 13 J9197 1342477 Voltage Controlled Oscillator 214 will output Ff b clock m dream. # vrn技 • 〇14^ψ,^ . Kong Tong. The clock signal of the VCO voltage controlled oscillator.*, the feedback frequency Fib can be used to lock the input registration frequency Fref, and the phase and frequency of the fish reference frequency / soil half-test frequency Fref synchronization Hey. Apricot to the husband &furnace; the trailer - + * test frequency Fref and input back: two - the frequency and phase - when the time - that is, the entire phase circuit is locked (Locked) state. The feedback frequency Ffb can be changed to the output frequency of the frequency (嶋) by the frequency divider, and the output frequency signal is the 222 of the 〇υτ丨 end, and the output frequency signal is The frequency is (Ffb/N), and the frequency is cried. The output frequency signal F〇ut is output to the output mode PLL phase-locked loop sub-system 21 via the 〇UT1 terminal. The system is basically a negative feedback system, which is utilized in the loop. The feedback signal, the signal frequency and phase of the output, is locked - at the frequency and phase of the reference reference frequency Fref at the input. The PFD phase/frequency detector 211 compares the difference between the phase and the frequency between the reference reference frequency Fref and the feedback frequency Ffb 2 , and detects the difference between the phase of the phase and the frequency difference of the frequency to affect the vc pressure. The frequency of the oscillator 214 is controlled. Ffb is output. When (Fref/Q) leads (Ffb/P), the UP high-potential output speeds up the Fout frequency; conversely, when (Fref/Q) falls behind (Ffb/p), the (10) high-potential output slows down the Fout frequency. Finally, the stable output state can be achieved as indicated by the formula. Therefore, it is only necessary to adjust the ratio between the P, Q, and N values of the PLL phase-locked loop subsystem 21 to obtain the required output frequency Fout °. The two input terminals of the PLL phase-locked loop subsystem 21 are the reference test-frequency Fref and the feedback frequency Ffb, and the output is the phase lock characteristic of the output frequency signal 19197 14 phase loop, when the PLL lock loop is locked. In the state of the PFD phase/frequency detector (1), the frequency and phase should be equal, & (Fref / Q) = (Ffb/P), thus, Ffb_ "fp 215 becomes the output after dividing N, ~" P ) /Q], when Ffb is de-frequency sitter.., DT T ^ gives the dry signal Fout, that is, Fout=Ffb/N, so the 'PLL phase-locked loop · 糸 糸 . ·. The turn-out frequency is F〇ut=[(Fref not H) / (Q 氺N )]. It can be expressed as: N-value of the phase-locked loop sub-system 21 except for the frequency, the variation P, Q, n ^ = ratio ' can be generated by at least one reference reference frequency (four) signal ^ i The various frequencies required in 4" Figure 4 is a flow chart showing the process of applying the system to the signal generation method - the process program. As far as the 4th θ is far, the steps are first. 1 (n 'frequency generation time m transmits the generated frequency to the output module 3, and proceeds to step 102. In step 102, the output module 3 transmits the frequency generated by the frequency generation subsystem 2 to the cable transmission mode to - One or more wafers 4 to complete the signal transmission process. 7. Figure 5 is a flow chart showing the process flow applied to the generation of the signal generation method in the figure! As described in the figure, first in step 201, the frequency generation subsystem 2 transmits the generated frequency to the wheeling module 3, and (4) step 2〇2. ] 5 1919? 1342477. 2〇2 'output module 3 Generate the frequency generated by the secondary system 2: two wireless transmission side The method of transmitting the signal to the one or more wafers 4 by using the wireless output sub-module 31 to complete the signal transmission process. The second figure is a working flow diagram, wherein the display is applied to the 祗5 tiger generated in the second figure.糸 以 以 以 讯 讯 讯 μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ 。 。 模组 模组Subtract 2 operating mode and turn-off (based on the set value frequency generation sub-system 2 will generate the frequency pass (four) output module 3 'and go to step 3 〇 2. = step 3G2, output module 3 will generate the frequency The frequency, the line transmission mode, is transmitted to one or more: the signal transmission process is completed and generated. The figure 7 is an operation flow chart, wherein the display is applied to the wide picture in the first picture: the raw system for signal generation method Another flow program. As before step 4〇1, the frequency generation subsystem 2 will read the frequency of one of the frequencies and generate the operation mode and output of the subsystem 2, and again, according to the settings. The value frequency is generated by the secondary system. The system 2 will generate the frequency of the transmission ❹m out of touch 3, the money to Step 4G2. Cheng: γ ^ 402 'The output module 3 generates the frequency generation subsystem 2: the frequency is transmitted in the wireless transmission mode, and is transmitted to more than f wafers 4 by the wireless output sub-module 3 to complete the signal transmission. Process. Fig. 8 is a flow chart showing the flow of the signal generation method applied to the signal generation system in Fig. 2, and the flow program is generated. As shown in Fig. 7, the oscillation module 24 is generated. Clock signal clk. J9J97 】6 1342477 〇t Step 5G2' The clock signal CLK can be directly transmitted to the frequency generation time 'Ding', where Ol) T0 will output the clock signal 111. Ί 503, the clock signal CLK can be output via the pll phase-locked loop B:r (4) and then transmitted to the freshly generated sub-system 0UT1 to output the clock signal 222. _ will or out / _ 504, the output module 'group 3 will 〇ϋΤ 0 clock signal 111 and / " clock signal 222 to wire transmission and / or helmet line transmission 1 to - or - In the way of ρ h ... fruit pass, the process. The upper part of the film 4 is completed and the signal is generated and transmitted. The back L9 picture is the operation flow chart, which shows the application to the picture in Fig. 2 = the process of generating the signal.斤不,, in step 601', the output frequency of the clock-setting module-frequency generation subsystem 2 is false:,, in 23, the θ rate and the working mode value can be stored in _桓4 and the pulse setting changes. It is only necessary to re-program the time, and re-programming when the output is in the working mode, and the re-programming action can be completed by the signals from the B DAT and SCL, and proceeds to step 6〇2. The clock module CLK is generated by the oscillating module 24 at the beginning of the second step. Li Tong ^ ΓΓ 03' clock signal CLK can be directly transmitted to the frequency generation second. OUTO will output the clock signal 1 1 1 . = Step, 604 ′ The clock signal CLK can be output to the 0UT1 4 pulse signal 222 of the frequency generation subsystem 2 via the frequency division process like the phase-locked loop. 〇叮1 will be in step 605, 屮Μ έΒ Λ Λ τ τ η η 杈 group 3 will OUTO clock signal 1η and / 19197 17 2... TI 4 M Λ 5 Tiger 222 with cable transmission and / or wireless transmission The method, through ^ to one or more crystals and the other 4 to complete the signal generation and transmission = MU is - operation flow chart, which shows the poem in Figure 2, ° ^ ^, the system to generate signal generation method - Process program. For example, in step 701, after the signal generation system is started, the clock and 22 read the frequency generated by the system generated in the ΕΕΡ_module 23 to generate the I frequency and the operating mode set value. The vibration module 24 will generate the clock signal CLK. System Μ ^ Step 7〇2 ′ The clock signal CLK can be directly transmitted to the frequency generation sub-, and the OljT0 outputs the clock signal 111. The 703 ′ clock signal CLK can be transmitted to the frequency generation subsystem 2 via the frequency division processing of the pLL phase-locked loop sub-section to output the clock signal 222. Or the 'output module 3' will process the coffee clock signal 111 and / pass 'off $ one of the % pulse heart tiger 222 in a wired transmission and/or wireless transmission mode. The above-mentioned ship 4 and the digital signal generation and transmission embodiment 'we can obtain a signal production system of the present invention = Γ, ' is applied to the chip working environment, the signal is generated on the system or wireless way When the pulse signal is supplied to one or one pass, the 'signal generation system can generate a signal generation method. The wafers of more than two tons can be output through the serial signal interface, which generates the working mode and wheel of the system. The frequency is set and the work 18 19197 mode and output frequency are involved.

In the 槿 group, the values of 3 and 卞6 are stored in the EEPROM of the signal generation system. Γ11 The system is based on the actual working condition of the chip, and the output of the external system can be raised. 4 use, 俾 let this signal generation system, for =, can work at the most efficient and 7 or power saving limit to 5 'will not be invented due to the single-operating frequency relationship and / or not Increase power consumption if necessary. The advantages of the system and method of the present invention are as follows: 1. 1 providing a plurality of clock frequencies as external frequencies for use by the chip, at least the chip can be used to generate the system material and output frequency via the serial signal interface. Set and work mode and output frequency.疋 (4) stored in the EEp_ module of the signal generation system, and can provide external frequency of different clock frequencies for the wafers according to the situation of the satellite. z. The wafer needs a higher FSB to speed up the work. When the processing speed is high, the higher clock frequency can be provided as the external frequency for the wafer to be used, and when the processing demand of the crystal chip is reduced, the lower clock frequency can be provided, and the frequency is used for the chip, and the frequency is lowered. The chip consumes power. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications that are made without departing from the spirit of the present invention are The following patents are included: [Simplified Schematic Description] Fig. 1 is a system block diagram showing the system architecture of the signal generating system to which the present invention is applied and the operation diagram of the wafer in cooperation with the signal generating system; 19197 19 1342477

Figure 2 is a sub-system block diagram showing the configuration architecture of the first embodiment of the first rate generation subsystem, and the third diagram is a block diagram for displaying the pll lock loop subsystem as shown in Fig. 2. The configuration architecture of an embodiment, and FIG. 4 is a flowchart of operation, in which the signal application method for the signal generation method in the i-th diagram is displayed;

. Figure 5 is a flow chart showing the flow of the five-hole 唬 system used in the figure to generate a signal generation method; 苐6 is a working flow chart, and the display is applied to Figure 1. The signal generates a further process procedure for the signal generation method; FIG. 7 is a flow chart showing another flow program applied to the nickname generation system in FIG. 1 for the signal generation method; Figure 8 is a flow chart showing the flow of the signal generation system applied to the signal generation system of Figure 2 for a signal generation method; Figure 9 is a flow chart showing the signal applied to the second diagram. A flow program for generating a system for signal generation; and FIG. 10 is a flow chart showing a flow program applied to the signal generation system of FIG. 2 for signal generation. [Main component symbol description] 1 Signal generation system 111 Output signal 1 Frequency generation subsystem 21 PLL phase-locked loop subsystem 211 PFD phase/frequency detector 19197 20 1342477· 212 Charge pump 213 LPF loop filter 214 VCO voltage-controlled oscillation 215 frequency divider 216 number Q counter 217 number P counter 2 2 clock setting module 222 output signal • 23 EEPROM module 24 oscillating module 3 output module 31 wireless output secondary module 4 chip 0UT1 output pin OUTO output Pin CLK clock signal

Claims (1)

Lu I, patent application scope: P signal generation method is applied to the 旒 generation method, including the following procedures: The output frequency and working mode of programming the clock setting module, when the change can be set to the clock setting module The editing may be performed by at least one of the serial clock signals; setting the clock setting module; \ Τ -91Ϊ4 /: the chip working environment 匕Ύ, determining the frequency generation sub-system variable output frequency and The working mode range, and the reprogrammed serial data of the moving chip and the threshold value stored in the EEPROM module/arc oscillating module are transmitted to the output mode by the frequency division processing of the phase locked loop system. And causing the output module to generate at least one or more of the wafers by the frequency system. Material transmission: The signal generation method as described in item j of the patent scope, =mode: the frequency generated by the frequency generation subsystem is transmitted to at least one of the wafers by wire transmission. Such as the scope of patent application! The signal generation method described in the item, = modulo: transmitting the frequency generated by the frequency generation subsystem to the at least one wafer by wireless transmission. - The nickname generation system is applied to the wafer work. The number generation system contains: Brother. f frequency generates the frequency to generate less than - more than one type of clock frequency, and generates at least two = 19197 (the clock frequency of repair 22 is transmitted to the output module; and the output module, which is responsible for - When the pulse frequency is transmitted as an FSB, at least one or more b曰: when the slice is more than one type, wherein the frequency generation subsystem includes at least one or more pu locks and more PU phase-locked loop times...":, First, the at least the pulse signal is divided, and the word is transmitted from the vibration surface group to the clock module of the clock module after the frequency division process is at least one or more. The chip can be programmed via the serial clock and the serial data input line of the staff and the serial data input line. Now, more than one clock setting module is programmed to operate the mode and output frequency of the system. Set, and save the working ° and the output frequency setting value in the EEPROM, to more than v EEPROM modules, the at least one EEPROM module can store the set value of the gas rate; Mode and output frequency above The oscillating module, the at least one vibration and the generated clock signal can be directly transmitted to the output module, so that the 'clock signal is passed through at least one or more PLL phase-locked loop times>, the first knife frequency After processing, it is sent to the wheel-out module. For example, the signal generation system described in claim 4, wherein the smart board group includes a wireless wheel-out module, the wireless transmission sub-module will transmit the pulse frequency wirelessly. Mode, transmitted to at least one crystal 19197 (revision) 23 5. 6. The signal generation system described in claim 4 or 5, teaches that the PLL phase-locked loop subsystem includes; SI frequency f detector, the phase/frequency detector will compare the 12th. The first frequency of the output end and the second frequency of the second counter wheel output, the difference between the phase and the frequency is detected. If the phase/frequency detection between the two frequencies is cried, ρ is located at: the first frequency, then the clock frequency is increased. If: the second will make the frequency divider's bit/frequency detector DNQ: Yu Di 2 Frequency, then the phase frequency is reduced; The output of the second pump 'the charge pump charge pump will be the first - signal virtual number: ... the difference between the bit and the frequency is converted into analog voltage wheel, the wave device, the circuit wave filter uses a chopper And the material pressure control oscillator, the two required control voltage; sent to the frequency divider to perform the frequency division of the clock frequency, the pulse frequency can be regarded as the feedback frequency and loses eight:: Control: Chen Guanglun At the time of the second clock, the signal from the signal is transmitted to the output mode: and the first counter of the pulse is processed after the frequency division process, the first clock is generated. The oscillation module is generated as an input terminal. The receiving from the number is divided by any first positive: wide #': and the received clock signal is transmitted in the form of the first signal by 19197 (revision) 24^42477 to the phase/frequency detector; a second counter, the second counter input receiving a clock frequency from the output of the voltage controlled oscillator, the clock signal being a feedback frequency, the first counter dividing the received feedback frequency by any number After a positive integer, 'transfer to the phase in the form of the second signal/ Rate detector. 7. The signal generation system according to item 6 of the patent application scope, wherein the proportional relationship between the positive integer of | / i and the second positive integer affects the clock signal after the frequency division and frequency division processing. 8: The signal generation system described in claim 5, wherein the chip is a CPU. 9. The signal generation system described in item 6 of the Chinese patent scope, wherein the day and the day are CPUs. 10. ^ The signal generation system described in claim 7 of the patent scope, wherein the day and the day are CPUs. 】9]97 (revision) 25