CN117595861A - Acquisition and data processing system for high-speed digital signals - Google Patents
Acquisition and data processing system for high-speed digital signals Download PDFInfo
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- CN117595861A CN117595861A CN202311574630.5A CN202311574630A CN117595861A CN 117595861 A CN117595861 A CN 117595861A CN 202311574630 A CN202311574630 A CN 202311574630A CN 117595861 A CN117595861 A CN 117595861A
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- 238000004806 packaging method and process Methods 0.000 claims abstract description 8
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- 238000003708 edge detection Methods 0.000 claims description 4
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
Abstract
The invention discloses a collection and data processing system for high-speed digital signals, which belongs to the technical field of high-speed digital signal processing and comprises the following components: the clock data recovery module adopts a multiphase clock and a data delay dual channel to carry out mixed sampling, and uses a low-frequency clock to acquire high-rate differential signal data so as to acquire oversampling data; the clock locking module is electrically connected with the clock data recovery module and is used for selecting an adaptive low-frequency clock according to the differential signal data; the data processing algorithm module is electrically connected with the clock data recovery module and is used for carrying out downsampling processing according to clock information corresponding to the low-frequency clock and generating parallel signals according to the oversampling data; the encoding and decoding module is electrically connected with the data processing algorithm module and is used for locking and aligning the clock and the data according to the parallel signals and the set protocol content, and packaging and outputting; the invention has a pure digital circuit structure and high portability.
Description
Technical Field
The invention relates to the technical field of high-speed digital signal processing, in particular to a system for collecting and processing high-speed digital signals.
Background
In high speed transmission communication systems, clock data recovery (Clock and Data Recovery, CDR) circuits are often used to ensure that the transmitted input data can be read correctly; in the prior art, in order to ensure higher universality and portability of the circuit, the circuit is generally realized by adopting a digital circuit, but if the circuit is implemented by adopting an all-digital circuit, the problem that the tracking phase capability is poor due to the limitation of time sequence delay and the like is caused; therefore, there is an urgent need to design a new acquisition circuit and data processing technology for high-speed digital signals to overcome the problems of the full digital circuit in the implementation process.
Disclosure of Invention
In order to solve the above-mentioned problems, the present invention provides a system for collecting and processing high-speed digital signals, which is applied to a differential signal interface without clock, and comprises:
the clock data recovery module adopts a multiphase clock and a data delay dual channel to carry out mixed sampling, and uses a low-frequency clock to acquire high-rate differential signal data so as to acquire oversampling data;
the clock locking module is electrically connected with the clock data recovery module and is used for selecting an adaptive low-frequency clock according to the differential signal data;
the data processing algorithm module is electrically connected with the clock data recovery module and is used for carrying out downsampling processing according to clock information corresponding to the low-frequency clock and generating parallel signals according to the oversampling data;
the encoding and decoding module is electrically connected with the data processing algorithm module and is used for locking and aligning the clock and the data according to the parallel signals and the set protocol content and packaging and outputting.
Preferably, the clock data recovery module is configured to perform oversampling according to the sampling rate being more than twice the data rate, so as to obtain oversampled data.
Preferably, the clock data recovery module is further configured to detect a jump edge of the oversampled data, determine an occurrence position of the metastable state, and select reliable data for storage.
Preferably, the clock locking module is further configured to capture transitions of the differential signal data by using an edge detection and timer, lock the clock and the data phase by using a method of adjusting the data delay according to the characteristic of 8b10b coding, determine whether the clock and the data match, and obtain an adapted low frequency clock.
Preferably, the clock data recovery module is further configured to encode the differential signal data according to the 8b10b code provided by the codec module, and generate oversampled data.
Preferably, the encoding and decoding module is further configured to add other protocols by customization according to the 8b10b encoding, so as to improve the degree of freedom of data, and improve the security and reliability of data by adding encryption or data packets.
Preferably, the encoding and decoding module is further configured to obtain a protocol of the external signal through the protocol configuration interface, add the protocol to the 8b10b code, and send the packed data to a sending end of the external signal.
Preferably, the encoding and decoding module is further configured to retransmit the packet header for alignment after the packetized data is sent to a certain length.
Preferably, the protocol configuration interface is further configured to configure the protocol content and the data format between the codec module and the transmitting end, and the maximum continuous transmission length.
Preferably, the high-speed digital signal is processed by the acquisition and data processing system, comprising the steps of:
the method comprises the steps that firstly, a high-speed digital signal is sent to a clock data recovery module through a differential signal interface to conduct initial data sampling, and a plurality of clocks are used for sampling data and delay of the data to obtain multiple oversampling data;
secondly, sending the initial sampling data into a clock locking module, analyzing and giving clock information by detecting the frequency locking data rate of data jump, adjusting the delay of the data according to the clock information, and sending the clock information back to a clock data recovery module for recovery;
thirdly, inputting the oversampled data and clock information into a signal processing algorithm module for downsampling, obtaining reliable data according to the clock information and a calculation result and converting the reliable data into parallel signals;
and fourthly, inputting the data and the clock in the parallel signals into a coding and decoding module, locking and aligning the clock and the data according to the protocol content in the coding and decoding module, packaging the data, transmitting a certain length, and then retransmitting the packet head for alignment.
The invention discloses the following technical effects:
the invention is a pure digital circuit structure and has very high portability;
the multi-time sampling is realized by adopting a multi-phase clock and data delay mode, and the required clock frequency is low and the stability is high;
the protocol part of the invention can be customized by a user and is applicable to various environments;
the invention is a universal data receiving terminal, and the sampling rate can be changed by changing an external clock.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a system according to the present invention;
fig. 2 is a schematic diagram of a clock data recovery process according to the present invention.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
As shown in fig. 1-2, the present invention provides a system for collecting and processing high-speed digital signals, which is applied to a differential signal interface without clock, and comprises:
the clock data recovery module adopts a multiphase clock and a data delay dual channel to carry out mixed sampling, and uses a low-frequency clock to acquire high-rate differential signal data so as to acquire oversampling data;
the clock locking module is electrically connected with the clock data recovery module and is used for selecting an adaptive low-frequency clock according to the differential signal data;
the data processing algorithm module is electrically connected with the clock data recovery module and is used for carrying out downsampling processing according to clock information corresponding to the low-frequency clock and generating parallel signals according to the oversampling data;
the encoding and decoding module is electrically connected with the data processing algorithm module and is used for locking and aligning the clock and the data according to the parallel signals and the set protocol content and packaging and outputting.
Still preferably, the clock data recovery module for a high-speed digital signal acquisition and data processing system according to the present invention is further configured to perform oversampling according to a sampling rate that is more than twice the data rate, so as to obtain oversampled data.
Further preferably, the clock data recovery module for the high-speed digital signal acquisition and data processing system provided by the invention is further used for detecting the jump edge of the oversampled data, judging the occurrence position of the metastable state, and selecting reliable data for storage.
Further preferably, the clock locking module for the high-speed digital signal acquisition and data processing system provided by the invention is further used for capturing jump of differential signal data by adopting an edge detection and timer, locking a clock and a data phase by using a method for adjusting data delay according to the characteristic of 8b10b coding, judging whether the clock and the data are matched, and obtaining an adaptive low-frequency clock.
Still preferably, the clock data recovery module for a high-speed digital signal acquisition and data processing system according to the present invention is further configured to encode differential signal data according to the 8b10b code provided by the codec module, and generate oversampled data.
Further preferably, the codec module for the high-speed digital signal acquisition and data processing system according to the present invention is further configured to increase the degree of freedom of data by adding other protocols through customization according to 8b10b encoding, and increase the security and reliability of data by adding encryption or data packets.
Further preferably, the codec module for the high-speed digital signal acquisition and data processing system provided by the invention is further configured to acquire a protocol of an external signal through a protocol configuration interface, add the protocol into the 8b10b code, and send the packed data to a sending end of the external signal.
Further preferably, the codec module for the high-speed digital signal acquisition and data processing system according to the present invention is further configured to retransmit the packet header for alignment after the packetized data is sent to a certain length.
Further preferably, the protocol configuration interface for the high-speed digital signal acquisition and data processing system provided by the invention is further used for self-configuring the protocol content and the data format between the coding and decoding module and the transmitting end and the maximum continuous transmission length.
Further preferably, the present invention processes high-speed digital signals by an acquisition and data processing system, comprising the steps of:
the method comprises the steps that firstly, a high-speed digital signal is sent to a clock data recovery module through a differential signal interface to conduct initial data sampling, and a plurality of clocks are used for sampling data and delay of the data to obtain multiple oversampling data;
secondly, sending the initial sampling data into a clock locking module, analyzing and giving clock information by detecting the frequency locking data rate of data jump, adjusting the delay of the data according to the clock information, and sending the clock information back to a clock data recovery module for recovery;
thirdly, inputting the oversampled data and clock information into a signal processing algorithm module for downsampling, obtaining reliable data according to the clock information and a calculation result and converting the reliable data into parallel signals;
and fourthly, inputting the data and the clock in the parallel signals into a coding and decoding module, locking and aligning the clock and the data according to the protocol content in the coding and decoding module, packaging the data, transmitting a certain length, and then retransmitting the packet head for alignment.
Example 1: the invention provides a high-speed digital signal acquisition circuit and a data processing scheme, wherein the circuit is designed as a digital circuit, and aims to improve the speed, the reliability and the portability of data transmission
The digital circuit part of the invention comprises a universal differential data interface, a clock data recovery module 1, a clock locking module 2, a data processing algorithm module 3, a codec module 4, a protocol interface 5 and an external clock 6 for externally supplied clock signals.
The clock data recovery module 1 adopts multiphase clock and data delay dual-channel sampling to be mixed, can acquire data with higher rate by using a low-frequency clock, and realizes over-sampling with sampling rate more than twice the data rate so as to improve the data reliability.
The clock data recovery module 1 detects the jump edge of the over-sampled data, judges the possible occurrence position of the metastable state, and selects reliable data for storage;
the encoding and decoding module 4 provides 8b10b encoding needed by an interface as a basis, other protocols can be added in a self-defined mode on the basis, the degree of freedom is high, encryption or data package can be added according to requirements, and data security and reliability are improved;
the clock locking module 2 captures data jump by adopting edge detection and a timer, judges whether the clock is matched with the data according to the 8b10b coding characteristic and selects an adaptive clock to sample the data.
The invention is mainly applied to clock-free differential signal interfaces such as SerDes, LVDS and the like, and the interfaces have the following main advantages: (1) Reducing wiring conflicts (serial, and no separate clock lines, clock embedded in the data stream, thus also solving the signal clock skew problem that limits the data transfer rate); (2) strong noise and interference resistance (differential transmission); (3) reducing switching noise; (4) strong expansion capability; (5) lower power consumption and packaging cost.
Accordingly, the receiving end needs to introduce a clock data recovery (clock and data recovery, CDR) module for recovering the data and clock to acquire the correct data. The CDR has various structures and schemes, and the invention uses a digital circuit to realize clock data recovery, thereby having higher portability.
The clock data recovery module can also perform data processing once after data acquisition to ensure the alignment of the clock and the data, and the clock data recovery module can be realized by micro-processing or a digital circuit.
The invention relates to a collection circuit and a data processing method for high-speed digital signals, which specifically comprise the following steps:
firstly, data enters a clock data recovery module 1 from a differential signal interface, initial data sampling is carried out according to an external clock 6, a plurality of clocks are used for sampling the data and delay thereof, the acquisition of high-frequency data by a low-frequency clock is realized, and multiple oversampled data are obtained.
Step two, the data is sent into a clock locking module 2, the clock information is analyzed and given by detecting the frequency locking data rate of the data jump, the delay of the data is adjusted according to the clock information, and the clock information is sent back to a clock data recovery module for recovery
And thirdly, the oversampled data and the clock information are input into the signal processing algorithm module 3 for downsampling, reliable data are obtained according to the clock information and the calculation result and are converted into parallel signals, a single data recovery process is shown in fig. 2, wherein the dark color part is error data, and the light color part is stable data.
Fourth, the data and clock are input into the encoding and decoding module 4, the locking and alignment of the clock and the data are completed by the protocol content in the encoding and decoding module, the packet header is retransmitted for alignment after the data are transmitted for a certain length by packing, and the protocol content, the data format and the maximum continuous transmission length can be configured by the protocol interface 5.
The invention is mainly realized by adopting a digital circuit, has higher universality and portability, can detect the rate of input data by adding a clock self-adaption function, and automatically selects a clock; by adding the data processing module, the reliability of the data and the maximum length of continuous transmission are improved.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A system for high-speed digital signal acquisition and data processing, for use with a clocked differential signal interface, comprising:
the clock data recovery module adopts a multiphase clock and a data delay dual channel to carry out mixed sampling, and uses a low-frequency clock to acquire high-rate differential signal data so as to acquire oversampling data;
the clock locking module is electrically connected with the clock data recovery module and is used for selecting the adaptive low-frequency clock according to the differential signal data;
the data processing algorithm module is electrically connected with the clock data recovery module and is used for carrying out downsampling processing according to clock information corresponding to the low-frequency clock and generating parallel signals according to the oversampling data;
the encoding and decoding module is electrically connected with the data processing algorithm module and is used for locking and aligning the clock and the data according to the parallel signals and the set protocol content, and packaging and outputting.
2. A system for the acquisition and data processing of high-speed digital signals as claimed in claim 1, wherein:
and the clock data recovery module is used for carrying out oversampling according to the fact that the sampling rate is more than twice the data rate, and acquiring the oversampled data.
3. A system for the acquisition and data processing of high-speed digital signals as claimed in claim 2, wherein:
the clock data recovery module is further configured to detect a jump edge of the oversampled data, determine an occurrence position of a metastable state, and select reliable data for storage.
4. A system for the acquisition and data processing of high-speed digital signals as claimed in claim 3, wherein:
the clock locking module is further configured to capture a jump of the differential signal data by using an edge detection and timer, lock a clock and a data phase by using a method of adjusting a data delay according to the characteristic of 8b10b coding, determine whether the clock and the data are matched, and obtain the adapted low-frequency clock.
5. A system for high speed digital signal acquisition and data processing as set forth in claim 4, wherein:
the clock data recovery module is further configured to encode the differential signal data according to the 8b10b code provided by the encoding and decoding module, and generate the oversampled data.
6. A system for high speed digital signal acquisition and data processing as in claim 5, wherein:
the encoding and decoding module is also used for adding other protocols through self definition according to the 8b10b encoding, improving the degree of freedom of data, and improving the safety and reliability of the data through adding encryption or data packets.
7. A system for high speed digital signal acquisition and data processing as in claim 6, wherein:
the encoding and decoding module is also used for obtaining the protocol of the external signal through a protocol configuration interface, adding the protocol into the 8b10b code and sending the packed data to the sending end of the external signal.
8. A system for high speed digital signal acquisition and data processing as in claim 7, wherein:
the encoding and decoding module is also used for retransmitting the packet header for alignment after the packed data is transmitted to a certain length.
9. A system for high-speed digital signal acquisition and data processing according to claim 8, wherein:
the protocol configuration interface is further configured to configure the protocol content and the data format between the codec module and the transmitting end, and the maximum continuous transmission length.
10. A system for high speed digital signal acquisition and data processing as claimed in claim 9, wherein:
the high-speed digital signal is processed by the acquisition and data processing system, which comprises the following steps:
the method comprises the steps that firstly, a high-speed digital signal is sent to a clock data recovery module through a differential signal interface to conduct initial data sampling, and a plurality of clocks are used for sampling data and delay of the data to obtain multiple times of oversampling data;
secondly, sending initial sampling data into the clock locking module, analyzing and giving clock information by detecting the frequency locking data rate of data jump, adjusting the phase of data to be matched with the clock phase by the clock information, and sending the clock information back to the clock data recovery module for recovery;
thirdly, inputting the oversampled data and clock information into the signal processing algorithm module for downsampling, obtaining reliable data according to the clock information and a calculation result and converting the reliable data into parallel signals;
and fourthly, inputting the data and the clock in the parallel signals into the encoding and decoding module, locking and aligning the clock and the data according to the protocol content in the encoding and decoding module, packaging the data, transmitting a certain length, and then retransmitting the packet header for alignment.
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| CN202311574630.5A CN117595861A (en) | 2023-11-23 | 2023-11-23 | Acquisition and data processing system for high-speed digital signals |
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