CN117559789A - Implementation method and device for CRM control of two-phase interleaved PFC circuit, storage medium and electronic equipment - Google Patents
Implementation method and device for CRM control of two-phase interleaved PFC circuit, storage medium and electronic equipment Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
- H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The embodiment of the application discloses a method and a device for realizing CRM control of a two-phase interleaved PFC circuit, a storage medium and electronic equipment, and belongs to the field of signal processing. The power control method and the power control device can adjust the duty ratio of two paths of PWM signals in real time, achieve the effect of controlling the phase difference of the two paths of PWM signals to be stable and kept at 180 in real time, increase the power of the whole switching power supply, reduce the loss of the switching power supply in a critical conduction mode, improve the performance index of the system, reduce the ripple voltage and the current distortion rate of the switching power supply, and improve the power density and the efficiency of the whole switching power supply.
Description
Technical Field
The application relates to the field of signal processing, in particular to a method and a device for realizing CRM control of a two-phase interleaved PFC circuit, a storage medium and electronic equipment.
Background
A power factor correction (Power Factor Correction, PFC) circuit is a circuit commonly used in switching power supplies for adjusting the relationship between the active power and the apparent power of the switching power supply, i.e., the ratio of the active power divided by the apparent power. The PFC circuit is divided into: a CCM (current continuous mode) PFC circuit, a CRM (current critical conduction mode) PFC circuit, and a DCM (current discontinuous mode) PFC circuit; whether the PFC circuit is provided with a rectifier bridge is divided into a bridged PFC circuit and a bridgeless PFC circuit. Along with pursuit of power density and power factor of a switching power supply, an interleaved PFC circuit is a common design, the interleaved PFC circuit is to connect two PFC circuits with the same structure in parallel, in order to further improve efficiency of the switching power supply, the interleaved PFC circuit generally adopts a critical conduction mode (current CRM control), namely, a power tube is turned on for a certain time, the power tube is turned off, due to the follow current effect of an inductor, the inductor current gradually decreases, and when the inductor current decreases to zero, the power tube is turned on again, and the cycle is repeated. In the mode, the power tube is opened near zero current, the switching loss of the power tube is greatly reduced, but the switching frequency is changed, so that the loss is reduced, the control difficulty is increased, meanwhile, in order to reduce the current ripple wave and the current distortion rate, two paths of PWM signals with the phase difference of 180 are generally provided for the staggered PFC circuit, however, in the actual work of the power supply, due to the influence of factors such as signal interference or circuit component errors, the two paths of ZCD signals are continuously staggered and overlapped, and the phase difference of the two paths of PWM signals is periodically and circularly changed between 0-360 degrees. Without the corresponding control method and strategy, the two PWM signals cannot be stably maintained around 180 degrees.
Disclosure of Invention
The implementation method, the implementation device, the storage medium and the electronic equipment for CRM control of the two-phase interleaved PFC circuit can accurately generate two paths of PWM signals of 180 degrees in two-phase interleaving. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a method for implementing CRM control of a two-phase interleaved PFC circuit, where the method includes:
after power-on, the loop interrupt timer, the first counter, the second counter, the third counter, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the first zero-crossing detection circuit and the second zero-crossing detection circuit are instructed to start working;
resetting the count value of the first counter when the first zero crossing signal generated by the first zero crossing detection circuit is detected, acquiring the current count value of the third counter, and writing the current count value into a memory;
resetting the count value of the second counter when the second zero crossing signal generated by the second zero crossing detection circuit is detected;
when the nth interrupt signal generated by the loop interrupt timer is detected, the current count value CNT1 of the first counter is acquired n And the current count value CNT2 of the second counter n The method comprises the steps of carrying out a first treatment on the surface of the Reading the latest count value CAP in the memory n And the last count value CAP n-1 According to CAP n And CAP n-1 Calculating the first counterCurrent period value CNTF n And pulling up the count value of the third counter to a preset maximum count value;
calculation of CNT2 n -CNT1 n Is Err_CNT n ；
If Err_CNT n Greater than or equal to 0, according to [ (Err_CNT) n -CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Less than 0, according to [ (Err_CNT ] n +CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n ；
And adjusting the duty ratio of the first PWM signal generator according to the calculated duty ratio adjustment amount: pm1_SET n ＝Duty1 n -Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the And adjusting the duty ratio of the second PWM signal generator according to the duty ratio adjustment amount: pm2_SET n ＝Duty2 n +Adj_Phase n 。
In a second aspect, an embodiment of the present application provides a device for implementing CRM control of a two-phase interleaved PFC circuit, where the device includes:
the indication unit is used for indicating the loop interrupt timer, the first counter, the second counter, the third counter, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the first zero-crossing detection circuit and the second zero-crossing detection circuit to start working after power is applied;
the writing unit is used for resetting the count value of the first counter when the first zero crossing signal generated by the first zero crossing detection circuit is detected, acquiring the current count value of the third counter and writing the current count value into the memory;
a reset unit, configured to reset a count value of the second counter when the second zero-crossing signal generated by the second zero-crossing detection circuit is detected;
an interrupt processing unit for acquiring the current count value CNT1 of the first counter when detecting the nth interrupt signal generated by the loop interrupt timer n And the current count value CNT2 of the second counter n The method comprises the steps of carrying out a first treatment on the surface of the Reading the latest count value CAP in the memory n And the last count value CAP n-1 According to CAP n And CAP n-1 Calculating the current period value CNTF of the first counter n And pulling up the count value of the third counter to a preset maximum count value;
a calculation unit for calculating CNT2 n -CNT1 n Is Err_CNT n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Greater than or equal to 0, according to [ (Err_CNT) n -CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Less than 0, according to [ (Err_CNT ] n +CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n ；
The adjusting unit is used for adjusting the duty ratio of the first PWM signal generator according to the calculated duty ratio adjusting quantity: pm1_SET n ＝Duty1 n -Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the And adjusting the duty ratio of the second PWM signal generator according to the duty ratio adjustment amount: pm2_SET n ＝Duty2 n +Adj_Phase n 。
In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-described method steps.
In a fourth aspect, embodiments of the present application provide an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.
The technical scheme provided by some embodiments of the present application has the beneficial effects that at least includes:
the third PWM signal generator, the third counter and the loop interrupt timer are introduced, the count values of the auxiliary PWM signal and the third counter output by the third PWM signal generator are used as references, the interrupt signal triggers the calculation and adjustment of the duty ratio adjustment quantity of the two paths of PWM signals, compared with the prior art that the first PWM signal generator and the second PWM signal generator are directly controlled to generate two paths of 180-degree PWM signals, the duty ratio of the two paths of PWM signals can be adjusted in real time, the effect of keeping the phase difference of the two paths of PWM signals at 180 is achieved, the power of the whole switching power supply can be increased, the loss of the switching power supply can be reduced under the critical conduction mode, the performance index of the system is improved, the ripple voltage and the current distortion rate of the switching power supply are reduced, and the power density and the efficiency of the whole switching power supply are improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a PFC circuit according to an embodiment of the present application;
fig. 2 is another schematic structural diagram of a PFC circuit according to an embodiment of the present disclosure;
fig. 3 is a flow chart of a method for implementing CRM control of a two-phase interleaved PFC circuit according to an embodiment of the present application;
FIG. 4 is a signal timing diagram of a third counter, a first counter, a second counter, and a loop interrupt timer provided in an embodiment of the present application;
FIG. 5 is a schematic view of the structure of an apparatus provided herein;
fig. 6 is a schematic structural diagram of an electronic device provided in the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the following detailed description of the embodiments of the present application will be given with reference to the accompanying drawings.
Fig. 1 shows a schematic structure of a two-phase interleaved PFC circuit, which may be a bridgeless two-phase interleaved PFC circuit or a bridged two-phase interleaved PFC circuit.
Referring to a bridgeless two-phase interleaved PFC circuit (abbreviated as PFC circuit) shown in fig. 1, the PFC circuit does not include a rectifier bridge, and the PFC circuit includes an AC power source AC, a first inductor L1, a second inductor L2, a first power tube M1, a second power tube M2, a third power tube M3, a fourth power tube M4, a fifth power tube M5, a sixth power tube M6, and a dc capacitor C1. The connection relation of each component in the PFC circuit is shown in fig. 1, and is not repeated here, the power tubes in the PFC circuit may be MOS tubes, and the opening time of the first power tube M1, the second power tube M2, the fifth power tube M5 and the sixth power tube M6 is shorter, which is called a fast power tube; the third power tube M3 and the fourth power tube M4 have long turn-on time, which is called a slow power tube. The first inductor L1, the fifth power tube M5, the first power tube M1 and the third power tube M3 form a main circuit, and the second inductor L2, the sixth power tube, the second power tube M2 and the fourth power tube M4 form an auxiliary circuit. The first PWM signal generator inputs a master PWM signal to the power tube of the master path, and the second PWM signal generator inputs a slave PWM signal to the power tube of the slave path.
Referring to fig. 2, the PFC circuit with bridge two-phase interleaving includes: rectifier bridges (D01-D04), a first inductor L1, a first diode D1, a first power tube Q1, a second inductor L2, a second diode D2 and a second power tube Q2. The first inductor L1, the first diode D1 and the first power tube Q1 form a main circuit, and the second inductor L2, the second diode D2 and the second power tube Q2 form a secondary circuit. The first PWM signal generator inputs a master PWM signal (PWM 1) to the first power transistor Q1, and the second PWM signal generator inputs a slave PWM signal (PWM 2) to the second power transistor.
It should be noted that, the implementation method of CRM control of the two-phase interleaved PFC circuit provided in the embodiments of the present application is generally executed by a device.
It should be understood that the number and connection relationships of the electrical devices in fig. 1 are merely illustrative. Other numbers of components and connections may be used as desired.
The following describes in detail the implementation method of CRM control of the two-phase interleaved PFC circuit according to the embodiment of the present application with reference to fig. 3.
Referring to fig. 3, a flow chart of a method for implementing CRM control of a two-phase interleaved PFC circuit is provided in an embodiment of the present application. As shown in fig. 2, the method according to the embodiment of the present application may include the following steps:
and S301, after power-on, the loop interrupt timer, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the first counter, the second counter, the third counter, the first zero-crossing detection circuit and the second zero-crossing detection circuit are instructed to start working.
After the PFC circuit is powered on, the processor indicates a loop interrupt timer, a first PWM signal generator, a second PWM signal generator, a third PWM signal generator, a first counter, a second counter, a third counter, a first zero crossing detection circuit and a second zero crossing detection circuit.
The PCF circuit is provided with a main path and a secondary path, and the main path and the secondary path are respectively provided with an inductor and a power tube. The loop interrupt timer is used to periodically generate an interrupt signal and input the interrupt signal to the processor. The first PWM signal generator is connected with a power tube in the main circuit and connected with a first counter, the first PWM signal generator is used for inputting a main PWM signal to the power tube, and the first counter is used for counting the main PWM signal. The processor is connected with the first counter, the second counter, the third counter, the first zero-crossing detection circuit and the second zero-crossing detection circuit.
The second PWM signal generator is connected with the power tube of the slave path and a second counter, the second PWM signal generator is used for inputting the slave PWM signal to the power tube, and the second counter is used for counting the slave PWM signal.
The third PWM signal generator is connected with the third counter, and is used for inputting the auxiliary PWM signal to the third counter, and the third counter is used for counting the auxiliary PWM signal.
The counter in this application may count in the following manner: the counter counts up by 1 every time the counter detects a rising edge of the PWM signal.
The first zero-crossing detection circuit is connected with the inductor in the main circuit and is used for detecting the current value of the main circuit, and when the current value is equal to zero, a first zero-crossing detection signal is output. The second zero-crossing detection circuit is connected with the inductor in the secondary circuit and is used for detecting the current value of the secondary circuit, and when the current value is equal to zero, a second zero-crossing detection signal is output to the processor. For example: the first zero-crossing detection signal and the second zero-crossing detection signal are high level signals.
In one or more possible embodiments, the period of the loop interrupt timer output interrupt signal may be configured by the processor according to actual requirements.
S302, when the first zero-crossing detection circuit is detected to output a first zero-crossing detection signal, resetting the first counter, acquiring the current count value of the third counter, and writing the current count value into a memory.
When the processor detects that the first zero-crossing detection circuit outputs a first zero-crossing detection signal, a reset instruction is sent to the first counter, the first counter resets the count value after receiving the reset instruction, and the count value after the first counter is reset is equal to 0. Meanwhile, the processor acquires the current count value of the third counter when detecting the first zero crossing detection signal, and stores the count value, for example: CAP for currently acquired count value n To indicate that the last acquired count value is CAP n-1 To represent.
S303, resetting the second counter when the second zero-crossing detection circuit outputs a second zero-crossing detection signal.
When the processor detects that the second zero-crossing detection circuit outputs a second zero-crossing detection signal, a reset instruction is sent to the second counter, the second counter receives the reset instruction to reset the count value, and the count value after the second counter is reset is equal to 0.
S304, when detecting that the interrupt generator outputs the nth interrupt signal, acquiring the current count value CNT1 of the first counter n And the current count value CNT2 of the second counter n And reading the latest count value CAP in the memory n And the last count value CAP n-1 According to CAP n And CAP n-1 Calculating the current period value CNTF of the first counter n And counting the thirdThe counter value of the counter is pulled up to a preset maximum counter value.
For example, referring to the timing diagram shown in fig. 3, shown in fig. 3 are the count waveform of the third counter, the count waveform of the first counter, and the count waveform of the second counter, respectively. The first counter is periodically reset based on the first zero-crossing detection signal, and the second counter is periodically reset based on the second zero-crossing detection signal. The loop interrupt timer periodically generates an interrupt signal, and the loop interrupt timer may be hardware or software, for example: the loop interrupt timer is an interrupt reset routine (Interrupt Service Routines). The processor detects the nth interrupt signal ISR n At this time, the current count value CNT1 of the first counter is acquired n And the current count value CNT2 of the second counter n And the processor instructs the auxiliary timer to pull the current count value up to a preset maximum count value, and then keeps the maximum count value until the processor detects the first zero crossing detection signal again, instructs the third counter to reset, and the count value of the third counter is equal to 0 after the resetting.
S305, calculate CNT2 n -CNT1 n Is Err_CNT n 。
S306, if Err_CNT n Greater than or equal to 0, according to [ (Err_CNT) n -CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Less than 0, according to [ (Err_CNT ] n +CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n 。
Wherein,% represents a modulo operator, kx is a constant, represents a preset adjustment coefficient, kx has a value range of 0 < Kx < 1, and specific numerical values can be determined according to actual requirements.
S307, the duty ratio of the first PWM signal generator is adjusted according to the calculated duty ratio adjustment quantity: pm1_SET n ＝Duty1 n -Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the And adjusting the duty ratio of the second PWM signal generator according to the duty ratio adjustment amount: pm2_SET n ＝Duty2 n +Adj_Phase n 。
Wherein, duty1 n Representing the current duty cycle of the first PWM signal generator, pm1_SET n Representing the duty cycle adjusted by the first PWM signal generator. Duty2 n Representing the current duty cycle of the second PWM signal generator, pm2_SET n Representing the duty cycle adjusted by the second PWM signal generator.
When the scheme of the embodiment of the application is executed, the third PWM signal generator, the third counter and the loop interrupt timer are introduced, the auxiliary PWM signal output by the third PWM signal generator and the count value of the third counter are used as references, the interrupt signal triggers the calculation and adjustment of the duty ratio adjustment quantity of the two paths of PWM signals, compared with the prior art that the first PWM signal generator and the second PWM signal generator are directly controlled to generate two paths of 180-degree PWM signals, the duty ratio of the two paths of PWM signals can be adjusted in real time, the effect of keeping the phase difference of the two paths of PWM signals at 180 is achieved, the power of the whole switching power supply can be increased, the loss of the switching power supply can be reduced under the continuous conduction mode, the performance index of the switching power supply is improved, the ripple voltage and the current distortion rate of the switching power supply are reduced, and the power density and the efficiency of the whole switching power supply are improved.
The following are device embodiments of the present application, which may be used to perform method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.
Fig. 5 is a schematic structural diagram of a device for implementing CRM control of a two-phase interleaved PFC circuit according to an exemplary embodiment of the present application, hereinafter referred to as device 5. The apparatus 5 may be implemented as all or part of an electronic device by software, hardware or a combination of both. The device 5 comprises: an instruction unit 501, a writing unit 502, a reset unit 503, an interrupt processing unit 504, a calculation unit 505, and an adjustment unit 506.
An indicating unit 501, configured to instruct, after power-up, the loop interrupt timer, the first counter, the second counter, the third counter, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the first zero-crossing detection circuit, and the second zero-crossing detection circuit to start operating;
a writing unit 502, configured to reset a count value of the first counter and obtain a current count value of the third counter when the first zero crossing signal generated by the first zero crossing detection circuit is detected, and write the current count value into the memory;
a reset unit 503, configured to reset a count value of the second counter when the second zero crossing signal generated by the second zero crossing detection circuit is detected;
an interrupt processing unit 504 for acquiring the current count value CNT1 of the first counter when detecting the nth interrupt signal generated by the loop interrupt timer n And the current count value CNT2 of the second counter n The method comprises the steps of carrying out a first treatment on the surface of the Reading the latest count value CAP in the memory n And the last count value CAP n-1 According to CAP n And CAP n-1 Calculating the current period value CNTF of the first counter n And pulling up the count value of the third counter to a preset maximum count value;
a calculating unit 505 for calculating CNT2 n -CNT1 n Is Err_CNT n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Greater than or equal to 0, according to [ (Err_CNT) n -CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Less than 0, according to [ (Err_CNT ] n +CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n ；
An adjusting unit 506, configured to adjust the duty ratio of the first PWM signal generator according to the calculated duty ratio adjustment amount: pm1_SET n ＝Duty1 n -Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the And adjusting the duty ratio of the second PWM signal generator according to the duty ratio adjustment amount: pm2_SET n ＝Duty2 n +Adj_Phase n 。
In one or more possible embodiments, further comprising:
the configuration unit configures a period value of the loop interrupt timer, a maximum count value of the third counter, an initial duty cycle of the first PWM signal generator, an initial duty cycle of the second PWM signal generator, an initial duty cycle of the third PWM signal generator, and a maximum count value of the third counter. The initial duty ratio represents the duty ratio of the PWM signal output by each signal generator after power-up, and parameter values of each device configuration may be determined according to actual requirements, which is not limited in this application.
Further, the duty ratio of the first PWM signal generator and the initial duty ratio of the second PWM signal generator are configured to be equal
It should be noted that, when the implementation method of CRM control of the two-phase interleaved PFC circuit is executed by the apparatus 5 provided in the foregoing embodiment, only the division of the foregoing functional modules is used as an example, in practical application, the foregoing functional allocation may be completed by different functional modules according to needs, that is, the internal structure of the apparatus is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the implementation device of the CRM control of the two-phase interleaved PFC circuit provided in the above embodiment belongs to the same concept as the implementation method embodiment of the CRM control of the two-phase interleaved PFC circuit, and the implementation process is shown in the method embodiment and will not be described herein.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
The embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are adapted to be loaded by a processor and execute the method steps of the embodiment shown in fig. 3, and the specific execution process may refer to the specific description of the embodiment shown in fig. 3, which is not repeated herein.
The present application also provides a computer program product storing at least one instruction that is loaded and executed by the processor to implement a method of implementing CRM control of a two-phase interleaved PFC circuit as described in the various embodiments above.
Referring to fig. 6, a schematic structural diagram of an electronic device is provided in an embodiment of the present application. As shown in fig. 5, the electronic device 600 may include: at least one processor 601, at least one communication interface 603, a memory 604, at least one communication bus 602.
Wherein the communication bus 602 is used to enable connected communications between these components.
The communication interface 603 is used to enable communication between external devices or apparatuses, and may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface).
The electronic device 600 further comprises a PFC circuit, a loop interrupt timer, a first PWM signal generator, a second PWM signal generator, a third PWM signal generator, a first counter, a second counter, a third counter, a first zero crossing detection circuit, and a second zero crossing detection circuit, the loop interrupt timer being coupled to the processor 601. The first PWM signal generator is connected to the main circuit of the PFC circuit, the first counter, and the processor 601, respectively. The second PWM signal generator is connected to the slave of the PFC circuit, the second counter and the processor 601, respectively. The third PWM signal generator is connected to the third counter and the processor 601, respectively. The first zero crossing detection circuit is connected to the processor 601 and the inductor in the main path, respectively, and the second zero crossing detection circuit is connected to the processor 601 and the inductor in the sub path, respectively.
Wherein the processor 601 may include one or more processing cores. The processor 601 utilizes various interfaces and lines to connect various portions of the overall electronic device 600, perform various functions of the electronic device 600, and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 604, and invoking data stored in the memory 604. Alternatively, the processor 601 may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field-Programmable gate array (FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 601 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 601 and may be implemented by a single chip.
The Memory 604 may include a random access Memory (RandomAccess Memory, RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 604 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 604 may be used to store instructions, programs, code, sets of codes, or instruction sets. The memory 604 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, etc.; the storage data area may store data or the like referred to in the above respective method embodiments. The memory 604 may also optionally be at least one storage device located remotely from the processor 601. As shown in fig. 6, an operating system, network communication modules, user interface modules, and application programs may be included in memory 604, which is one type of computer storage medium.
In the electronic device 600 shown in fig. 6, the user interface 603 is mainly used for providing an input interface for a user, and acquiring data input by the user; the processor 601 may be configured to invoke an application program stored in the memory 604 and specifically execute the method shown in fig. 3, and the specific process may be shown in fig. 3, which is not repeated herein.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, or the like.
The foregoing disclosure is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the claims herein, as the equivalent of the claims herein shall be construed to fall within the scope of the claims herein.
Claims (6)
1. The implementation method of the CRM control of the two-phase interleaved PFC circuit is characterized by comprising the following steps:
after power-on, the loop interrupt timer, the first counter, the second counter, the third counter, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the first zero-crossing detection circuit and the second zero-crossing detection circuit are instructed to start working;
resetting the count value of the first counter when the first zero crossing signal generated by the first zero crossing detection circuit is detected, acquiring the current count value of the third counter, and writing the current count value into a memory;
resetting the count value of the second counter when the second zero crossing signal generated by the second zero crossing detection circuit is detected;
when the nth interrupt signal generated by the loop interrupt timer is detected, the current count value CNT1 of the first counter is acquired n And the current count value CNT2 of the second counter n The method comprises the steps of carrying out a first treatment on the surface of the Reading the latest count value CAP in the memory n And the last count value CAP n-1 According to CAP n And CAP n-1 Calculating the current period value CNTF of the first counter n And pulling up the count value of the third counter to a preset maximum count value;
calculation of CNT2 n -CNT1 n Is Err_CNT n ；
If Err_CNT n Greater than or equal to 0, according to [ (Err_CNT) n -CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Less than 0, according to [ (Err_CNT ] n +CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n ；
Adjusting according to the calculated duty cycleThe amount adjusts the duty cycle of the first PWM signal generator: pm1_SET n ＝Duty1 n -Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the And adjusting the duty ratio of the second PWM signal generator according to the duty ratio adjustment amount: pm2_SET n ＝Duty2 n +Adj_Phase n 。
2. The method as recited in claim 1, further comprising:
configuring a period value of the loop interrupt timer, a maximum count value of the third counter, an initial duty cycle of the first PWM signal generator, an initial duty cycle of the second PWM signal generator, and a maximum count value of the third counter.
3. The method of claim 2, wherein the duty cycle of the first PWM signal generator and the initial duty cycle of the second PWM signal generator are configured to be equal.
4. An implementation device for CRM control of a two-phase interleaved PFC circuit, the device comprising:
the indication unit is used for indicating the loop interrupt timer, the first counter, the second counter, the third counter, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the first zero-crossing detection circuit and the second zero-crossing detection circuit to start working after power is applied;
the writing unit is used for resetting the count value of the first counter when the first zero crossing signal generated by the first zero crossing detection circuit is detected, acquiring the current count value of the third counter and writing the current count value into the memory;
a reset unit, configured to reset a count value of the second counter when the second zero-crossing signal generated by the second zero-crossing detection circuit is detected;
an interrupt processing unit for acquiring the current count value CNT1 of the first counter when detecting the nth interrupt signal generated by the loop interrupt timer n And the current count value CNT2 of the second counter n The method comprises the steps of carrying out a first treatment on the surface of the Reading the latest count value CAP in the memory n And the last count value CAP n-1 According to CAP n And CAP n-1 Calculating the current period value CNTF of the first counter n And pulling up the count value of the third counter to a preset maximum count value;
a calculation unit for calculating CNT2 n -CNT1 n Is Err_CNT n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Greater than or equal to 0, according to [ (Err_CNT) n -CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the If Err_CNT n Less than 0, according to [ (Err_CNT ] n +CNTF n /2)％CNTF n /2]* Kx calculates the current duty cycle adjustment Adj_Phase n ；
The adjusting unit is used for adjusting the duty ratio of the first PWM signal generator according to the calculated duty ratio adjusting quantity: pm1_SET n ＝Duty1 n -Adj_Phase n The method comprises the steps of carrying out a first treatment on the surface of the And adjusting the duty ratio of the second PWM signal generator according to the duty ratio adjustment amount: pm2_SET n ＝Duty2 n +Adj_Phase n 。
5. A computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the method steps of any one of claims 1 to 3.
6. An electronic device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1-3.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211535214X | 2022-11-30 | ||
| CN202211535214.XA CN115765428A (en) | 2022-11-30 | 2022-11-30 | Method and device for realizing CRM (customer relationship management) control of two-phase interleaved PFC (Power factor correction) circuit, storage medium and electronic equipment |
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| Publication Number | Publication Date |
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| CN117559789A true CN117559789A (en) | 2024-02-13 |
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|---|---|---|---|
| CN202211535214.XA Withdrawn CN115765428A (en) | 2022-11-30 | 2022-11-30 | Method and device for realizing CRM (customer relationship management) control of two-phase interleaved PFC (Power factor correction) circuit, storage medium and electronic equipment |
| CN202311482835.0A Pending CN117559789A (en) | 2022-11-30 | 2023-11-09 | Implementation method and device for CRM control of two-phase interleaved PFC circuit, storage medium and electronic equipment |
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| CN202211535214.XA Withdrawn CN115765428A (en) | 2022-11-30 | 2022-11-30 | Method and device for realizing CRM (customer relationship management) control of two-phase interleaved PFC (Power factor correction) circuit, storage medium and electronic equipment |
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|---|---|
| CN (2) | CN115765428A (en) |
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2022
- 2022-11-30 CN CN202211535214.XA patent/CN115765428A/en not_active Withdrawn
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| CN115765428A (en) | 2023-03-07 |
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