CN117542928A - Micron-sized patterned substrate and preparation method and application thereof - Google Patents
Micron-sized patterned substrate and preparation method and application thereof Download PDFInfo
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- CN117542928A CN117542928A CN202311346375.9A CN202311346375A CN117542928A CN 117542928 A CN117542928 A CN 117542928A CN 202311346375 A CN202311346375 A CN 202311346375A CN 117542928 A CN117542928 A CN 117542928A
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- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 69
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 39
- 230000008569 process Effects 0.000 claims abstract description 24
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 230000001737 promoting effect Effects 0.000 claims abstract description 8
- 229910052594 sapphire Inorganic materials 0.000 claims description 27
- 239000010980 sapphire Substances 0.000 claims description 27
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 16
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000010992 reflux Methods 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 claims description 5
- 229910052753 mercury Inorganic materials 0.000 claims description 5
- 229910000077 silane Inorganic materials 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000008859 change Effects 0.000 abstract description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 239000002904 solvent Substances 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 4
- 239000002318 adhesion promoter Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002957 persistent organic pollutant Substances 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000265 homogenisation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
Abstract
The invention relates to a preparation method of a micron-sized patterned substrate, which is prepared by the following steps: s1, coating a tackifier on a cleaned substrate, and then performing first baking to form a tackifier layer; s2, coating negative photoresist on the adhesion promoting layer, and then performing second baking to form a photoresist layer; s3, exposing and developing the substrate coated with the adhesion promoting layer and the photoresist layer; s4, heating the developed substrate and carrying out thermal reflow to obtain a pattern array; and S5, finally carrying out ICP inductively coupled plasma etching on the substrate after thermal reflow. The method reduces the etching depth of micron-sized patterns, shortens the process time, improves the yield, and realizes the change of micron-sized patterns and uniform array.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a micron-sized patterned substrate and a preparation method and application thereof.
Background
Patterning the sapphire substrate (Patterned Sapphire Substrate, PSS), i.e. growing a dry etching mask on the sapphire substrate, patterning the mask by standard photolithographic techniques, etching the sapphire by ICP etching techniques, removing the mask, and growing a GaN material thereon, whereby the longitudinal epitaxy of the GaN material is changed to lateral epitaxy. On one hand, dislocation density of GaN epitaxial materials can be effectively reduced, so that non-radiative recombination of an active region is reduced, reverse leakage current is reduced, and service life of an LED is prolonged; on the other hand, light emitted by the active region is scattered for multiple times through the interface of the GaN and the sapphire substrate, so that the emergence angle of total reflection light is changed, the emergence probability of light of the flip LED from the sapphire substrate is increased, and the light extraction efficiency is improved. By combining the two reasons, the emergent light brightness of the LED grown on the PSS is greatly improved compared with that of the traditional LED, meanwhile, the reverse leakage current is reduced, and the service life of the LED is prolonged.
With the development of process technology in the LED field and the rapid growth of the whole LED industry, the research on the GaN-based LED device PSS substrate is also gradually increased. PSS technology is adopted by various manufacturers at present so as to improve the light extraction efficiency of the LED device. The pattern types of PSS are also more, and a pattern similar to a cone is used in a more common shape, the pattern period is about 3 mu m, and the height is about 1.5 mu m.
However, the etching section related to the traditional sapphire patterning has long time and limited productivity of a single device, besides the improvement of productivity of a machine, no liftable space exists in the process, and the depth of the standard conical pattern is required to be finished in a single furnace for 43-45 minutes.
Disclosure of Invention
The invention aims to provide a micron-sized patterned substrate, a preparation method and application thereof, wherein the method reduces the etching depth of micron-sized patterning, shortens the process time, improves the yield and realizes the change of micron-sized patterns and uniform array.
In order to achieve the above object, a first aspect of the present invention provides a method for preparing a micron-sized patterned substrate, which is prepared by a method comprising the steps of:
s1, coating a tackifier on a cleaned substrate, and then performing first baking to form a tackifier layer;
s2, coating negative photoresist on the adhesion promoting layer, and then performing second baking to form a photoresist layer;
s3, exposing and developing the substrate coated with the adhesion promoting layer and the photoresist layer;
s4, heating the developed substrate to perform thermal reflux to obtain a pattern array;
and S5, finally carrying out ICP inductively coupled plasma etching on the substrate after thermal reflow.
Optionally, in S1, cleaning the substrate with an SPM solution; the SPM solution is prepared from sulfuric acid and hydrogen peroxide in a mass ratio of 5:1, mixing; preferably, the sulfuric acid concentration is 98%, and the hydrogen peroxide concentration is 30%.
Optionally, in S1, the adhesion promoter is silane, and the thickness of the adhesion promoter is 1-2nm; the temperature of the first baking is 105-110 ℃ and the time is 65-70s.
Optionally, in S2, the negative photoresist has a thickness of 4.6-5.0 μm; the temperature of the second baking is 95-105 ℃ and the time is 40-45s.
Optionally, in S3, the exposure condition is: the light source of the mercury lamp has the light intensity of 400+/-20 cd, the CD line width is less than or equal to 650nm, the wavelength is 436nm or 365nm, and the single-field exposure time is 880-900ms; and/or positive photoresist developer is adopted for development, and the development time is 220-250s.
Optionally, in S4, the thermal reflux temperature is 169-171 ℃ for 610-620S.
Optionally, in S5, the etching process parameters are: main etching gas BCl 3 The flow is 90-95sccm, the upper radio frequency power is 2000-2200W, and the lower radio frequency power is 2000-2200WThe power is 500-600W, the vacuum pressure is less than 2.8 x 10 -5 Torr; and/or the etching time is 21-22min; and/or the etching depth is 0.9 mu m + -50 nm.
Optionally, the substrate is sapphire, quartz glass or silicon wafer.
Optionally, the etching pattern includes square, round, conical, regular hexagonal and hemispherical.
Optionally, the patterned array includes a microlens patterned array and a grating micro-scale patterned array.
In a second aspect, the present invention provides a micron-sized patterned substrate prepared by the method provided in the first aspect.
A third aspect of the present invention provides the use of the micron-sized patterned substrate provided in the second aspect of the present invention in the manufacture of a semiconductor device.
Through the technical scheme, compared with the prior art, the invention has the following beneficial effects:
1. the invention reduces the etching depth of the standard micron-sized patterning, so that the etching process is easier to control, the process duration is greatly shortened, and the etching time is shortened by more than 45%.
2. Because the etching process is simplified, the equipment cost, the special gas cost and the labor cost are saved, and the yield is improved by more than 20%.
3. The thermal reflow technology provided by the invention can realize micron-sized pattern change and uniform array.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
FIG. 1 is a schematic of the micron-sized patterned sapphire of example 1;
FIG. 2 is a schematic view of the depth of a conventional etched segment in comparative example 1;
FIG. 3 is a schematic diagram of the metallographic microscope dimensions and top view of the lithographic pattern of example 1;
FIG. 4 is a hemispherical pattern after thermal reflow in example 1;
FIG. 5 is a top view of a microscope of the micron-sized patterned sapphire of example 1;
FIG. 6 is a macro-array diagram of micron-sized patterned sapphire in example 1;
FIG. 7 is a graph showing the comparison of the conventional etching in comparative example 1 with the etching region in example 1;
FIG. 8 is a three-dimensional array of comparative example 1 in comparison to example 1 etched areas;
FIG. 9 is a graphical representation of the pattern change after thermal reflow in example 3;
FIG. 10 is a graphical representation of the pattern change after thermal reflow in example 1;
FIG. 11 is a graph showing the pattern change after thermal reflow in example 4.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
The invention provides a preparation method of a micron-sized patterned substrate, which is prepared by the following steps:
s1, coating a tackifier on a cleaned substrate, and then performing first baking to form a tackifier layer;
s2, coating negative photoresist on the adhesion promoting layer, and then performing second baking to form a photoresist layer;
s3, exposing and developing the substrate coated with the adhesion promoting layer and the photoresist layer;
s4, heating the developed substrate to perform thermal reflux to obtain a pattern array;
and S5, finally carrying out ICP inductively coupled plasma etching on the substrate after thermal reflow.
According to the invention, the substrate is heated before etching, so that the microstructure pattern on the substrate can be spontaneously changed into a hemispherical-like structure from a cylindrical structure due to the action of surface tension, the curvature radius of the microstructure is gradually reduced, a pattern homogenization array is formed, when the microstructure pattern is changed into a hemispherical-like shape, the pattern can go deep into a patterning gap to start operation during etching, and further, the etching time is shortened by more than 45% only by 21-22min when the etching section is used for etching, the equipment cost, the special gas cost and the labor cost are saved, and the yield is improved.
According to the present invention, in S1, the substrate is cleaned with an SPM solution; the SPM solution is prepared from sulfuric acid and hydrogen peroxide in a mass ratio of 5:1, mixing; preferably, the sulfuric acid concentration is 98%, and the hydrogen peroxide concentration is 30%. In the invention, the SPM solution is used for cleaning the substrate, so that organic matters and particulate matters on the surface of the substrate can be completely removed.
According to the invention, in S1, the tackifier is silane, and the thickness of the tackifier is 1-2nm; the temperature of the first baking is 105-110 ℃ and the time is 65-70s. In the invention, the adhesion promoter can enhance the binding force between the surface of the substrate and the photoresist, so that the photoresist can be more uniformly present on the surface of the substrate, thereby ensuring more stable implementation of the subsequent process.
According to the present invention, in S2, the negative photoresist has a thickness of 4.6 to 5.0 μm; the temperature of the second baking is 95-105 ℃ and the time is 40-45s. In the invention, the negative photoresist is adopted, and is opposite to the region formed after the positive photoresist is developed, the region formed by the negative photoresist is less than the region formed by the positive photoresist, as shown in fig. 7 and 8, and the subsequent etching can also save the etching process; and the negative photoresist has good adhesion capability, high photosensitive speed and low cost. The solvent in the photoresist can be evaporated by baking the photoresist layer for curing, and the uniformity of the photoresist layer can be ensured at a specific temperature and time within +/-2% of a standard uniformity value.
According to the present invention, in S3, the exposure conditions are: the light source of the mercury lamp has the light intensity of 400+/-20 cd, the CD line width of less than or equal to 650nm, the wavelength of 436nm or 365nm and the single-field exposure time of 880-900ms. In the invention, the stepper is adopted for exposure, and specific parameters of the stepper can realize the standard size of the transferred pattern, so that the subsequent process can be smoothly carried out as required.
According to the invention, in S3, the positive photoresist developer is used for development, and the development time is 220-250S. In the invention, the specified parameters of development can avoid defects such as pattern missing, pattern distortion and the like.
According to the invention, in S4, the thermal reflux temperature is 169-171 ℃ and the time is 610-620S. In the invention, the micro pattern morphology can be converted into a hemispherical structure from a cylindrical shape in a proper thermal reflux temperature and time, and then in a subsequent etching procedure, the etching depth can be reduced for etching, and the etching time is saved.
According to the present invention, in S5, the etching process parameters are: main etching gas BCl 3 The flow is 90-95sccm, the upper radio frequency power is 2000-2200W, the lower radio frequency power is 500-600W, and the vacuum pressure is less than 2.8 x 10 -5 Torr; and/or the etching time is 21-22min; and/or the etching depth is 0.9 mu m + -50 nm. In the invention, the standardized pattern can be realized through the set etching process parameters, and the dimension of the standardized pattern is as follows: the bottom width is 2.65-2.75 μm, the height is 1.45-1.65 μm, and the triangle radian is less than 150nm.
According to the invention, the substrate is sapphire, quartz glass or silicon wafer.
According to the invention, the etching pattern comprises square, round, conical, regular hexagon and hemispherical.
According to the invention, the pattern array comprises a microlens pattern array and a grating micron-sized pattern array.
In a second aspect, the present invention provides a micron-sized patterned substrate prepared by the method provided in the first aspect.
A third aspect of the present invention provides the use of the micron-sized patterned substrate provided in the second aspect of the present invention in the manufacture of a semiconductor device.
The invention is illustrated in further detail by the following examples. The starting materials used in the examples are all available commercially.
Example 1
A micron-sized sapphire patterned substrate is prepared by the following method:
s1, preparing a 4-inch sapphire substrate slice, and using an SPM cleaning scheme (sulfuric acid H 2 SO 4 : hydrogen peroxide solution H 2 O 2 =5:1) cleaning organic pollutants on the sapphire substrate sheet for 30min, and then spin-drying under the following conditions: the rotating speed is 800r/min, and the time is 11min.
S2, spin-coating silane with the thickness of 2nm on a sapphire substrate by using a spin coater, wherein the rotation speed of a vacuum chuck of the spin coater is 1800r/min; and then baking and curing for 70s at 110 ℃ to strengthen the bonding force between the surface of the substrate slice and the photoresist.
S3, continuously using a full-automatic photoresist homogenizing machine to carry out CP soft baking at 60 ℃ for 1min on the sapphire substrate slice, dehydrating and removing moisture on the surface of the sapphire substrate slice, then carrying out spin-coating photoresist (adopting negative photoresist AZ4620 and vacuum chuck rotating speed 2200r/min to obtain uniform thickness of 4.8+/-0.02 mu m), carrying out HP solid baking at 100 ℃ for 45S, evaporating a solvent in the photoresist, wherein the solvent can enable the coated photoresist to be thinner, absorb heat and influence adhesiveness of the photoresist.
S4, exposing the uniformly-glued sapphire substrate by using a Nikon steppers stepper, wherein the exposure conditions are as follows: the light source of the mercury lamp has the light intensity of 400+/-20 CD, the line width of the CD of 650nm, the wavelength of 436nm and the single-field exposure time of 900ms.
S5, developing the exposed substrate for 240S by using RMZX-238 positive photoresist developing solution. The graphic structure of FIG. 3 (metallographic microscope: top view)
S6, heating the heating table (the heating temperature is controlled to be 2-3 ℃/min and the time is controlled to be 60min to reach the designated temperature of 170 ℃), and then placing the substrate on the surface of the heating table in a flat way for thermal reflow (the time is 620S) to obtain the morphology of the uniform array in the figures 4, 5 and 6, and the morphology of the uniform array in the figure 10 (the figure 4 is the unit morphology, the figure 5 is the array graph, the figure 6 is the macro array graph, and the figure 10 is the microscopic electron microscope graph of the array graph).
S7, substrate basePerforming ICP inductively coupled plasma etching, wherein the etching process parameters are as follows: main etching gas BCl 3 Flow 95sccm, upper RF power 2200W, lower RF power 500W, vacuum pressure < 2.8x10 -5 After etching for 22min, a standard pattern with an etching depth of 0.9 μm.+ -. 50nm was obtained as shown in FIG. 1.
In the present embodiment, the main etching gas BCl 3 The conventional etching process needs 43-45min, and the etching process needs 22min, so that the time is shortened by about half, and the specific gas flow is reduced by about 50%; the etching time is shortened by about 21min, the thermal reflow time is shortened by about 10min, other process time is unchanged, the comprehensive time (ICP etching of one furnace for 7 sheets, and thermal reflow can be carried out on a plurality of sheets at one time) is reduced by 11min, and more products can be produced in the same time.
Example 2
A micron-sized sapphire patterned substrate is prepared by the following method:
s1, preparing a 4-inch sapphire substrate slice, and using an SPM cleaning scheme (sulfuric acid H 2 SO 4 : hydrogen peroxide solution H 2 O 2 =5: 1) Cleaning organic pollutants on the sapphire substrate slice for 30min, and then spin-drying under the following conditions: the rotating speed is 800r/min, and the time is 11min.
S2, spin-coating silane with the thickness of 1nm on a sapphire substrate by using a spin coater, wherein the rotation speed of a vacuum chuck of the spin coater is 1800r/min; and then baking and curing for 65s at the temperature of 105 ℃ to strengthen the bonding force between the surface of the substrate slice and the photoresist.
S3, continuously using a full-automatic photoresist homogenizing machine to carry out CP soft baking at 60 ℃ for 1min on the sapphire substrate slice, dehydrating and removing moisture on the surface of the sapphire substrate slice, then carrying out spin-coating photoresist (adopting negative photoresist AZ4620 and vacuum chuck rotating speed 2200r/min to obtain uniform thickness of 4.8+/-0.02 mu m), then carrying out HP solid baking at 95 ℃ for 40S, evaporating a solvent in the photoresist, wherein the solvent can enable the coated photoresist to be thinner, absorb heat and influence the adhesiveness of the photoresist.
S4, exposing the uniformly-glued sapphire substrate by using a Nikon steppers stepper, wherein the exposure conditions are as follows: the light source of the mercury lamp has the light intensity of 400+/-20 CD, the CD line width of 650nm, the wavelength of 365nm and the single-field exposure time of 880ms.
S5, developing the exposed substrate for 220S by using RMZX-238 positive photoresist developing solution.
And S6, heating the heating table (the heating temperature is controlled to be 2-3 ℃/min and the time is controlled to be 60min to reach the designated temperature of 170 ℃), and then placing the substrate on the surface of the heating table smoothly for thermal reflow (the time is 610S) to obtain a topography map of the uniform array.
S7, performing ICP inductively coupled plasma etching on the substrate, wherein the etching process parameters are as follows: main etching gas BCl 3 Flow 90sccm, upper RF power 2000W, lower RF power 600W, vacuum pressure < 2.8x10 -5 And (3) Torr, wherein the etching depth is 1 mu m plus or minus 50nm, and etching for 21min to obtain a standard pattern.
Example 3
Example 3 differs from example 1 in that in S5 the thermal reflow temperature is 175 ℃ and the time is 600S. In this example, adjacent patterns were melted and the reflow was excessive, as shown in fig. 9.
Example 4
Example 4 differs from example 1 in that in S5 the thermal reflow temperature is 130 ℃ and the time is 600S. After thermal reflow, the pattern change profile on the wafer is as shown in fig. 11, and the thermal reflow temperature is insufficient to form the desired profile.
Comparative example 1
Comparative example 1 uses a conventional etching process, differing from example 1 in that no thermal reflow is performed and the etching is performed in a standard pattern. Comparative example 1 the pattern before etching was cylindrical in shape and was in the main etching gas BCl 3 Flow 105sccm, power 2500W, RF W, vacuum pressure < 2.8x10 -5 Etching was completed for 44 minutes under Torr, and the etching process is shown in FIG. 2.
In summary, it can be seen from example 1 and comparative example 1 that the thermal reflow process performed before etching can not only uniformly array, but also change the micro pattern morphology from cylindrical to hemispherical structure, and further reduce the etching depth to etch in the subsequent etching process, the etching time is reduced from 44 minutes to 22 minutes, the etching time is reduced to 50% of the original time, and the preparation time of the substrate is reduced by 11 minutes in addition to 10 minutes of thermal reflow. Further, due to the shortened etching time, the special gas is saved by 50%, more products can be produced in the same time, and the production cost is reduced.
As can be seen from examples 1, 3 and 4, the thermal reflow temperature is different, the micro pattern is changed differently at the same time, and when the temperature is too high, the reflow is excessive, and when the temperature is too low, the micro pattern cannot obtain a desired shape, and thus the etching process cannot be smoothly performed.
The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the scope of the technical concept of the present invention, and all the simple modifications belong to the protection scope of the present invention.
In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. The various possible combinations of the invention are not described in detail in order to avoid unnecessary repetition.
Moreover, any combination of the various embodiments of the invention can be made without departing from the spirit of the invention, which should also be considered as disclosed herein.
Claims (10)
1. The preparation method of the micron-sized patterned substrate is characterized by comprising the following steps:
s1, coating a tackifier on a cleaned substrate, and then performing first baking to form a tackifier layer;
s2, coating negative photoresist on the adhesion promoting layer, and then performing second baking to form a photoresist layer;
s3, exposing and developing the substrate coated with the adhesion promoting layer and the photoresist layer;
s4, heating the developed substrate to perform thermal reflux to obtain a pattern array;
and S5, finally carrying out ICP inductively coupled plasma etching on the substrate after thermal reflow.
2. The manufacturing method according to claim 1, wherein in S1, the substrate is cleaned with an SPM solution; the SPM solution is prepared from sulfuric acid and hydrogen peroxide in a mass ratio of 5:1, mixing; preferably, the sulfuric acid concentration is 98%, and the hydrogen peroxide concentration is 30%.
3. The production method according to claim 1, wherein in S1, the tackifier is silane, and the tackifier has a thickness of 1 to 2nm; the temperature of the first baking is 105-110 ℃ and the time is 65-70s; and/or the number of the groups of groups,
in S2, the thickness of the negative photoresist is 4.6-5.0 mu m; the temperature of the second baking is 95-105 ℃ and the time is 40-45s.
4. The production method according to claim 1, wherein in S3, the exposure condition is: the light source of the mercury lamp has the light intensity of 400+/-20 cd, the CD line width is less than or equal to 650nm, the wavelength is 436nm or 365nm, and the single-field exposure time is 880-900ms; and/or positive photoresist developer is adopted for development, and the development time is 220-250s.
5. The preparation method according to claim 1, wherein the thermal reflow temperature is 169-171 ℃ for 610-620S in S4.
6. The method of claim 1, wherein in S5, the etching process parameters are: main etching gas BCl 3 The flow is 90-95sccm, the upper radio frequency power is 2000-2200W, the lower radio frequency power is 500-600W, and the vacuum pressure is less than 2.8 x 10 - 5 Torr; and/or the etching time is 21-22min; and/or the etching depth is 0.9 mu m + -50 nm.
7. The method of any one of claims 1-6, wherein the substrate base is sapphire, quartz glass or silicon wafer.
8. The method of any one of claims 1-6, wherein the etched pattern comprises square, circular, conical, regular hexagonal, and hemispherical;
the pattern array comprises a micro lens pattern array and a grating micron-sized pattern array.
9. A micron-sized patterned substrate prepared by the method of any one of claims 1-8.
10. Use of the micron-sized patterned substrate of claim 9 in the manufacture of a semiconductor device.
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| CN202311346375.9A CN117542928A (en) | 2023-10-17 | 2023-10-17 | Micron-sized patterned substrate and preparation method and application thereof |
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