CN117542894A - VDMOS termination structure and semiconductor device - Google Patents
VDMOS termination structure and semiconductor device Download PDFInfo
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- CN117542894A CN117542894A CN202311602052.1A CN202311602052A CN117542894A CN 117542894 A CN117542894 A CN 117542894A CN 202311602052 A CN202311602052 A CN 202311602052A CN 117542894 A CN117542894 A CN 117542894A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
Abstract
The application provides a VDMOS terminal structure and a semiconductor device, the VDMOS terminal structure comprises: a substrate; a first epitaxial layer on the surface of the substrate; the second epitaxial layer is positioned on the surface, far away from the substrate, of the first epitaxial layer, and the doping types of the first epitaxial layer and the second epitaxial layer are different; and the first grooves are arranged at intervals along the preset direction, are positioned in the second epitaxial layer and the first epitaxial layer, and gradually reduce in depth in the preset direction, wherein the preset direction is a direction perpendicular to the thickness of the substrate, and the depth is the length of the first grooves in the thickness direction of the substrate. The problem that the withstand voltage capability of VDMOS terminal structure is lower in prior art has been solved to this application.
Description
Technical Field
The present application relates to the technical field of semiconductor power devices, and in particular, to a VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor) termination structure and a semiconductor device.
Background
SiC MOSFETs (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOS, metal oxide semiconductor field effect transistors) are widely used in the wind gap industry for new energy automobiles, traffic tracks, photovoltaics, etc. with the advantages of high voltage and high temperature resistance, high frequency, low power loss, high switching speed, etc. SiC MOSFETs can be classified into planar MOSFETs (e.g., double-Diffused MOSFETs, abbreviated as DMOSFETs) and trench types MOSFET (Trench MOSFET) according to their gate structures. Compared with DMOSFET, the SiC Trench MOSFET has the advantages of smaller on-resistance, higher power density and the like.
The most important performance of the power device is to block high voltage, the device can bear high voltage on a PN junction, metal-semiconductor contact and depletion layer of an MOS interface through design, and the electric field strength of the depletion layer can be increased along with the increase of the applied voltage, so that avalanche breakdown finally occurs beyond the limit of the material. The curvature of the electric field in the depletion region at the edge of the device is increased, so that the electric field intensity is larger than that in the die, avalanche breakdown occurs at the edge of the die earlier than in the die in the voltage rising process, and in order to maximize the performance of the device, a voltage dividing structure is required to be designed at the edge of the device, so that the curvature of PN junctions at the edge of the active region (cell region) is reduced, the depletion layer is transversely extended, the voltage withstand capability in the horizontal direction is enhanced, and the breakdown occurs at the edge and the inside of the device simultaneously. The cutoff ring is distributed at the outermost periphery of the chip between the voltage dividing structure and the scribing groove area, and is indispensable in high reliability requirements and devices packaged by the module.
Junction termination extension technology is one of the most commonly used voltage dividing structures in current power devices. The process is very simple, and can be formed together with the active region in a diffusion way without adding process steps. The junction termination extension technique is to make a circle of lightly doped P-type region around the main junction. When the main junction is reverse biased, the junction termination extension region is depleted at the same time. This corresponds to the introduction of negative charges inside the depletion region of the drift region, which expand the depletion region and can itself absorb a part of the electric field, thereby reducing the electric field spikes at the edges of the main junction. Thereby improving the breakdown resistance of the device.
The interface charge of the oxide layer on the surface of the conventional junction terminal extension structure can greatly influence the surface potential of the device, affect the voltage division effect and reduce the breakdown voltage; the depth of the P-type implant region is greatly affected by the process, and thermal processes in the process can severely affect the device's voltage withstand capability.
Disclosure of Invention
The primary purpose of the present application is to provide a VDMOS terminal structure and a semiconductor device, so as to at least solve the problem of low voltage withstand capability of the VDMOS terminal structure in the prior art.
To achieve the above object, according to one aspect of the present application, there is provided a VDMOS terminal structure including: a substrate; a first epitaxial layer on a surface of the substrate; a second epitaxial layer on a surface of the first epitaxial layer remote from the substrate, the first epitaxial layer being of a different doping type than the second epitaxial layer; and the first trenches are arranged at intervals along a preset direction, are positioned in the second epitaxial layer and the first epitaxial layer, and gradually reduce in depth in the preset direction, wherein the preset direction is a direction perpendicular to the thickness of the substrate, and the depth is the length of the first trenches in the thickness direction of the substrate.
Optionally, the VDMOS terminal structure further includes: the first implantation regions are located in the second epitaxial layer at intervals along the preset direction, each first implantation region is located on the same side of all the first trenches, the surfaces of the first implantation regions, which are far away from the substrate, and the surfaces of the second epitaxial layer, which are far away from the substrate, are the same, the doping types of the first implantation regions are the same as those of the second epitaxial layer, and the doping concentration of the first implantation regions is larger than that of the second epitaxial layer.
Optionally, the doping concentrations of the plurality of first implantation regions gradually decrease in the predetermined direction.
Optionally, the width of the plurality of first injection regions in the predetermined direction is gradually reduced, the width being the distance between two opposite edges of the first injection regions in the predetermined direction.
Optionally, the VDMOS terminal structure further includes: the second implantation regions are arranged in the first epitaxial layer at intervals along the preset direction, the first trenches are correspondingly arranged in the second implantation regions one by one, the surfaces of the second implantation regions, which are far away from the substrate, and the partial surfaces of the second epitaxial layer, which are close to the substrate, are the same, the doping types of the second implantation regions are the same as the doping types of the first implantation regions, and the doping concentration of the second implantation regions is larger than that of the first implantation regions.
Optionally, the VDMOS terminal structure further includes: the second groove is positioned in the second epitaxial layer, the second groove comprises a plurality of bottom surfaces which are sequentially connected, and the distances between the bottom surfaces and the surface, far away from the substrate, of the second epitaxial layer are gradually increased or gradually decreased along the preset direction.
Optionally, the VDMOS terminal structure further includes: the third injection region is positioned in the first epitaxial layer and is positioned at one side of the plurality of first injection regions, which is far away from the plurality of second injection regions, the surface of the third injection region, which is far away from the substrate, is the same surface as the partial surface of the first epitaxial layer, which is far away from the substrate, and the doping type of the third injection region is the same as that of the first epitaxial layer; the third groove is positioned in the second epitaxial layer, and part of the bottom surface of the third groove and the surface of the third injection region, which is far away from the substrate, are the same surface; the fourth injection region is positioned in the first epitaxial layer and between the first injection region and the third injection region, the surface of the fourth injection region, which is far away from the substrate, is the same as the partial surface of the first epitaxial layer, which is far away from the substrate, the doping type of the fourth injection region is the same as the doping type of a plurality of first injection regions, the doping concentration of the fourth injection region is smaller than the doping concentration of a plurality of first injection regions, and the doping concentration of the fourth injection region is larger than the doping concentration of the second epitaxial layer.
Optionally, the VDMOS terminal structure further includes: and the dielectric layer is covered on the second epitaxial layer and in the plurality of first grooves.
Optionally, the bottom surface of the first trench with the smallest depth in the plurality of first trenches and a part of the surface of the first epitaxial layer, which is far away from the substrate, are the same surface.
According to another aspect of the present application, there is provided a semiconductor device including: any of the VDMOS termination structures described.
By means of the technical scheme, the VDMOS terminal structure comprises a substrate, a first epitaxial layer, a second epitaxial layer and a plurality of first grooves which are sequentially stacked, wherein the first epitaxial layer and the second epitaxial layer are arranged in the first epitaxial layer, the first grooves are arranged at intervals along a preset direction, the doping types of the first epitaxial layer and the second epitaxial layer are different, the first grooves are arranged in the second epitaxial layer and the first epitaxial layer, and the depth of the first grooves in the preset direction is gradually reduced. Compared with the problem of lower voltage withstand capability of a device caused by directly injecting P-type ions into a first epitaxial layer to form a P-type injection region with changed depth in the VDMOS terminal structure in the prior art, the VDMOS terminal structure of the invention has the advantages that a second epitaxial layer with different doping types from the first epitaxial layer is added, the channel electron mobility of the VDMOS is improved, and the switching performance of the VDMOS terminal structure is improved; compared with the VDMOS terminal structure with the same depth of the grooves, in the VDMOS terminal structure, the depth of the first grooves is gradually reduced in the preset direction, so that under the action of voltage, the electric field line distribution at the bottoms of the grooves with different depths is changed, the electric field line density is reduced, the concentration degree of the electric field distribution generated at the bottoms of the grooves with different depths is improved, after the concentration degree of the electric field is improved, the breakdown voltage is increased, the voltage withstand level of the VDMOS terminal structure is also increased, and the voltage withstand performance of the VDMOS terminal structure is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 shows a schematic structural diagram of a VDMOS terminal structure provided in an embodiment according to the present application;
fig. 2 shows a schematic structural diagram of a specific VDMOS terminal structure provided according to an embodiment of the present application;
fig. 3 shows a schematic structural diagram of another specific VDMOS terminal structure provided according to an embodiment of the present application;
fig. 4 shows a schematic structural diagram of yet another specific VDMOS terminal structure provided according to an embodiment of the present application;
fig. 5 shows a schematic structural diagram of still another specific VDMOS terminal structure provided according to an embodiment of the present application;
fig. 6 is a schematic flow chart of a method for manufacturing a VDMOS terminal structure according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a substrate; 20. a first epitaxial layer; 30. a second epitaxial layer; 40. a first trench; 50. a first implant region; 60. a second implant region; 70. a second trench; 71. a third implant region; 72. a third trench; 73. a fourth implant region; 80. a dielectric layer.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the voltage withstand capability of the VDMOS terminal structure in the prior art is low, and in order to solve the above problem, embodiments of the present application provide a VDMOS terminal structure and a semiconductor device.
In an exemplary embodiment of the present application, there is provided a VDMOS terminal structure, as shown in fig. 1, including: a substrate 10; a first epitaxial layer 20 on the surface of the substrate 10; a second epitaxial layer 30 on a surface of the first epitaxial layer 20 remote from the substrate 10, the first epitaxial layer 20 and the second epitaxial layer 30 being different in doping type; and a plurality of first trenches 40 spaced apart from each other in a predetermined direction, wherein each of the first trenches 40 is located in the second epitaxial layer 30 and the first epitaxial layer 20, and a depth of the plurality of first trenches 40 in the predetermined direction is gradually reduced, the predetermined direction being a direction perpendicular to a thickness of the substrate 10, and the depth being a length of the first trench 40 in the thickness direction of the substrate 10.
Any suitable material may be selected by those skilled in the art to form the above-described substrate, first epitaxial layer, and second epitaxial layer. In the embodiment of the present application, the material of the substrate is SiC, the material of the first epitaxial layer is SiC, and the material of the second epitaxial layer is SiC, that is, the VDMOS terminal structure of the present application is a SiC VDMOS terminal structure.
Specifically, if the doping type of the first epitaxial layer is N-type, the doping type of the second epitaxial layer is P-type; if the doping type of the first epitaxial layer is P-type, the doping type of the second epitaxial layer is N-type.
Specifically, the widths of the plurality of first grooves may be the same or different, and the widths are lengths of the first grooves in the predetermined direction, so that a person skilled in the art may flexibly select whether the widths of the plurality of first grooves are the same or different according to actual needs, which is not particularly limited in this application.
Specifically, the thickness of the substrate is 300-500 μm, the thickness of the first epitaxial layer is 5-30 μm, the thickness of the second epitaxial layer is 0.5-2 μm, and the width of the plurality of first trenches is 1-2 μm.
In the practical application process, a person skilled in the art can flexibly select the doping types of the first epitaxial layer and the second epitaxial layer according to actual needs, which is not particularly limited in the application.
In the embodiment of the present application, fig. 1 exemplarily shows a case where there are 3 first trenches 40 described above. Of course, the number of the first grooves is not limited to 3, but may be 2, 4, or any other number, which is not particularly limited in this application.
The VDMOS terminal structure comprises a plurality of first grooves, a substrate, a first epitaxial layer and a second epitaxial layer, wherein the first grooves are arranged at intervals along a preset direction, the substrate, the first epitaxial layer and the second epitaxial layer are sequentially stacked, the doping types of the first epitaxial layer and the second epitaxial layer are different, each first groove is located in the second epitaxial layer and the first epitaxial layer, and the depth of the plurality of first grooves is gradually reduced in the preset direction. Compared with the problem that the voltage withstand capability of a device is lower due to the fact that P-type ions are directly injected into a first epitaxial layer to form a P-type injection region with changed depth in the VDMOS terminal structure in the prior art, the second epitaxial layer with different doping types from the first epitaxial layer is added to the VDMOS terminal structure, the overall channel electron mobility of the VDMOS is improved, the overall switching performance of a switch is improved, a plurality of first grooves with gradually reduced depth in a preset direction are further added to the VDMOS terminal structure, the concentration degree of electric field distribution generated at the bottoms of grooves with different depths is improved under the action of voltage, compared with the situation that the depths of the grooves are the same, the electric field line distribution at the bottoms of the grooves with different depths is changed, the electric field line density is reduced, after the electric field concentration degree is improved, breakdown voltage is increased, the voltage withstand level of the VDMOS terminal structure is also increased, and therefore the voltage withstand capability of the VDMOS terminal structure is improved.
In addition, for the plurality of first trenches, after determining the depth of each first trench, the same equipment and process as those of the SIC VDMOS gate trench can be used to trench the VDMOS termination structure to form the plurality of first trenches and gate trenches, so that the cell region and the termination region of the device can complete the etching process of the trench in the same process, without designing another process flow and additional equipment, and the reduction of the production and manufacturing costs is realized.
According to a specific embodiment of the present application, as shown in fig. 2, the above VDMOS terminal structure further includes: and a plurality of first implantation regions 50 disposed at intervals along the predetermined direction, wherein the first implantation regions 50 are disposed in the second epitaxial layer 30, the first implantation regions 50 are disposed on the same side of all the first trenches 40, surfaces of the first implantation regions 50 away from the substrate 10 are the same as surfaces of portions of the second epitaxial layer 30 away from the substrate 10, the doping types of the first implantation regions 50 are the same as the doping types of the second epitaxial layer 30, and the doping concentrations of the first implantation regions 50 are greater than the doping concentrations of the second epitaxial layer 30. In this embodiment, a plurality of first injection regions are disposed in the second epitaxial layer along a predetermined direction, so that the influence of surface charges on the electric field distribution of the VDMOS terminal structure is small, thereby further improving the voltage withstand capability of the VDMOS terminal structure and ensuring the reliability of the VDMOS terminal structure.
Specifically, the depths of the plurality of first implantation regions may be the same or different, and a person skilled in the art may flexibly select whether the depths of the plurality of first implantation regions are the same or different according to actual needs, which is not particularly limited in the present application.
In this embodiment, the depth of the plurality of first injection regions is 0.5 micrometers to 1 micrometer.
In the embodiment of the present application, fig. 2 exemplarily illustrates a case where there are 2 first implantation regions 50 described above. Of course, the number of the first implantation regions is not limited to 2, but may be 3, 4, or other numbers, which is not particularly limited in this application.
In an alternative, as shown in fig. 2, the doping concentrations of the plurality of first implantation regions 50 gradually decrease in the predetermined direction. In this embodiment, by setting the doping concentrations of the plurality of first injection regions in the predetermined direction to gradually decrease, the overall doping region concentration distribution of the VDMOS terminal structure can be ensured to be better, and the voltage-withstanding performance of the VDMOS terminal structure is further optimized.
According to another embodiment of the present application, as shown in fig. 2, the width of the plurality of first injection regions 50 in the predetermined direction is gradually reduced, and the width is a distance between two opposite edges of the first injection region 50 in the predetermined direction. In this embodiment, by setting the widths of the plurality of first injection regions in the predetermined direction to be gradually reduced, the area of the voltage division region can be made smaller, the manufacturing cost of the device is guaranteed to be lower, and meanwhile, the depth and concentration distribution of the doping region of the whole VDMOS terminal structure are further guaranteed to be better, so that the voltage resistance performance of the VDMOS terminal structure is further optimized.
According to still another embodiment of the present application, as shown in fig. 2 and fig. 3, the above VDMOS terminal structure further includes: a plurality of second implantation regions 60 disposed at intervals along the predetermined direction, wherein the plurality of second implantation regions 60 are disposed in the first epitaxial layer 20, the first trenches 40 are disposed in the second implantation regions 60 in a one-to-one correspondence, surfaces of the plurality of second implantation regions 60 away from the substrate 10 and surfaces of the second epitaxial layer 30 near the substrate 10 are the same, doping types of the plurality of second implantation regions 60 are the same as doping types of the plurality of first implantation regions 50, and doping concentrations of the plurality of second implantation regions 60 are greater than doping concentrations of the plurality of first implantation regions 50. In this embodiment, a plurality of second injection regions are disposed in the first epitaxial layer along the predetermined direction, and the plurality of second injection regions are located in the second injection regions and are disposed in the first trenches in a one-to-one correspondence manner, and the doping types of the plurality of second injection regions are the same as the doping types of the plurality of first injection regions, i.e., the doping types of the plurality of second injection regions are different from the doping types of the first epitaxial layer, so that the plurality of second injection regions respectively form a plurality of PN junctions with the first epitaxial layer, thereby further relieving electric field concentration at the bottoms of the plurality of first trenches, further improving the electric field concentration degree, further improving the voltage withstand level of the VDMOS terminal structure, and further improving the voltage withstand performance of the VDMOS terminal structure.
Specifically, the doping concentrations of the plurality of second implantation regions may be the same or different, and the depths of the plurality of second implantation regions in the predetermined direction may be gradually reduced as the depths of the plurality of first trenches are gradually reduced in one-to-one correspondence therewith.
Specifically, the width of the plurality of the second implantation regions is 1-5 μm.
In still other exemplary embodiments of the present application, as shown in fig. 3, the above VDMOS terminal structure further includes: and a second trench 70 in the second epitaxial layer 30, wherein the second trench 70 includes a plurality of bottom surfaces connected in sequence, and distances between the plurality of bottom surfaces and a surface of the second epitaxial layer 30 away from the substrate 10 are gradually increased or gradually decreased along the predetermined direction, that is, the plurality of bottom surfaces of the second trench 70 are distributed in a stepwise manner. In this embodiment, the second trench is disposed in the second epitaxial layer, and the second trench includes a plurality of bottom surfaces that are sequentially connected, where the distances between the bottom surfaces and the surfaces of the second epitaxial layer away from the substrate gradually increase or gradually decrease along the predetermined direction, so that the area of the voltage division area can be further ensured to be smaller, the manufacturing cost of the device is further ensured to be lower, and meanwhile, the depth and concentration distribution of the doped region of the whole VDMOS terminal structure are further ensured to be better, so that the voltage withstand capability of the VDMOS terminal structure is further improved.
In this embodiment, as shown in fig. 3, the second trench 70 includes 3 bottom surfaces connected in sequence, and distances between the 3 bottom surfaces of the second trench 70 and a surface of the second epitaxial layer 30 away from the substrate 10 gradually increase along the predetermined direction.
In a specific embodiment, as shown in fig. 2 and fig. 3, the above VDMOS terminal structure further includes: a third implantation region 71 located in the first epitaxial layer 20 and located on a side of the plurality of first implantation regions 50 away from the plurality of second implantation regions 60, wherein a surface of the third implantation region 71 away from the substrate 10 is the same surface as a partial surface of the first epitaxial layer 20 away from the substrate 10, and a doping type of the third implantation region 71 is the same as a doping type of the first epitaxial layer 20; a third trench 72 in the second epitaxial layer 30, wherein a portion of a bottom surface of the third trench 72 is the same surface as a surface of the third implantation region 71 away from the substrate 10; a fourth implantation region 73 located in the first epitaxial layer 20 and located between the first implantation region 50 and the third implantation region 71 adjacent to the third implantation region 71, wherein a surface of the fourth implantation region 73 remote from the substrate 10 is the same as a surface of a portion of the first epitaxial layer 20 remote from the substrate 10, a doping type of the fourth implantation region 73 is the same as a doping type of the plurality of first implantation regions 50, a doping concentration of the fourth implantation region 73 is smaller than a doping concentration of the plurality of first implantation regions 50, and a doping concentration of the fourth implantation region 73 is greater than a doping concentration of the second epitaxial layer 30. In this embodiment, through setting up the third injection zone, can guarantee that the design of terminal area is better, guarantee that the size of terminal area is less, through setting up the fourth injection zone, further guaranteed that the holistic doping area concentration distribution of VDMOS terminal structure is better, simultaneously make the fourth injection zone can form PN junction with first epitaxial layer, still further improved the withstand voltage ability of VDMOS terminal structure, through setting up the third slot, can further guarantee that the bleeder area is less, can further guarantee that the holistic doping area degree of depth and the concentration distribution of VDMOS terminal structure are better simultaneously, further promote the withstand voltage performance of terminal structure.
Specifically, the depth of the third implantation region is 5-15 μm, the width of the third implantation region is 1-2 μm, the width of the third trench is 1-2 μm, the depth of the fourth implantation region is 0.5-1 μm, and the width of the fourth implantation region is 1-3 μm.
In this embodiment, as shown in fig. 2 and 3, the width of the third grooves 72 is larger than the width of all the first grooves 40. Therefore, the depletion layer can be prevented from diffusing to the cut-off ring, and the reliability of the device is further ensured.
More specifically, in some embodiments, as shown in fig. 4 and fig. 5, the above VDMOS terminal structure further includes: a dielectric layer 80 overlying the second epitaxial layer 30 and the plurality of first trenches. In this embodiment, through setting up the dielectric layer, can further guarantee that the influence of the electric field of device surface accumulation to the partial pressure structure of device is less, can guarantee that the effect of partial pressure ring is better, guarantees that the performance of device is better.
Fig. 4 shows a structure obtained by growing a dielectric layer on the basis of fig. 2, and fig. 5 shows a structure obtained by growing a dielectric layer on the basis of fig. 3.
Specifically, the material of the dielectric layer may be silicon oxide, silicon nitride, or other isolation materials, and a person skilled in the art may flexibly select a suitable material of the dielectric layer according to actual needs, which is not particularly limited in this application.
Specifically, the thickness of the dielectric layer is 500-1000 μm.
More specifically, in some embodiments, as shown in fig. 4 and 5, the dielectric layer 80 is further filled in the second trench and the third trench.
In other embodiments, as shown in fig. 1, 2, 3, 4 and 5, the bottom surface of the first trench 40 with the smallest depth among the plurality of first trenches 40 is the same surface as the partial surface of the first epitaxial layer 20 away from the substrate 10.
According to the embodiment of the application, a manufacturing method of the VDMOS terminal structure is also provided.
Fig. 6 is a flowchart of a method for fabricating a VDMOS terminal structure according to an embodiment of the present application. As shown in fig. 6, the method comprises the steps of:
step S101: providing a substrate;
step S102: forming a first epitaxial layer on the exposed surface of the substrate;
step S103: forming a second epitaxial layer on the exposed surface of the first epitaxial layer, wherein the doping types of the first epitaxial layer and the second epitaxial layer are different;
step S104: and forming a plurality of first trenches penetrating through the first epitaxial layer to the second epitaxial layer, wherein the plurality of first trenches are arranged at intervals in a predetermined direction, the depth of the plurality of first trenches in the predetermined direction gradually decreases, the predetermined direction is a direction perpendicular to the thickness of the substrate, and the depth is the length of the first trenches in the thickness direction of the substrate.
Specifically, the material of the substrate is SiC, the material of the first epitaxial layer is SiC, and the material of the second epitaxial layer is SiC.
Specifically, if the doping type of the first epitaxial layer is N-type, the doping type of the second epitaxial layer is P-type; if the doping type of the first epitaxial layer is P-type, the doping type of the second epitaxial layer is N-type.
Specifically, the widths of the plurality of first grooves may be the same or different, and the widths are lengths of the first grooves in the predetermined direction, so that a person skilled in the art may flexibly select whether the widths of the plurality of first grooves are the same or different according to actual needs, which is not particularly limited in this application.
Specifically, the thickness of the substrate is 300-500 μm, the thickness of the first epitaxial layer is 5-30 μm, the thickness of the second epitaxial layer is 0.5-2 μm, and the width of the plurality of first trenches is 1-2 μm.
In the practical application process, a person skilled in the art can flexibly select the doping types of the first epitaxial layer and the second epitaxial layer according to actual needs, which is not particularly limited in the application.
In the method for manufacturing the VDMOS terminal structure, firstly, a substrate is provided; then, forming a first epitaxial layer on the exposed surface of the substrate; forming a second epitaxial layer on the exposed surface of the first epitaxial layer, wherein the doping types of the first epitaxial layer and the second epitaxial layer are different; finally, a plurality of first trenches penetrating through the first epitaxial layer to the second epitaxial layer are formed, the plurality of first trenches are arranged at intervals in a predetermined direction, and the depth of the plurality of first trenches is gradually reduced in the predetermined direction. Compared with the problem of lower voltage withstand capability of a device caused by directly injecting P-type ions into a first epitaxial layer to form a P-type injection region with changed depth in the VDMOS terminal structure in the prior art, the VDMOS terminal structure obtained by the method has the advantages that a second epitaxial layer with different doping types from the first epitaxial layer is added, the channel electron mobility of the whole VDMOS is improved, and the switching performance of the whole VDMOS terminal structure is improved; compared with the VDMOS terminal structure with the same depth of the grooves, in the VDMOS terminal structure, the depth of the first grooves is gradually reduced in the preset direction, so that under the action of voltage, the electric field line distribution at the bottoms of the grooves with different depths is changed, the electric field line density is reduced, the concentration degree of the electric field distribution generated at the bottoms of the grooves with different depths is improved, after the concentration degree of the electric field is improved, the breakdown voltage is increased, the voltage withstand level of the VDMOS terminal structure is also increased, and the voltage withstand performance of the VDMOS terminal structure is improved.
In addition, for the plurality of first trenches, after determining the depth of each first trench, the same equipment and process as those of the SIC VDMOS gate trench can be used to trench the VDMOS termination structure to form the plurality of first trenches, so that the cell region and the termination region of the device can complete the etching process of the trench in the same process, without needing another design process flow and additional equipment, and the reduction of production and manufacturing costs is realized.
In other embodiments, the method further comprises, prior to forming the second epitaxial layer on the exposed surface of the first epitaxial layer: performing ion implantation on the first epitaxial layer to form a plurality of second preparation implantation regions in the first epitaxial layer, wherein the second preparation implantation regions are arranged at intervals along the preset direction, the surfaces of the second preparation implantation regions, which are far away from the substrate, are the same surface as the partial surfaces of the first epitaxial layer, which are far away from the substrate, and the doping types of the second preparation implantation regions are different from the doping types of the first epitaxial layer; performing ion implantation on the first epitaxial layer to form a third implantation region in the first epitaxial layer, wherein the third implantation region is positioned at one side of the plurality of second preparation implantation regions, the surface of the third implantation region, which is far away from the substrate, is the same surface as the partial surface of the first epitaxial layer, which is far away from the substrate, and the doping type of the third implantation region is the same as the doping type of the first epitaxial layer; and performing ion implantation on the first epitaxial layer to form a fourth implantation region in the first epitaxial layer, wherein the fourth implantation region is positioned between the second preparation implantation region adjacent to the third implantation region and the third implantation region, the surface of the fourth implantation region, which is far away from the substrate, is the same surface as the partial surface of the first epitaxial layer, which is far away from the substrate, and the doping type of the fourth implantation region is different from the doping type of the first epitaxial layer, and the doping concentration of the fourth implantation region is less than the doping concentration of all the second preparation implantation regions.
In order to enable those skilled in the art to more clearly understand the technical solutions of the present application, the following describes in detail the implementation procedure of the method for manufacturing the VDMOS terminal structure of the present application in combination with specific embodiments.
The embodiment relates to a specific manufacturing method of a VDMOS terminal structure, which comprises the following steps:
step S1: providing a substrate;
step S2: forming a first epitaxial layer on an exposed surface of a substrate;
step S3: performing P-type ion implantation on the first epitaxial layer to form a plurality of second preparation implantation regions which are arranged at intervals along a preset direction in the first epitaxial layer, wherein the surfaces of the second preparation implantation regions, which are far away from the substrate, and the partial surfaces of the first epitaxial layer, which are far away from the substrate, are the same surface, and the doping types of the second preparation implantation regions are different from those of the first epitaxial layer;
step S4: performing N-type ion implantation on the first epitaxial layer to form a third implantation region in the first epitaxial layer, wherein the third implantation region is positioned at one side of the plurality of second preparation implantation regions, the surface of the third implantation region, which is far away from the substrate, and the partial surface of the first epitaxial layer, which is far away from the substrate, are the same surface, and the doping type of the third implantation region is the same as that of the first epitaxial layer;
Step S5: performing P-type ion implantation on the first epitaxial layer to form a fourth implantation region in the first epitaxial layer, wherein the fourth implantation region is positioned between a second preparation implantation region adjacent to the third implantation region and the third implantation region, the surface of the fourth implantation region, which is far away from the substrate, and the partial surface of the first epitaxial layer, which is far away from the substrate are the same surface, the doping type of the fourth implantation region is different from that of the first epitaxial layer, and the doping concentration of the fourth implantation region is less than that of all the second preparation implantation regions;
step S6: forming a second epitaxial layer on the exposed surface of the first epitaxial layer, wherein the doping types of the first epitaxial layer and the second epitaxial layer are different, and the doping concentration of the second epitaxial layer is smaller than that of the fourth injection region;
step S7: performing P-type ion implantation on the second epitaxial layer to form a plurality of first implantation regions arranged at intervals along a preset direction in the second epitaxial layer, wherein all the first implantation regions are positioned between a second preparation implantation region and a fourth implantation region which are adjacent to the fourth implantation region, the surfaces of the plurality of first implantation regions far away from the substrate and the partial surfaces of the second epitaxial layer far away from the substrate are the same surface, the doping types of the plurality of first implantation regions are the same as those of the second epitaxial layer, the doping concentration of all the first implantation regions is smaller than that of the second preparation implantation region, the doping concentration of all the first implantation regions is larger than that of the fourth implantation region, and the width of the plurality of first implantation regions is gradually reduced in the preset direction;
Step S8: the first epitaxial layer, the second preparation injection region and the second epitaxial layer are etched by a dry method to form a plurality of first grooves penetrating the first epitaxial layer to the second epitaxial layer, second grooves in the second epitaxial layer and third grooves in the second epitaxial layer, the rest of the second preparation injection region forms the second injection region, the first grooves are arranged at intervals in a preset direction, the first grooves are correspondingly arranged in the second injection region one by one, the depth of the first grooves is gradually reduced in the preset direction, the preset direction is a direction perpendicular to the thickness of the substrate, the depth is the length of the first grooves in the thickness direction of the substrate, the second grooves comprise a plurality of bottom surfaces which are sequentially connected, the distance between the bottom surfaces and the surface of the second epitaxial layer away from the substrate is gradually increased or gradually reduced along the preset direction, the second grooves are positioned on one side of all the first grooves, part of the bottom surfaces of the third grooves and the surface of the third injection region away from the substrate are the same surface, and the third grooves are positioned on one side of the second grooves away from the first grooves;
step S9: and covering a dielectric layer on the second epitaxial layer, in the plurality of first grooves, in the second groove and in the third groove, and finally obtaining the VDMOS terminal structure.
Specifically, the material of the dielectric layer may be silicon oxide, silicon nitride, or other isolation materials, and a person skilled in the art may flexibly select a suitable material of the dielectric layer according to actual needs, which is not particularly limited in this application.
Specifically, the depth of the plurality of first implant regions is 0.5 to 1 μm, the width of the plurality of second implant regions is 1 to 5 μm, the depth of the third implant region is 5 to 15 μm, the width of the third implant region is 1 to 2 μm, the width of the third trench is 1 to 2 μm, the depth of the fourth implant region is 0.5 to 1 μm, the width of the fourth implant region is 1 to 3 μm, and specifically, the thickness of the dielectric layer is 500 to 1000 μm.
According to still another aspect of the present application, there is provided a semiconductor device including: any of the above VDMOS termination structures.
The semiconductor device includes any one of the above VDMOS termination structures, where the VDMOS termination structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a plurality of first trenches in the first epitaxial layer and in the second epitaxial layer, the plurality of first trenches being arranged at intervals along a predetermined direction, the first epitaxial layer and the second epitaxial layer being different in doping type, each of the first trenches being in the second epitaxial layer and the first epitaxial layer, and a depth of the plurality of first trenches gradually decreasing in the predetermined direction. Compared with the problem of lower voltage withstand capability of a device caused by directly injecting P-type ions into a first epitaxial layer to form a P-type injection region with changed depth in the VDMOS terminal structure in the prior art, the VDMOS terminal structure of the invention has the advantages that a second epitaxial layer with different doping types from the first epitaxial layer is added, the channel electron mobility of the VDMOS is improved, and the switching performance of the VDMOS terminal structure is improved; compared with the VDMOS terminal structure with the same depth of the grooves, in the VDMOS terminal structure, the depth of the first grooves is gradually reduced in the preset direction, so that under the action of voltage, the electric field line distribution at the bottoms of the grooves with different depths is changed, the electric field line density is reduced, the concentration degree of the electric field distribution generated at the bottoms of the grooves with different depths is improved, after the concentration degree of the electric field is improved, the breakdown voltage is increased, the voltage withstand level of the VDMOS terminal structure is also increased, and the voltage withstand performance of the VDMOS terminal structure is improved.
According to still another aspect of the present application, there is provided a method for manufacturing a VDMOS terminal structure, including:
from the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) In the VDMOS terminal structure of the present application, the VDMOS terminal structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a plurality of first trenches in the first epitaxial layer and in the second epitaxial layer, where the plurality of first trenches are arranged at intervals along a predetermined direction, the doping types of the first epitaxial layer and the second epitaxial layer are different, and each of the first trenches is located in the second epitaxial layer and the first epitaxial layer, and the depths of the plurality of first trenches in the predetermined direction are gradually reduced. Compared with the problem of lower voltage withstand capability of a device caused by directly injecting P-type ions into a first epitaxial layer to form a P-type injection region with changed depth in the VDMOS terminal structure in the prior art, the VDMOS terminal structure of the invention has the advantages that a second epitaxial layer with different doping types from the first epitaxial layer is added, the channel electron mobility of the VDMOS is improved, and the switching performance of the VDMOS terminal structure is improved; compared with the VDMOS terminal structure with the same depth of the grooves, in the VDMOS terminal structure, the depth of the first grooves is gradually reduced in the preset direction, so that under the action of voltage, the electric field line distribution at the bottoms of the grooves with different depths is changed, the electric field line density is reduced, the concentration degree of the electric field distribution generated at the bottoms of the grooves with different depths is improved, after the concentration degree of the electric field is improved, the breakdown voltage is increased, the voltage withstand level of the VDMOS terminal structure is also increased, and the voltage withstand performance of the VDMOS terminal structure is improved.
2) In a semiconductor device of the present application, including any one of the above VDMOS terminal structures, the above VDMOS terminal structure includes a plurality of first trenches disposed at intervals along a predetermined direction, and a substrate, a first epitaxial layer, and a second epitaxial layer stacked in order, where the doping types of the first epitaxial layer and the second epitaxial layer are different, and each of the first trenches is located in the second epitaxial layer and the first epitaxial layer, and the depths of the plurality of first trenches gradually decrease in the predetermined direction. Compared with the problem of lower voltage withstand capability of a device caused by directly injecting P-type ions into a first epitaxial layer to form a P-type injection region with changed depth in the VDMOS terminal structure in the prior art, the VDMOS terminal structure obtained by the method has the advantages that a second epitaxial layer with different doping types from the first epitaxial layer is added, the channel electron mobility of the whole VDMOS is improved, and the switching performance of the whole VDMOS terminal structure is improved; compared with the VDMOS terminal structure with the same depth of the grooves, in the VDMOS terminal structure, the depth of the first grooves is gradually reduced in the preset direction, so that under the action of voltage, the electric field line distribution at the bottoms of the grooves with different depths is changed, the electric field line density is reduced, the concentration degree of the electric field distribution generated at the bottoms of the grooves with different depths is improved, after the concentration degree of the electric field is improved, the breakdown voltage is increased, the voltage withstand level of the VDMOS terminal structure is also increased, and the voltage withstand performance of the VDMOS terminal structure is improved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (10)
1. A VDMOS termination structure comprising:
a substrate;
a first epitaxial layer on a surface of the substrate;
a second epitaxial layer on a surface of the first epitaxial layer remote from the substrate, the first epitaxial layer being of a different doping type than the second epitaxial layer;
and the first trenches are arranged at intervals along a preset direction, are positioned in the second epitaxial layer and the first epitaxial layer, and gradually reduce in depth in the preset direction, wherein the preset direction is a direction perpendicular to the thickness of the substrate, and the depth is the length of the first trenches in the thickness direction of the substrate.
2. The VDMOS terminal structure of claim 1, further comprising:
the first implantation regions are located in the second epitaxial layer at intervals along the preset direction, each first implantation region is located on the same side of all the first trenches, the surfaces of the first implantation regions, which are far away from the substrate, and the surfaces of the second epitaxial layer, which are far away from the substrate, are the same, the doping types of the first implantation regions are the same as those of the second epitaxial layer, and the doping concentration of the first implantation regions is larger than that of the second epitaxial layer.
3. The VDMOS termination structure of claim 2, wherein the doping concentrations of the plurality of first implant regions in the predetermined direction decrease gradually.
4. The VDMOS termination structure of claim 2, wherein the plurality of first injection regions have a gradually decreasing width in the predetermined direction, the width being a distance between two opposite edges of the first injection region in the predetermined direction.
5. The VDMOS terminal structure of claim 2, further comprising:
the second implantation regions are arranged in the first epitaxial layer at intervals along the preset direction, the first trenches are correspondingly arranged in the second implantation regions one by one, the surfaces of the second implantation regions, which are far away from the substrate, and the partial surfaces of the second epitaxial layer, which are close to the substrate, are the same, the doping types of the second implantation regions are the same as the doping types of the first implantation regions, and the doping concentration of the second implantation regions is larger than that of the first implantation regions.
6. The VDMOS terminal structure of claim 1, further comprising:
The second groove is positioned in the second epitaxial layer, the second groove comprises a plurality of bottom surfaces which are sequentially connected, and the distances between the bottom surfaces and the surface, far away from the substrate, of the second epitaxial layer are gradually increased or gradually decreased along the preset direction.
7. The VDMOS terminal structure of claim 5, further comprising:
the third injection region is positioned in the first epitaxial layer and is positioned at one side of the plurality of first injection regions, which is far away from the plurality of second injection regions, the surface of the third injection region, which is far away from the substrate, is the same surface as the partial surface of the first epitaxial layer, which is far away from the substrate, and the doping type of the third injection region is the same as that of the first epitaxial layer;
the third groove is positioned in the second epitaxial layer, and part of the bottom surface of the third groove and the surface of the third injection region, which is far away from the substrate, are the same surface;
the fourth injection region is positioned in the first epitaxial layer and between the first injection region and the third injection region, the surface of the fourth injection region, which is far away from the substrate, is the same as the partial surface of the first epitaxial layer, which is far away from the substrate, the doping type of the fourth injection region is the same as the doping type of a plurality of first injection regions, the doping concentration of the fourth injection region is smaller than the doping concentration of a plurality of first injection regions, and the doping concentration of the fourth injection region is larger than the doping concentration of the second epitaxial layer.
8. The VDMOS terminal structure of any of claims 1 to 7, further comprising:
and the dielectric layer is covered on the second epitaxial layer and in the plurality of first grooves.
9. The VDMOS termination structure of any of claims 1-7, wherein a bottom surface of the first trench of the smallest depth of the plurality of first trenches is the same surface as a portion of the surface of the first epitaxial layer that is remote from the substrate.
10. A semiconductor device, comprising: the VDMOS termination structure of any of claims 1 to 9.
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