CN117525059A - Miniaturized high-density module - Google Patents

Miniaturized high-density module Download PDF

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Publication number
CN117525059A
CN117525059A CN202311491047.8A CN202311491047A CN117525059A CN 117525059 A CN117525059 A CN 117525059A CN 202311491047 A CN202311491047 A CN 202311491047A CN 117525059 A CN117525059 A CN 117525059A
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CN
China
Prior art keywords
silicon
substrate
packaging unit
layer
based packaging
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Pending
Application number
CN202311491047.8A
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Chinese (zh)
Inventor
杜顺勇
笪余生
赖浩翔
陈森
陶霞
兰伯章
王淮
张童童
李虹萍
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CETC 29 Research Institute
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CETC 29 Research Institute
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Publication date
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Priority to CN202311491047.8A priority Critical patent/CN117525059A/en
Publication of CN117525059A publication Critical patent/CN117525059A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a miniaturized high-density module, belongs to the technical field of hardware circuit design, and solves the problem of airtight and matching limitation of the existing chip stacking structure; the packaging structure comprises an LTCC substrate and a silicon-based packaging unit; the upper surface of the LTCC substrate is connected with the lower surface of the silicon-based packaging unit through the first solder balls, so that signal interconnection of the LTCC substrate and the silicon-based packaging unit is realized; the lower surface of the LTCC substrate is connected with the PCB motherboard through a second solder ball; the LTCC substrate is used for accommodating the packaging chip, and the silicon-based packaging unit is used for accommodating the hierarchical chip; the structure of the silicon-based packaging unit is formed from bottom to top in sequence: the first silicon substrate, the first silicon frame, the second silicon substrate, the second silicon frame and the third silicon substrate are connected through wafer-level bonding; the invention improves the matching property with the motherboard through the transfer of the LTCC substrate, and has better air tightness and higher reliability.

Description

Miniaturized high-density module
Technical Field
The invention belongs to the technical field of hardware circuit design, and is applied to a multilayer stacking integration technology of components, in particular to a miniaturized high-density module.
Background
With the rapid development of modern communication and radar technology, the demand for microwave circuits featuring miniaturization, low cost and high reliability has been increasing. In the prior art, stacking and integrating technology is one of important technical paths for realizing miniaturization of a module circuit by layering components in different circuit substrates.
However, the limitation of the prior art still lies in the air tightness and matching property of the stacked structure, so how to realize the vertical interconnection transmission of the multi-layer stack of the chips and the radio frequency signal and simultaneously ensure the high reliability of the upper plate under the condition of ensuring the air tightness of the micro-module becomes the research focus of the person skilled in the art.
Disclosure of Invention
Aiming at the current situation in the background technology, the invention provides a miniaturized high-density module, and the multi-layer chip stacking is completed through a TSV process, so that high-density integration and vertical interconnection of radio frequency signals are realized, and meanwhile, the effect of high heat dissipation is also considered. The invention improves the matching property with the motherboard through the transfer of the internal LTCC substrate, so that the reliability of the whole module is higher, and the control wiring density is improved through the LTCC substrate.
The invention adopts the following technical scheme to achieve the purpose:
a miniaturized high-density module comprises an LTCC substrate and a silicon-based packaging unit; the upper surface of the LTCC substrate is connected with the lower surface of the silicon-based packaging unit through the first solder balls, so that signal interconnection of the LTCC substrate and the silicon-based packaging unit is realized; the lower surface of the LTCC substrate is connected with the PCB motherboard through a second solder ball; the LTCC substrate is used for accommodating packaging chips, and the silicon-based packaging unit is used for accommodating multiple layers of chips.
Specifically, the second solder balls are high-lead solder balls; radio frequency and low frequency signals are transmitted into the LTCC substrate through the high lead solder balls, pass through the internal signal holes in the LTCC substrate, pass through the upper surface of the LTCC substrate from the lower surface of the LTCC substrate, and then enter the silicon-based packaging unit through the first solder balls.
Further, the structure of the silicon-based packaging unit is formed from bottom to top in sequence: a first silicon substrate, a first silicon frame, a second silicon substrate, a second silicon frame, and a third silicon substrate; the structural components of the silicon-based packaging unit are connected through wafer-level bonding.
Further, the first silicon substrate, the second silicon substrate and the third silicon substrate have the same hierarchical structure, and the hierarchical structure is as follows: the semiconductor device comprises a bottom surface metal layer, a silicon structure layer, a middle wiring layer, a PI layer and a top surface metal layer; a substrate signal hole is formed in the PI layer, and a TSV hole is formed in the silicon structure layer; when radio frequency and low frequency signals are transmitted to each silicon substrate, signal interconnection among structural components of the silicon-based packaging unit is realized through the substrate signal holes and the TSV holes.
Further, the number of the level chips is 3, and the level chips are respectively adhered to the upper surface of the first silicon substrate, the upper surface of the second silicon substrate and the lower surface of the third silicon substrate; each level chip is interconnected with metal patterns in the silicon substrate at corresponding positions through gold wires.
Specifically, the bonding connection area of each structural component in the silicon-based packaging unit is a reserved metal area.
Further, the first silicon frame and the second silicon frame have the same hierarchical structure, and the hierarchical structure is that from bottom to top: a bottom metal layer, a silicon structure layer and a top metal layer; TSV holes are formed in the silicon structure layer; when radio frequency and low frequency signals are transmitted to each silicon frame, signal interconnection among all structural components of the silicon-based packaging unit is realized through the TSV holes.
Preferably, the TSV hole includes a radio frequency signal transmission hole and a low frequency signal transmission hole; copper layer avoidance is arranged outside the metal bonding pad of the radio frequency signal transmission hole, and a plurality of shielding holes are uniformly surrounded outside the copper layer avoidance; copper sheet avoidance is arranged outside the metal bonding pad of the low-frequency signal transmission hole; the TSV holes arranged on the silicon substrate correspond to the TSV holes arranged on the silicon frame, and the corresponding bonding pad positions of each TSV hole are reserved before the structural components of the silicon-based packaging unit are connected.
Preferably, a metal heat sink is welded on the upper surface of the third silicon substrate.
Specifically, a concave cavity area is formed in the lower surface of the LTCC substrate, and a packaging chip is arranged in the concave cavity area; and a multi-layer passive circuit is arranged in the LTCC substrate, and signals of the packaged chip penetrate through the multi-layer passive circuit to the first solder ball so as to realize signal interconnection with the silicon-based packaging unit.
In summary, by adopting the technical scheme, the invention has the following beneficial effects:
1. the invention realizes the multilayer stacking and high-density wiring of chips while ensuring the air tightness;
2. the invention can realize good expansion between the module and the PCB motherboard by the transfer of the silicon base and the LTCC substrate, thereby improving the mismatching phenomenon when the silicon base unit is directly welded with the PCB motherboard;
3. the invention integrates the LTCC substrate in the module, realizes multi-layer radio frequency interconnection and complex low-frequency wiring, and solves the defect of weak silicon-based wiring capability; meanwhile, the bottom is welded with the packaging chip, so that the complex signal control of the miniaturized high-density module is realized;
4. according to the invention, the metal heat dissipation piece is welded at the top, so that the whole module can dissipate heat better.
Drawings
FIG. 1 is a schematic diagram of the overall structure of the module of the present invention;
FIG. 2 is a schematic diagram of a silicon substrate in a hierarchical structure according to the present invention;
FIG. 3 is a schematic view of a silicon frame in the present invention;
FIG. 4 is a schematic top view of a silicon-based package unit and a metal region thereof according to the present invention;
FIG. 5 is a side view of a silicon-based package unit in a hierarchical structure according to the present invention;
FIG. 6 is a schematic diagram of a silicon frame and signal transmission holes thereof according to the present invention;
FIG. 7 is a schematic diagram of a connection structure of a top metal layer according to the present invention;
fig. 8 is a schematic diagram of a hierarchical structure of an LTCC substrate according to the present invention.
The meaning of the symbols in the drawings is specifically as follows:
1-LTCC substrate, 11-first silicon substrate, 12-first silicon frame, 13-second silicon substrate, 14-second silicon frame, 15-third silicon substrate, 2-silicon-based packaging unit, 21-top metal layer, 22-PI layer, 23-middle wiring layer, 24-silicon structure layer, 25-bottom metal layer, 26-substrate signal hole, 27-TSV hole, 28-metal region, 29-low frequency signal transmission hole, 30-radio frequency signal transmission hole, 31-gold wire, 32-pad position, 4-level chip, 41-metal heat sink, 5-packaging chip, 6-first solder ball, 7-second solder ball.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 1, a miniaturized high-density module comprises an LTCC substrate 1 and a silicon-based packaging unit 2; the upper surface of the LTCC substrate 1 is connected with the lower surface of the silicon-based packaging unit 2 through the first solder balls 6, so that signal interconnection of the LTCC substrate 1 and the silicon-based packaging unit 2 is realized; the lower surface of the LTCC substrate 1 is connected with a PCB motherboard through a second solder ball 7; the LTCC substrate 1 is used for accommodating package chips 5, and the silicon-based package unit 2 is used for accommodating multiple levels of chips 4.
By arranging the LTCC substrate 1 in the embodiment, not only the signal interconnection function is realized, but also the thermal expansion mismatch between the silicon substrate and the motherboard can be improved, so that the reliability of the micro-module is greatly improved.
In this embodiment, the second solder balls 7 are high lead solder balls; radio frequency and low frequency signals are transmitted into the LTCC substrate 1 through the high lead solder balls, pass through the internal signal holes in the LTCC substrate 1, pass through the upper surface of the lower surface of the LTCC substrate 1, and then enter the silicon-based packaging unit 2 through the first solder balls 6.
Example 2
On the basis of embodiment 1, this embodiment specifically describes a silicon-based package unit 2.
As shown in fig. 1, the structure of the silicon-based packaging unit 2 is formed sequentially from bottom to top: a first silicon substrate 11, a first silicon frame 12, a second silicon substrate 13, a second silicon frame 14, and a third silicon substrate 15; the structural components of the silicon-based packaging unit 2 are connected by wafer-level bonding.
Based on the above structure, the number of the laminate chips 4 in this embodiment is 3, and reference may be made to the schematic of fig. 1 or fig. 5. The level chip 4 is adhered to the upper surface of the first silicon substrate 11, the upper surface of the second silicon substrate 13, and the lower surface of the third silicon substrate 15, respectively; each hierarchical chip 4 is interconnected with metal patterns in the silicon substrate at corresponding positions through the gold wires 31, so that the power-up and signal transmission processes of the chips are realized.
In the silicon-based packaging unit 2 of the present embodiment, as shown in fig. 4 and 5, bonding connection areas of the first silicon substrate 11, the first silicon frame 12, the second silicon substrate 13, the second silicon frame 14 and the third silicon substrate 15 are all reserved metal areas 28, so as to ensure the air tightness of the silicon-based packaging unit 2.
Example 3
Based on embodiment 2, the present embodiment specifically describes the hierarchical structure of the silicon substrate and the silicon frame.
As shown in fig. 2, the first silicon substrate 11, the second silicon substrate 13, and the third silicon substrate 15 have the same hierarchical structure, which is sequentially: a bottom metal layer 25, a silicon structural layer 24, a middle routing layer 23, a PI layer 22 and a top metal layer 21.
A substrate signal hole 26 is arranged in the PI layer 22, and a TSV hole 27 is arranged in the silicon structure layer 25; when radio frequency and low frequency signals are transmitted to each silicon substrate, signal interconnection between each structural component of the silicon-based packaging unit 2 is achieved through the substrate signal holes 26 and the TSV holes 27.
As shown in fig. 3, the first silicon frame 12 and the second silicon frame 14 have the same hierarchical structure, and the hierarchical structure is that: a bottom metal layer 25, a silicon structural layer 24, and a top metal layer 21.
A TSV hole 27 is provided in the silicon structure layer 24; when radio frequency and low frequency signals are transmitted to each silicon frame, signal interconnection between each structural component of the silicon-based packaging unit 2 is achieved through the TSV holes 27.
In the present embodiment, as shown in fig. 6, the TSV hole 27 includes a radio frequency signal transmission hole 30 and a low frequency signal transmission hole 29; the metal bonding pad of radio frequency signal transmission hole 30 is provided with the copper layer and dodges outward to dodge outside evenly enclosing and establish a plurality of shielding holes at the copper layer.
Copper sheet avoidance is arranged outside the metal bonding pad of the low-frequency signal transmission hole 29, so that short circuit phenomenon is avoided during bonding; the positions of the TSV holes 27 arranged on the silicon substrate and the copper layers or copper sheets of the TSV holes 27 arranged on the silicon frame correspond to each other so as to ensure the air tightness of the silicon-based packaging unit 2. Meanwhile, each TSV hole 27 is reserved with a corresponding pad position 32 for the bonding process before the connection of the structural components of the silicon-based packaging unit 2, so as to ensure smooth transmission of the signal holes therein.
Example 4
On the basis of the above embodiments, the present embodiment introduces a detail perfected structure.
In this embodiment, as shown in fig. 7, a metal heat sink 41 is soldered on the upper surface of the third silicon substrate 15, which is beneficial to heat dissipation of the entire silicon-based package unit 2. The TSV holes 27 of the silicon structure layer 25 in the third silicon substrate 15 are shown; since the level chip 4 corresponding to the third silicon substrate 15 is located on the lower surface thereof, the TSV hole 27 is still perforated with respect to the bottom of the chip, so as to realize the interconnection transmission of the chip signal through the third silicon substrate 15.
In this embodiment, as shown in fig. 8, a cavity area is provided on the lower surface of the LTCC substrate 1, and a package chip 5 is provided in the cavity area; a multi-layer passive circuit is arranged in the LTCC substrate 1 to realize radio frequency wiring interconnection of multi-layer high-density wiring; the signals of the packaging chip 5 penetrate to the first solder balls 6 through the multilayer passive circuit, so that the signals of the silicon-based packaging unit 2 are interconnected.

Claims (10)

1. A miniaturized high density module, its characterized in that: comprises an LTCC substrate (1) and a silicon-based packaging unit (2); the upper surface of the LTCC substrate (1) is connected with the lower surface of the silicon-based packaging unit (2) through a first solder ball (6), so that signal interconnection of the LTCC substrate (1) and the silicon-based packaging unit (2) is realized; the lower surface of the LTCC substrate (1) is connected with the PCB motherboard through a second solder ball (7); the LTCC substrate (1) is used for accommodating package chips (5), and the silicon-based package unit (2) is used for accommodating a plurality of level chips (4).
2. A miniaturized high density module as set forth in claim 1, wherein: the second solder balls (7) are high-lead solder balls; radio frequency and low frequency signals are transmitted into the LTCC substrate (1) through the high lead solder balls, pass through internal signal holes in the LTCC substrate (1), pass through the lower surface of the LTCC substrate (1) to the upper surface, and then enter the silicon-based packaging unit (2) through the first solder balls (6).
3. A miniaturized high density module as set forth in claim 1, wherein: the structure of the silicon-based packaging unit (2) is formed from bottom to top in sequence: a first silicon substrate (11), a first silicon frame (12), a second silicon substrate (13), a second silicon frame (14), and a third silicon substrate (15); the structural components of the silicon-based packaging unit (2) are connected through wafer-level bonding.
4. A miniaturized high density module as set forth in claim 3 wherein: the first silicon substrate (11), the second silicon substrate (13) and the third silicon substrate (15) have the same hierarchical structure, and the hierarchical structure is as follows: a bottom surface metal layer (25), a silicon structure layer (24), a middle wiring layer (23), a PI layer (22) and a top surface metal layer (21); a substrate signal hole (26) is formed in the PI layer (22), and a TSV hole (27) is formed in the silicon structure layer (24); when radio frequency and low frequency signals are transmitted to each silicon substrate, signal interconnection among structural components of the silicon-based packaging unit (2) is achieved through the substrate signal holes (26) and the TSV holes (27).
5. A miniaturized high density module as set forth in claim 3 wherein: the number of the hierarchical chips (4) is 3, and the hierarchical chips are respectively adhered to the upper surface of the first silicon substrate (11), the upper surface of the second silicon substrate (13) and the lower surface of the third silicon substrate (15); each level chip (4) is interconnected with the metal pattern in the silicon substrate at the corresponding location by a gold wire (31).
6. A miniaturized high density module as set forth in claim 3 wherein: the bonding connection area of each structural component in the silicon-based packaging unit (2) is a reserved metal area (28).
7. A miniaturized high density module as set forth in claim 3 wherein: the first silicon frame (12) and the second silicon frame (14) have the same hierarchical structure, and the hierarchical structure is as follows from bottom to top: a bottom metal layer (25), a silicon structural layer (24) and a top metal layer (21); a TSV hole (27) is arranged in the silicon structure layer (24); when radio frequency and low frequency signals are transmitted to each silicon frame, signal interconnection among all structural components of the silicon-based packaging unit (2) is realized through the TSV holes (27).
8. A miniaturized high density module as set forth in claim 4 or 7, wherein: the TSV hole (27) comprises a radio frequency signal transmission hole (30) and a low frequency signal transmission hole (29); copper layer avoidance is arranged outside the metal bonding pad of the radio frequency signal transmission hole (30), and a plurality of shielding holes are uniformly formed in the copper layer avoidance outside in a surrounding mode; copper sheet avoidance is arranged outside the metal bonding pad of the low-frequency signal transmission hole (29); the positions of the TSV holes (27) arranged on the silicon substrate correspond to the positions of the TSV holes (27) arranged on the silicon frame, and the corresponding bonding pad positions (32) are reserved for each TSV hole (27) before the structural components of the silicon-based packaging unit (2) are connected.
9. A miniaturized high density module as set forth in claim 3 wherein: and a metal heat radiating member (41) is welded on the upper surface of the third silicon substrate (15).
10. A miniaturized high density module as set forth in claim 1, wherein: the lower surface of the LTCC substrate (1) is provided with a concave cavity area, and a packaging chip (5) is arranged in the concave cavity area; the LTCC substrate (1) is internally provided with a multi-layer passive circuit, and signals of the packaging chip (5) penetrate to the first solder balls (6) through the multi-layer passive circuit, so that signal interconnection with the silicon-based packaging unit (2) is realized.
CN202311491047.8A 2023-11-09 2023-11-09 Miniaturized high-density module Pending CN117525059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311491047.8A CN117525059A (en) 2023-11-09 2023-11-09 Miniaturized high-density module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311491047.8A CN117525059A (en) 2023-11-09 2023-11-09 Miniaturized high-density module

Publications (1)

Publication Number Publication Date
CN117525059A true CN117525059A (en) 2024-02-06

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Application Number Title Priority Date Filing Date
CN202311491047.8A Pending CN117525059A (en) 2023-11-09 2023-11-09 Miniaturized high-density module

Country Status (1)

Country Link
CN (1) CN117525059A (en)

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