CN117524880A - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN117524880A CN117524880A CN202311535788.1A CN202311535788A CN117524880A CN 117524880 A CN117524880 A CN 117524880A CN 202311535788 A CN202311535788 A CN 202311535788A CN 117524880 A CN117524880 A CN 117524880A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 230000008569 process Effects 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims description 45
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 37
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 30
- 238000004364 calculation method Methods 0.000 claims description 13
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- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 230000004308 accommodation Effects 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 abstract description 5
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- 238000010586 diagram Methods 0.000 description 3
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- 229910021645 metal ion Inorganic materials 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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Abstract
The application belongs to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing method of a semiconductor device and the semiconductor device, comprising the following steps: manufacturing a first wafer, wherein the first wafer comprises a base layer and a target structure layer, a containing groove is formed in the first side of the base layer, and part or all of the target structure layer is located in the containing groove; dividing the target structure layer into a normal region and a deviation region according to the height of the upper surface of the target structure layer relative to the first side; correspondingly designing the volume of the accommodating groove of the corresponding deviation zone on the second wafer according to the deviation of the height of the deviation zone on the first wafer relative to the height of the normal zone; and manufacturing a second wafer, wherein at least part of the target structure layer of the second wafer and part of the target structure layer of the first wafer are manufactured by adopting the same process conditions. By increasing or decreasing the volume of the accommodating groove on the second wafer, the height of the upper surface of the target structure layer can be controlled, the consistency of the film thickness of the target structure layer is improved, and the yield of the semiconductor device is improved.
Description
Technical Field
The application belongs to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing method of a semiconductor device and the semiconductor device.
Background
In the fabrication of semiconductor devices, it is often necessary to form a target structural layer on a substrate or one or more structural layers on a substrate, with grooves formed in the substrate or one or more structural layers on the substrate, and with the target structural layer partially or entirely formed within the grooves.
The recess structure limited by the substrate or one or more structural layers on the substrate, and the fabrication process of the target structural layer, the film layer height uniformity of the target structural layer is poor, resulting in a reduced yield of semiconductor devices.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device and the semiconductor device, so as to improve the yield of the semiconductor device.
In order to achieve the above object, the present application provides a method for manufacturing a semiconductor device, including:
manufacturing a first wafer, wherein the first wafer comprises a transistor, the transistor comprises a base layer and a target structure layer formed on one side of the base layer, a containing groove is formed on the first side of the base layer, and part or all of the target structure layer is positioned in the containing groove;
dividing the target structural layer into a normal region and a deviation region according to the height of the upper surface of the target structural layer relative to the first side, wherein the height of the deviation region is larger than or smaller than that of the normal region;
Correspondingly designing the volume of the accommodating groove corresponding to the deviation zone on the second wafer according to the deviation of the height of the deviation zone relative to the height of the normal zone on the first wafer;
and manufacturing the second wafer, wherein at least part of the target structure layer of the second wafer and part of the target structure layer of the first wafer are manufactured by adopting the same process conditions.
Optionally, the target structure layer is partially located in the accommodating groove, the target structure layer includes a buried portion and an overflow portion, the buried portion is buried in the base layer, the overflow portion is exposed on the first side, and a height of the target structure layer relative to the first side is equal to a thickness of the overflow portion.
Optionally, the accommodating groove is a rectangular groove or a convex hexagonal groove, the target structure layer comprises a silicon germanium body, the transistor comprises a gate, the gate is located on the first side of the substrate, a gap is formed between adjacent gates, and an overflow part of the silicon germanium body is located in the gap between the adjacent gates.
Optionally, the volume of the accommodating groove on the second wafer corresponding to the offset region includes:
Setting the thickness H_bulk1 of the overflow part corresponding to the deviation area when the second wafer is manufactured;
calculating the sectional area S_bulk1 of the overflow part in the extending direction of the gap between adjacent grids according to the thickness H_bulk1 of the overflow part;
and calculating the sectional area S_Trench1 of the accommodating groove on the second wafer in the gap extending direction between the adjacent grid electrodes according to the sectional area S_SiGe of the silicon germanium body in the gap extending direction between the adjacent grid electrodes and the sectional area S_bulk1 of the overflow part.
Optionally, the accommodating groove is a convex hexagonal groove, and the cross-sectional area s_bulk1 of the overflow portion is:
wherein OP is the width of the gap between adjacent grids, and alpha is the vertex angle of the overflow part.
Optionally, the sectional area s_tresh1 of the accommodating groove is:
S_Trench1＝S_SiGe-S_bulk1。
optionally, the sectional areas s_tresh1 and l_tresh1 of the accommodating groove conform to the following formula:
wherein l_tresh0 is the cross-sectional perimeter of the receiving groove corresponding to the offset region of the first wafer in the extending direction of the gap between the adjacent gates, and l_tresh1 is the cross-sectional perimeter of the receiving groove corresponding to the offset region of the second wafer in the extending direction of the gap between the adjacent gates.
Optionally, the gate includes a gate electrode and a side wall located between the gate electrode and the accommodating groove, the accommodating groove is a convex hexagonal groove, and a section perimeter l_perimeter of the accommodating groove in a gap extending direction between adjacent gates is calculated by the following perimeter calculation formula:
Wherein BCD is the lower side length of the cross section of the accommodating groove, S2G is the width of the side wall, T2G is the distance between the accommodating groove and the gate electrode in the width direction of the gap between adjacent gates, RCD is the depth of the accommodating groove, the accommodating groove comprises an upper isosceles trapezoid area far from the substrate and a lower isosceles trapezoid area close to the substrate, and SMD is the height of the upper isosceles trapezoid area;
and the section perimeter L_Trench0 and the section perimeter L_Trench1 are calculated by the perimeter calculation formula.
Optionally, the volume of the accommodating groove on the second wafer corresponding to the offset region includes:
calculating the section perimeter L_Trench1 of the accommodating groove according to the section area S_Trench1 of the accommodating groove, and calculating the section perimeter L_Trench0 of the accommodating groove of the first wafer;
taking the perimeter L_Trench1 and the perimeter L_Trench0 into a calculation formula of the sectional area S_Trench1 of the accommodating groove, and calculating the expected sectional area S_bulk1 of the overflow part;
when the expected sectional area S_bulk1 of the overflow part meets the design requirement, forming the accommodating groove according to the sectional area S_Trench1 of the accommodating groove, and when the expected sectional area S_bulk1 of the overflow part does not meet the design requirement, redesigning the thickness H_bulk1 of the overflow part and the corresponding sectional area S_bulk1 of the overflow part until the expected sectional area S_bulk1 of the overflow part meets the design requirement.
Optionally, the silicon germanium body includes a seed layer and an epitaxial layer, the seed layer is formed on an inner side wall of the accommodating groove, the epitaxial layer is formed in the seed layer and outside the accommodating groove, the epitaxial layer is formed by adopting an epitaxial growth process, and the epitaxial layer of the second wafer and the epitaxial layer of the first wafer are manufactured by adopting the same process conditions.
Optionally, the offset region includes a thin offset region, and the volume of the accommodating groove on the second wafer corresponding to the offset region includes:
and reducing the volume of the accommodating groove corresponding to the thinning region on the second wafer.
Optionally, the offset region includes a thickness offset region, and the volume of the accommodating groove corresponding to the offset region on the second wafer includes:
and increasing the volume of the accommodating groove corresponding to the thickness deviation area on the second wafer.
Optionally, the offset region includes a thicker region and a thinner region, and the forming process of the target structural layer includes chemical vapor deposition or physical vapor deposition; before the volume of the accommodation groove corresponding to the offset region on the second wafer of the corresponding design, the method comprises the steps of:
when at least the thinner region of the target structural layer of the first wafer is 0, the manufacturing method of the semiconductor device comprises the following steps:
Reducing the thickness of the target structure layer formed when the second wafer is manufactured, and dividing the normal region and the deviation region according to the target structure layer which is expected to be formed;
when at least the partial thickness region of the target structural layer of the first wafer is 0, the manufacturing method of the semiconductor device comprises the following steps:
and increasing the thickness of the target structure layer formed when the second wafer is manufactured, and dividing the normal region and the deviation region according to the target structure layer which is expected to be formed.
The application also provides a semiconductor device which is manufactured by adopting the manufacturing method of the semiconductor device.
The manufacturing method of the semiconductor device disclosed by the application and the semiconductor device have the following beneficial effects:
the manufacturing method of the semiconductor device comprises the following steps: manufacturing a first wafer, wherein the first wafer comprises a base layer and a target structure layer, a containing groove is formed in the first side of the base layer, and part or all of the target structure layer is located in the containing groove; dividing the target structure layer into a normal region and a deviation region according to the height of the upper surface of the target structure layer relative to the first side; correspondingly designing the volume of a containing groove of a corresponding deviation zone on the second wafer according to the height of the deviation zone of the target structural layer on the first wafer; and then the second wafer is manufactured by adopting the same process conditions. Because the target structure layers of the first wafer and the second wafer are manufactured by adopting the same process conditions, the volume distribution of the first wafer and the second wafer is approximately equal, and the height of the upper surface of the target structure layer can be controlled by increasing or reducing the volume of the accommodating groove on the second wafer, so that almost all areas of the target structure layer are in the value interval of the normal area, namely, the consistency of the film thickness of the target structure layer is improved, and the yield of the semiconductor device is further improved.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a flowchart of a method of fabricating a semiconductor device in an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a semiconductor device in an embodiment of the present application.
Fig. 3 is a schematic view of a target structure layer partition of a first wafer according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a semiconductor device having a P-type transistor in an embodiment of the present application.
Fig. 5 is a schematic diagram of forming a silicon germanium body in an embodiment of the present application.
Reference numerals illustrate:
100. A substrate; 101. a first side; 110. a receiving groove;
200. a target structural layer; 201. a normal zone; 202. a thinner region; 203. a thickness deviation area; 210. a seed layer; 220. an epitaxial layer; 221. a buried portion; 222. an overflow portion;
300. a gate insulating layer; 400. a gate electrode; 500. a side wall; 600. a cap; 700. a metal layer;
10. a wafer; 20. a reaction chamber.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The present application is further described in detail below with reference to the drawings and specific examples. It should be noted that the technical features of the embodiments of the present application described below may be combined with each other as long as they do not collide with each other. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present application and are not to be construed as limiting the present application.
Referring to fig. 1 and 2, the method for manufacturing a semiconductor device in this embodiment includes:
s100: a first wafer is fabricated, the first wafer including a transistor, the transistor including a base layer and a target structure layer 200 formed on a first side of the base layer, the first side 101 of the base layer being provided with a receiving groove 110, and the target structure layer 200 being partially or entirely located in the receiving groove 110.
The base layer may include the substrate 100, that is, the target structure layer 200 may be formed directly on the substrate 100; the base layer may further include a substrate 100 and one or more functional layers formed on the substrate 100, and the target structure layer 200 is formed on the functional layer on a side remote from the substrate 100. The target structure layer 200 may be formed by chemical vapor deposition, physical vapor deposition, or other processes, and the chemical vapor deposition includes epitaxial growth, and in this embodiment, the specific forming process of the target structure layer 200 is not limited.
S200: the target structural layer 200 is divided into a normal region 201 and a deviation region according to the height of the upper surface of the target structural layer 200 with respect to the first side 101, the height of the deviation region being greater than or less than the height of the normal region 201.
In this embodiment, the height of the target structure layer 200, the normal region 201, and the height of the offset region refer to the height of the first side 101. The upper surface of the target structure layer 200 may be higher or lower than the first side 101, and when the upper surface of the target structure layer 200 is higher than the first side 101, the height of the upper surface of the target structure layer 200 with respect to the first side 101 is a positive value; when the upper surface of the target structure layer 200 is lower than the first side 101, the height of the upper surface of the target structure layer 200 with respect to the first side 101 is negative. The normal region 201 is a value interval of the height of the upper surface of the target structure layer 200 relative to the first side 101 when the semiconductor device is qualified. On the first wafer, the area of the target structure layer 200 located in the normal area 201 is greater than or equal to 0.
S300: according to the deviation of the height of the deviated region on the first wafer relative to the height of the normal region 201, the volume of the accommodating groove 110 of the corresponding deviated region on the second wafer is correspondingly designed.
The first wafer is a wafer sample wafer or a wafer produced in the previous batch, and the second wafer is a wafer positive wafer or a wafer produced in the next batch. The height of the upper surface of the target structure layer 200 may be higher than the upper limit of the value interval or lower than the lower limit of the value interval, so as to correspondingly design the volume of the accommodating groove 110 of the corresponding deviation zone on the second wafer, i.e. increase or decrease the volume of the accommodating groove 110 of the corresponding deviation zone on the second wafer.
S400: and manufacturing a second wafer, wherein at least part of the target structure layer 200 of the second wafer and part of the target structure layer 200 of the first wafer are manufactured by adopting the same process conditions.
The same process conditions include the same film forming apparatus, the same process method, and the same process parameters, but are not limited thereto as long as the target structure layer 200 having the same morphology structure can be formed.
It should be noted that, the target structural layer 200 may be one structural layer formed by one process, or the target structural layer 200 may be two or more structural layers formed by two or more processes, at least a portion of the target structural layer 200 of the second wafer and a portion of the target structural layer 200 of the first wafer are manufactured by using the same process conditions, that is, when the target structural layer 200 includes two or more structural layers, at least one of the structural layers is manufactured by using the same process conditions.
In the conventional semiconductor device manufacturing process, the substrate 100 or the accommodating groove of one or more functional layers on the substrate 100 is limited to be a groove structure, and the manufacturing process of the target structural layer 200 is limited, so that the uniformity of the film thickness of the target structural layer 200 is poor, and the yield of the semiconductor device is reduced.
The manufacturing method of the semiconductor device in the embodiment comprises the following steps: manufacturing a first wafer, wherein the first wafer comprises a base layer and a target structure layer 200, the first side 101 of the base layer is provided with a containing groove 110, and the target structure layer 200 is partially or completely positioned in the containing groove 110; the target structural layer 200 is divided into a normal region 201 and a deviated region according to the height of the upper surface of the target structural layer 200 with respect to the first side 101; designing the volume of the accommodating groove 110 of the corresponding deviation zone on the second wafer according to the height of the deviation zone of the target structural layer 200 on the first wafer; and then the second wafer is manufactured by adopting the same process conditions. Because the target structure layer 200 of the first wafer and the second wafer are manufactured by adopting the same process conditions, the volume distributions of the first wafer and the second wafer are approximately equal, and the height of the upper surface of the target structure layer 200 can be controlled by increasing or decreasing the volume of the accommodating groove 110 of the corresponding deviation zone on the second wafer, so that almost all the areas of the target structure layer 200 are in the value zone of the normal zone 201, namely, the consistency of the film thickness of the target structure layer 200 is improved, and the yield of semiconductor devices is further improved.
In some embodiments, the target structural layer 200 is partially located within the receiving groove 110. The target structure layer 200 includes a buried portion 221 and an overflow portion 222, the buried portion 221 is buried in the base layer, the overflow portion 222 is exposed at the first side 101 of the base layer, and the height of the target structure layer 200 with respect to the first side 101 is equal to the thickness of the overflow portion 222.
The target structure layer 200 includes a buried portion 221 and an overflow portion 222, and the buried portion 221 fills the accommodating groove 110, and at this time, by increasing or decreasing the volume of the accommodating groove 110 on the second wafer, a more precise control of the thickness of the overflow portion 222 can be achieved by controlling the thickness of the overflow portion 222.
In some embodiments, the offset region includes an offset thin region 202, and the volume of the receiving groove 110 corresponding to the offset region on the second wafer includes:
the volume of the accommodating groove 110 corresponding to the thinned region 202 on the second wafer is reduced.
In addition, the offset region further includes an offset thick region 203, and the volume of the accommodating groove 110 corresponding to the offset region on the second wafer includes:
the volume of the accommodating groove 110 corresponding to the offset thick region 203 on the second wafer is increased.
Because the target structural layer 200 of the first wafer and the second wafer are manufactured by adopting the same process conditions, the volume distributions of the first wafer and the second wafer are approximately equal, and for the thin area 202 of the target structural layer 200, the volume of the accommodating groove 110 corresponding to the thin area 202 is reduced when the second wafer is manufactured, the volume of the buried part 221 of the corresponding thin area 202 of the target structural layer 200 can be reduced, and thus the thickness of the overflow part 222 of the corresponding thin area 202 of the target structural layer 200 is increased; for the thicker region 203 of the target structure layer 200, the volume of the accommodating groove 110 corresponding to the thinner region 202 is increased when the second wafer is manufactured, and the volume of the buried portion 221 of the corresponding thinner region 202 of the target structure layer 200 can be increased, so that the thickness of the overflow portion 222 of the corresponding thicker region 203 of the target structure layer 200 is reduced, the thickness uniformity of the overflow portion 222 is further improved, almost all the regions of the target structure layer 200 of the second wafer are in the value interval of the normal region 201, and the yield of the semiconductor device is further improved.
In some embodiments, when at least the thinner region 202 and the thicker region 203 of the target structure layer 200 are 0 and not 0, before the volumes of the accommodating grooves 110 corresponding to the deviated regions on the second wafer are correspondingly designed, the method for manufacturing the semiconductor device includes: the thickness of the target structure layer 200 formed when the second wafer is fabricated is reduced, and then the normal region 201 and the offset region are divided according to the target structure layer 200 that is expected to be formed.
At least the thinner region 202 of the target structure layer 200 of the first wafer is 0, i.e. the target structure layer 200 has a normal region 201 and a thicker region 203, or the target structure layer 200 is entirely thicker, at this time, the time for forming the target structure layer 200 when the second wafer is manufactured can be reduced, so as to reduce the thickness of the target structure layer 200, then the normal region 201 and the deviated region are divided according to the target structure layer 200 which is expected to be formed, and the thickness of the overflow portion 222 is adjusted by adjusting the volume of the accommodating groove 110, so that the thickness of the overflow portion 222 of the corresponding thicker region 203 of the target structure layer 200 is reduced, and almost all the regions of the target structure layer 200 are within the value interval of the normal region 201.
Accordingly, when the thickness deviation area 203 of the target structure layer 200 of at least the first wafer is 0 and the thickness deviation area 202 is not 0, the method for manufacturing the semiconductor device includes: the thickness of the target structure layer 200 formed when the second wafer is fabricated is increased.
At least the thickness deviation area 203 of the target structure layer 200 is 0, i.e. the target structure layer 200 has a normal area 201 and a thin area 202, or the target structure layer 200 is entirely thin, at this time, the time for forming the target structure layer 200 when the second wafer is manufactured can be increased to increase the thickness of the target structure layer 200, then the normal area 201 and the deviation area are divided according to the target structure layer 200 which is formed as expected, and the thickness of the overflow portion 222 is adjusted by adjusting the volume of the accommodating groove 110, so that the thickness of the overflow portion 222 of the target structure layer 200 corresponding to the thin area 202 is increased, and almost all the areas of the target structure layer 200 are within the value interval of the normal area 201.
It should be noted that, the thickness of the target structural layer 200 is mainly affected by the formation time of the target structural layer 200, and the thickness of the target structural layer 200 may be adjusted by increasing or decreasing the formation time of the target structural layer 200, but the present invention is not limited thereto, and the thickness of the target structural layer 200 may be adjusted by adjusting the temperature, the flow rate of the reaction gas, and the like, as the case may be.
By the means, the adjusting proportion of the accommodating groove 110 in the thicker region 203 and the thinner region 202 is reduced, so that the process difficulty of adjusting the size of the accommodating groove 110 is reduced. For example, when the dimensional change of the accommodating groove 110 is small, the difficulty of controlling the etching process forming the accommodating groove 110 is reduced.
For example, to achieve greater performance, semiconductor devices are evolving toward smaller feature sizes and higher element densities. Therefore, a gate of a Metal-Oxide-Semiconductor field effect transistor (MOS) becomes thinner and shorter than ever before, affecting the electrical performance of the Semiconductor device. At the same time, device speeds based on silicon processes have been approaching physical limits, limited by the inherent characteristics of silicon materials.
The Embedded silicon germanium (SiGe) technology is adopted to manufacture the P-type metal oxide semiconductor transistor (PMOS, P-type transistor for short), so that the carrier mobility of the P-type transistor can be enhanced, and the performances of the P-type transistor and the P-type transistor semiconductor device are greatly improved.
Referring to the embodiment shown in fig. 4, the P-type transistor semiconductor device is fabricated using embedded silicon germanium technology. The P-type transistor semiconductor device includes a channel in a substrate 100, a silicon germanium body (SiGe) as a source and drain, and a gate. The substrate 100 is a single crystal material. The gate electrode includes a gate insulating layer 300 and a gate electrode 400. Optionally, the gate further includes a sidewall 500. Optionally, the PMOS further includes a cap 600 and a metal layer 700. The gate electrode 400 is formed on the first side 101 of the substrate 100, the gate insulating layer 300 is formed between the gate electrode 400 and the substrate 100, and the sidewalls 500 are formed on both sides of the gate electrode 400. The substrate 100 on both sides of the gate electrode 400 and both sides of the sidewall 500 thereof is formed with accommodating grooves 110 serving as source and drain trenches.
Illustratively, the receiving groove 110 is created by anisotropic wet etching. Since the substrate 100 or the functional material layer on the substrate 100, i.e. the base layer, is made of single crystal material, and the etching rates of different crystal orientations are different under the same etchant, the source-drain trench with polygonal structure is generated. In the embodiment shown in fig. 4, the source-drain trenches are convex hexagonal trenches, known as sigma trenches, and the sige body is at least partially formed in the convex hexagonal trenches. In other embodiments, the source-drain trench may also be formed as a rectangular trench, i.e., the sidewall of the source-drain trench is perpendicular to the bottom surface, depending on the crystal orientation of the substrate 100.
The cap 600 is formed on the side of the silicon germanium body remote from the substrate 100 and the metal layer 700 is formed on the side of the cap 600 and gate electrode 400 remote from the substrate 100. Cap 600 is, for example, a highly doped monocrystalline silicon layer, the dopant including, for example, boron. The material of the metal layer 700 includes at least one of refractory metals such as nickel (Ni), tungsten (W), titanium (Ti), and the like, for example. Optionally, the metal layer 700 performs a silicidation reaction with the cap 600 and the gate electrode 400 made of polysilicon to form a metal silicide, thereby improving contact between the metal and the source and drain regions and the gate electrode. In other embodiments, the metal layer 700 and the target structure layer 200 are in direct contact and form a metal silicide via a silicidation reaction.
When the P-type transistor semiconductor device is fabricated, the gate insulating layer 300, the gate electrode 400 and the sidewall 500 may be formed on the substrate 100, then the convex hexagonal groove and the silicon germanium body may be formed, and finally the cap 600 and the metal layer 700 may be formed. The silicon germanium body may be formed by an epitaxial growth process.
Referring to fig. 5, a wafer 10 is placed in a reaction chamber 20 of an epitaxial growth apparatus, and a reaction gas is introduced from one side in a first direction and flows out from the other side in the first direction. The consistency of the thickness of the silicon germanium film is poor under the influence of various conditions such as reaction temperature, temperature field, gas flow rate, gas flow field and the like. In particular, the edge region of wafer 10, the sige bulk layer uniformity variation is more pronounced. Some epitaxial growth apparatus may introduce a small amount of reactant gas in a second direction that is perpendicular to the first direction, but introducing reactant gas in the second direction may only improve the uniformity of the sige film thickness in the edge region of the wafer 10 to some extent.
The applicant has found that when the height of the upper surface of the sige body is low, for example, the height after the epitaxy is lower than the first side 101 of the substrate 100, or the silicidation reaction of the metal layer 700 with the target structure layer 200 consumes more thickness of the target structure layer 200, so that the upper surface of the target structure layer 200 after the silicidation reaction is lower than the first side 101 of the substrate 100, or the silicidation reaction of the metal layer 700 with the cap 600 consumes more thickness of the target structure layer 200 after the entire cap 600 is consumed, so that when the upper surface of the target structure layer 200 after the silicidation reaction is lower than the first side 101 of the substrate 100, metal ions in the metal layer 700 are easily diffused into the channel between adjacent sige bodies, resulting in a reduced yield of P-type transistor semiconductor devices. In addition to the above-described upper surface of the target structure layer 200 being lower than the first side 101 of the substrate 100, insufficient thickness of the overflow 222 may also result in easy diffusion of metal ions in the metal layer 700 into the channel between adjacent sige bodies.
When the method for manufacturing a semiconductor device in this embodiment is used to manufacture a P-type transistor semiconductor device, the accommodating groove 110 is a convex hexagonal groove, and the target structure layer 200 includes a silicon germanium body. The transistor includes gates located on the first side 101 of the substrate 100, with gaps formed between adjacent gates, and the overflow 222 of the silicon germanium body located in the gaps between adjacent gates. The target structure layer 200 includes a silicon germanium body, and the lower limit of the value interval of the normal region 201 of the target structure layer 200 is greater than 0, i.e. the thickness of the overflow portion 222 is greater than 0. It can be understood that when the height of the upper surface of the target structure layer 200 relative to the first side 101 is outside the value range of the normal region 201, the deviation region is defined.
By adopting the manufacturing method of the semiconductor device in the embodiment to manufacture the silicon germanium body of the P-type transistor semiconductor device, the upper surface of the silicon germanium body is higher than the first side 101 of the substrate 100 to a uniform degree, the overflow part 222 is prevented from being too thin, metal ions in the metal layer 700 are prevented from being diffused into a channel between adjacent silicon germanium bodies, and the yield of the P-type transistor semiconductor device is improved.
Referring to fig. 2 and 4, the sige body includes a seed layer 210 and an epitaxial layer 220, the seed layer 210 is formed on an inner sidewall of the accommodating groove 110, the epitaxial layer 220 is formed in the seed layer 210 and outside the accommodating groove 110, the epitaxial layer 220 is formed by an epitaxial growth process, and at least the epitaxial layer 220 of the second wafer and the epitaxial layer 220 of the first wafer are manufactured by using the same process conditions. The overflow 222 is a portion of the epitaxial layer 220 outside the accommodating groove 110, and the buried portion 221 includes a portion of the epitaxial layer 220 inside the accommodating groove 110 and the seed layer 210.
Because the volume of the epitaxial layer 220 in the silicon germanium body is larger than the volume of the seed layer 210, the epitaxial layer 220 of the second wafer and the epitaxial layer 220 of the first wafer are manufactured by adopting the same process conditions, and the volume distribution of the silicon germanium body can be ensured to be approximately unchanged.
Referring to fig. 1 and 2, the volume of the accommodating groove 110 corresponding to the offset region on the second wafer is designed correspondingly, including:
setting the thickness H_bulk1 of the overflow part 222 corresponding to the deviation area when manufacturing the second wafer;
calculating the cross section S_bulk1 of the overflow part 222 in the extending direction of the gap between adjacent gates according to the thickness H_bulk1 of the overflow part;
the cross-sectional area s_trest1 of the accommodating groove 110 on the second wafer in the gap extension direction between the adjacent gates is calculated according to the cross-sectional area s_sige of the SiGe body in the gap extension direction between the adjacent gates and the cross-sectional area s_bulk1 of the overflow portion 222.
The silicon germanium body of the first wafer and the silicon germanium body of the second wafer are manufactured by adopting the same process conditions, and the volume distribution of the silicon germanium body of the first wafer and the silicon germanium body of the second wafer is approximately equal. By adjusting the volume of the accommodating groove 110 corresponding to the offset region, the thickness h_bulk1 of the overflow portion 222 can be adjusted to be within the value interval of the normal region 201. The sectional area s_trenc1 of the accommodating groove 110 is equal to the sectional area of the buried portion 221, and the sectional area s_trenc1 of the accommodating groove 110 can be calculated according to the sectional area s_bulk1 of the overflow portion 222. The length of the receiving groove 110 along the extending direction of the gap between the adjacent gates is almost constant, so the volume of the receiving groove 110 is determined by the sectional area of the receiving groove 110.
In this embodiment, the accommodating groove 110 is a convex hexagonal groove, and the accommodating groove 110 includes an upper isosceles trapezoid area far from the substrate 100 and a lower isosceles trapezoid area near the substrate 100. The cross-sectional area s_ring of the accommodating groove 110 has the following formula:
where OP is the width of the gap between the gates, i.e., the upper side length of the section of the accommodating groove 110, BCD is the lower side length of the section of the accommodating groove 110, S2G is the width of the side wall 500, T2G is the distance between the accommodating groove 110 and the gate electrode 400 in the width direction of the gap between adjacent gates, RCD is the depth of the accommodating groove 110, and SMD is the height of the isosceles trapezoid area on the upper portion.
The cross-sectional area s_Trench0 of the accommodating groove 110 of the first wafer may be calculated according to the above cross-sectional area calculation formula of the accommodating groove 110, or the dimensions such as the depth RCD of the accommodating groove 110 may be calculated according to the cross-sectional area s_Trench1 of the accommodating groove 110 of the second wafer, for the following reasons:
since the sidewall 500 is hardly etched during the etching of the accommodating groove 110, the width OP of the gap between adjacent gates is almost constant before and after the etching of the accommodating groove 110. The accommodating groove 110 is etched from the upper surface of the substrate 100 exposed by the adjacent gate electrode, for example, the etching method is anisotropic wet etching, and since the substrate 100 or the functional material layer on the substrate 100, that is, the base layer, is made of single crystal material, the substrate 100 with different crystal orientations is etched at the same etching agent with a great difference in etching rate by using a anisotropic wet etchant such as TMAH, so that the accommodating groove 110 with a polygonal structure is generated. In the embodiment shown in fig. 2, the accommodating recess 110 is a convex hexagon, and the inclination angles of the sides of the convex hexagon are all related to the crystal orientation, i.e., have a fixed inclination angle with respect to the surface of the substrate 100, and according to the above-mentioned geometric relationship, the lower side length BCD of the cross section of the accommodating recess 110, the width S2G of the sidewall 500, the distance T2G between the accommodating recess 110 and the gate electrode 400 in the width direction of the gap between adjacent gates, the depth RCD of the accommodating recess 110, and the height SMD of the upper isosceles trapezoid region are all related dimensions. The etching depth RCD of the accommodating groove 110 can be calculated according to the sectional area s_tresh1 of the accommodating groove 110 of the second wafer.
In summary, the thickness h_bulk1 of the overflow portion 222 when the second wafer is manufactured is set, the cross-sectional area s_trench1 of the accommodating groove 110 is calculated according to the thickness h_bulk1 of the overflow portion 222, the etching depth RCD of the accommodating groove 110 is further calculated, the accommodating groove 110 is etched according to the etching depth RCD of the accommodating groove 110, for example, the etching depth is controlled by controlling the etching time, the etchant concentration distribution, the regional etching and other conditions, the distribution range of the sige body in the value interval of the normal region 201 can be improved, and the yield of the P-type transistor semiconductor device is further improved.
In some embodiments, the cross-sectional area s_bulk1 of the overflow 222 is:
for the first wafer, OP is the width of the gap between adjacent gates and α is the top angle of the overflow 222. When at least the epitaxial layer 220 in the target structure layer 200 is prepared by an epitaxial process, the crystal orientation of the epitaxial layer 220 may be related to the crystal orientation of the substrate 100, and thus the angle α of the top angle of the epitaxial layer 220 is formed to be a fixed value related to the crystal orientation of the substrate 100. In other embodiments, the angle α of the top corner of the epitaxial layer 220 may be varied by a deposition process or other adjustment means, and the present invention is not particularly limited, but it will be appreciated that the same angle α should be produced under the same process conditions.
The sige body of the first wafer and the sige body of the second wafer are manufactured using the same process conditions, and the top angles of the overflow portions 222 of the two are approximately equal, so that the cross-sectional area s_bulk1 of the overflow portions 222 can be calculated according to the thickness h_bulk1 of the overflow portions 222 set when the second wafer is manufactured.
For example, the sectional area s_tresh1 of the accommodating groove 110 is:
S_Trench1＝S_SiGe-S_bulk1。
the sectional area S_Trench1 of the accommodating groove 110 is calculated by subtracting the sectional area S_bulk1 of the overflow portion 222 from the sectional area S_SiGe of the silicon germanium body, and the calculation mode is simpler.
In some embodiments, the cross-sectional areas s_tresh1, l_tresh1 of the receiving groove 110 of the second wafer conform to the following formula:
wherein, l_trest0 is the cross-sectional perimeter of the receiving groove corresponding to the offset region of the first wafer in the extending direction of the gap between the adjacent gates, and l_trest1 is the cross-sectional perimeter of the receiving groove corresponding to the offset region of the second wafer in the extending direction of the gap between the adjacent gates.
The formula of the relation among the section circumferences L_Trench, S_Trench and each side length and the values of S_SiGe, S_bulk1 and L_Trench0 are brought into the calculation formula of the section area S_Trench1 of the accommodating groove 110 of the second wafer, the etching depth RCD of the accommodating groove 110 can be calculated, the accommodating groove 110 is etched according to the etching depth RCD of the accommodating groove 110, the distribution range of the silicon germanium body in the value range of the normal region 201 can be improved, and the yield of the P-type transistor semiconductor device is further improved.
The perimeter of the cross section of the accommodating groove 110 will also change, and the perimeter of the cross section of the accommodating groove 110 will cause the overall speed of epitaxial growth, that is, the longer the perimeter of the cross section of the accommodating groove 110, the larger the epitaxial area of the target structure layer 200 in the accommodating groove 110 in the epitaxial process, and the larger the volume of the generated target structure layer 200 in the same epitaxial process time. Therefore, when calculating the sectional area s_tresh1 of the accommodating groove 110, the influence caused by the perimeter change of the accommodating groove 110 is considered to obtain the corrected s_tresh1, so that the accuracy of calculating the sectional area of the accommodating groove 110 can be further improved.
In some embodiments, the cross-sectional perimeter L Trench of the receiving groove 110 in the direction of the gap extension between adjacent gates is calculated by the following perimeter calculation formula:
the cross-section perimeter l_Trench0 and the cross-section perimeter l_Trench1 are both calculated by the perimeter calculation formula above.
Although the accommodating groove 110 is a convex hexagonal groove, the seed layer 210 is formed on the inner sidewall of the accommodating groove 110, and when the epitaxial layer 220 is grown, the seed layer 210 is grown from the inner side of the seed layer 210 to the outside of the accommodating groove 110, and since the seed layer 210 is not present at the opening of the accommodating groove 110, i.e., the upper side of the cross section, only the lower side and the side of the accommodating groove 110 affect the volume change rate of the epitaxial growth of the epitaxial layer 220. Therefore, the upper edge of the receiving groove 110 is not counted when the cross-sectional circumference of the receiving groove 110 is calculated, and the accuracy of calculating the cross-sectional area of the receiving groove 110 can be further improved.
In some embodiments, the volume of the accommodating groove 110 corresponding to the offset region on the second wafer is designed correspondingly, including:
calculating the section perimeter L_Trench1 of the accommodating groove 110 according to the section area S_Trench1 of the accommodating groove 110, and calculating the section perimeter L_Trench0 of the accommodating groove 110 of the first wafer;
taking the perimeter L_Trench1 and the perimeter L_Trench0 into a calculation formula of the cross section S_Trench1 of the accommodating groove 110, and calculating the cross section S_bulk1 of the expected overflow part;
when the sectional area S_bulk1 of the expected overflow part meets the design requirement, forming the accommodating groove 110 according to the sectional area S_Trench1 of the accommodating groove 110, and when the sectional area S_bulk1 of the expected overflow part does not meet the design requirement, redesigning the thickness H_bulk1 of the overflow part and the sectional area S_bulk1 of the corresponding overflow part until the sectional area S_bulk1 of the expected overflow part meets the design requirement.
In this embodiment, the cross-sectional circumferences l_tresh1 and l_tresh0 are brought into the calculation formula of the cross-sectional area s_tresh1 of the accommodating groove, the cross-sectional area s_bulk1 of the expected overflow portion is calculated, and then whether the cross-sectional area s_bulk1 of the expected overflow portion meets the design requirement is verified, so that it is simpler to obtain the cross-sectional area s_tresh1 of the accommodating groove 110 and the corresponding etching depth RCD.
In some embodiments, when the cross-sectional area of the accommodating groove 110 is adjusted according to the above method, the cross-sectional area of the accommodating groove 110 is adjusted by a smaller proportion, so that the height uniformity of the overflow portion is improved.
In other embodiments, the shape of the accommodating groove 110 is rectangular, and the present invention is equally applicable, and only the geometric formulas for calculating the area and the circumference are different. In this embodiment, what is needed to be changed in accordance with the etching principle is the depth of the trench and the width of the lateral opening. It can be appreciated that excessive differences in etching rates in different crystal orientations may result in negligible etching on the faces of the receiving grooves 110 corresponding to some crystal orientations.
The application also provides a semiconductor device, which is manufactured by the manufacturing method of the semiconductor device disclosed above.
In the manufacturing of the semiconductor device in this embodiment, a first wafer is manufactured first, the first wafer includes a base layer and a target structure layer 200, a first side 101 of the base layer is provided with a receiving groove 110, the target structure layer 200 is partially or completely located in the receiving groove 110, the target structure layer 200 is divided into a normal region 201 and an offset region according to the height of the upper surface of the target structure layer 200 relative to the first side 101, the volume of the receiving groove 110 corresponding to the offset region on a second wafer is designed according to the height of the offset region of the target structure layer 200 on the first wafer, and then the second wafer is manufactured by adopting the same process conditions. Because the target structure layer 200 of the first wafer and the second wafer are manufactured by adopting the same process conditions, the volume distributions of the first wafer and the second wafer are approximately equal, and the height of the upper surface of the target structure layer 200 can be controlled by increasing or decreasing the volume of the accommodating groove 110 on the second wafer, so that almost all areas of the target structure layer 200 are within the value interval of the normal area 201, namely, the consistency of the film thickness of the target structure layer 200 is improved, and the yield of semiconductor devices is further improved.
The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this application, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly, and may be, for example, fixedly attached, detachably attached, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In the description of the present specification, reference to the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present application have been shown and described, it should be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the embodiments by one of ordinary skill in the art within the scope of the application, and therefore all changes and modifications that fall within the spirit and scope of the invention as defined by the claims and the specification of the application are intended to be covered thereby.
Claims (14)
1. A method of fabricating a semiconductor device, comprising:
manufacturing a first wafer, wherein the first wafer comprises a transistor, the transistor comprises a base layer and a target structure layer formed on one side of the base layer, a containing groove is formed on the first side of the base layer, and part or all of the target structure layer is positioned in the containing groove;
dividing the target structural layer into a normal region and a deviation region according to the height of the upper surface of the target structural layer relative to the first side, wherein the height of the deviation region is larger than or smaller than that of the normal region;
correspondingly designing the volume of the accommodating groove corresponding to the deviation zone on the second wafer according to the deviation of the height of the deviation zone relative to the height of the normal zone on the first wafer;
And manufacturing the second wafer, wherein at least part of the target structure layer of the second wafer and part of the target structure layer of the first wafer are manufactured by adopting the same process conditions.
2. The method according to claim 1, wherein the target structure layer is partially located in the accommodating groove, the target structure layer includes a buried portion buried in the foundation layer and an overflow portion exposed from the first side, and a height of the target structure layer with respect to the first side is equal to a thickness of the overflow portion.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the accommodating groove is a rectangular groove or a convex hexagonal groove, the target structure layer comprises a silicon germanium body, the transistor comprises a gate, the gate is located on the first side, a gap is formed between adjacent gates, and an overflow portion of the silicon germanium body is located in the gap between adjacent gates.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the volume of the accommodating groove corresponding to the offset region on the second wafer of the corresponding design includes:
Setting the thickness H_bulk1 of the overflow part corresponding to the deviation area when the second wafer is manufactured;
calculating the sectional area S_bulk1 of the overflow part in the extending direction of the gap between adjacent grids according to the thickness H_bulk1 of the overflow part;
and calculating the sectional area S_Trench1 of the accommodating groove on the second wafer in the gap extending direction between the adjacent grid electrodes according to the sectional area S_SiGe of the silicon germanium body in the gap extending direction between the adjacent grid electrodes and the sectional area S_bulk1 of the overflow part.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the accommodating groove is a convex hexagonal groove, and the cross-sectional area s_bulk1 of the overflow portion is:
wherein OP is the width of the gap between adjacent grids, and alpha is the vertex angle of the overflow part.
6. The method of manufacturing a semiconductor device according to claim 4, wherein the sectional area s_trench1 of the accommodating groove is:
S_Trench1＝S_SiGe-S_bulk1。
7. the method of manufacturing a semiconductor device according to claim 4, wherein the cross-sectional areas s_tresh1, l_tresh1 of the accommodating groove satisfy the following formula:
wherein l_tresh0 is the cross-sectional perimeter of the receiving groove corresponding to the offset region of the first wafer in the extending direction of the gap between the adjacent gates, and l_tresh1 is the cross-sectional perimeter of the receiving groove corresponding to the offset region of the second wafer in the extending direction of the gap between the adjacent gates.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the gate electrode includes a gate electrode and a sidewall between the gate electrode and the accommodating groove, the accommodating groove is a convex hexagonal groove, and a cross-sectional perimeter l_trench of the accommodating groove in a gap extending direction between adjacent gate electrodes is calculated by a perimeter calculation formula:
wherein BCD is the lower side length of the cross section of the accommodating groove, S2G is the width of the side wall, T2G is the distance between the accommodating groove and the gate electrode in the width direction of the gap between adjacent gates, RCD is the depth of the accommodating groove, the accommodating groove comprises an upper isosceles trapezoid area far from the substrate and a lower isosceles trapezoid area close to the substrate, and SMD is the height of the upper isosceles trapezoid area;
and the section perimeter L_Trench0 and the section perimeter L_Trench1 are calculated by the perimeter calculation formula.
9. The method of manufacturing a semiconductor device according to claim 7, wherein the volume of the accommodating groove corresponding to the offset region on the second wafer of the corresponding design includes:
calculating the section perimeter L_Trench1 of the accommodating groove according to the section area S_Trench1 of the accommodating groove, and calculating the section perimeter L_Trench0 of the accommodating groove of the first wafer;
The perimeter L_Trench1 of the section and the perimeter L_Trench0 are brought into a calculation formula of the sectional area S_Trench1 of the accommodating groove,
calculating the expected sectional area S_bulk1 of the overflow part; when the expected sectional area S_bulk1 of the overflow part meets the design requirement, forming the accommodating groove according to the sectional area S_Trench1 of the accommodating groove, and when the expected sectional area S_bulk1 of the overflow part does not meet the design requirement, redesigning the thickness H_bulk1 of the overflow part and the corresponding sectional area S_bulk1 of the overflow part until the expected sectional area S_bulk1 of the overflow part meets the design requirement.
10. The method of manufacturing a semiconductor device according to claim 3, wherein the silicon germanium body comprises a seed layer and an epitaxial layer, the seed layer is formed on an inner side wall of the accommodating groove, the epitaxial layer is formed in the seed layer and outside the accommodating groove, the epitaxial layer is formed by an epitaxial growth process, and the epitaxial layer of the second wafer and the epitaxial layer of the first wafer are manufactured by the same process conditions.
11. The method of manufacturing a semiconductor device according to claim 1, wherein the offset region includes a thinned region, and the volume of the accommodating groove on the corresponding design second wafer corresponding to the offset region includes:
And reducing the volume of the accommodating groove corresponding to the thinning region on the second wafer.
12. The method according to claim 1 or 11, wherein the offset region includes a bias thick region, and the volume of the accommodating groove corresponding to the offset region on the second wafer of the corresponding design includes:
and increasing the volume of the accommodating groove corresponding to the thickness deviation area on the second wafer.
13. The method of manufacturing a semiconductor device according to claim 12, wherein the offset region includes a thicker region and a thinner region, and the formation process of the target structure layer includes chemical vapor deposition or physical vapor deposition; before the volume of the accommodation groove corresponding to the offset region on the second wafer of the corresponding design, the method comprises the steps of:
when at least the thinner region of the target structural layer of the first wafer is 0, the manufacturing method of the semiconductor device comprises the following steps:
reducing the thickness of the target structure layer formed when the second wafer is manufactured, and dividing the normal region and the deviation region according to the target structure layer which is expected to be formed;
when at least the partial thickness region of the target structural layer of the first wafer is 0, the manufacturing method of the semiconductor device comprises the following steps:
And increasing the thickness of the target structure layer formed when the second wafer is manufactured, and dividing the normal region and the deviation region according to the target structure layer which is expected to be formed.
14. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to any one of claims 1 to 13.
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| WO2023072180A1 (en) * | 2021-10-29 | 2023-05-04 | 北京北方华创微电子装备有限公司 | Semiconductor processing device and method for monitoring wafer position status |
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