CN117524278A - Dynamic random access memory compatible method, device and equipment - Google Patents

Dynamic random access memory compatible method, device and equipment Download PDF

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Publication number
CN117524278A
CN117524278A CN202311467495.4A CN202311467495A CN117524278A CN 117524278 A CN117524278 A CN 117524278A CN 202311467495 A CN202311467495 A CN 202311467495A CN 117524278 A CN117524278 A CN 117524278A
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China
Prior art keywords
random access
access memory
dynamic random
firmware
chip
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康克勤
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Ecarx Hubei Tech Co Ltd
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Ecarx Hubei Tech Co Ltd
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Priority to CN202311467495.4A priority Critical patent/CN117524278A/en
Publication of CN117524278A publication Critical patent/CN117524278A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device

Abstract

The application provides a method, a device and equipment for compatibility of a dynamic random access memory, which are used for reading a mark value of a target dynamic random access memory matched with a system-level chip from an electronic fuse module of the system-level chip, and then acquiring firmware of the target dynamic random access memory according to a corresponding relation between the mark value of the dynamic random access memory stored in a general flash memory and the firmware. Therefore, when a certain dynamic random access memory is needed, the firmware of the dynamic random access memory can be obtained from the general flash memory according to the mark value of the dynamic random access memory, the system firmware of the system-in-chip does not need to be changed in the whole process, the maintenance amount of the system firmware of the system-in-chip is reduced, and the compatibility, expansibility and flexibility of the dynamic random access memory are improved.

Description

Dynamic random access memory compatible method, device and equipment
Technical Field
The application relates to the field of vehicle software, in particular to a method, a device and equipment for compatibility of a dynamic random access memory.
Background
The DRAM (Dynamic Random Access Memory, DRAM) is a bridge for communication with a System On Chip (SOC) in an embedded System, and all programs are run in the DRAM. In the embedded platform, a dynamic random access memory and a system-level chip generally form a system core unit, and a complete embedded system is formed by hardware design and some peripheral devices.
At present, a set of system firmware of a system-level chip corresponds to one type of dynamic random access memory, when the system-level chip needs to be matched with a plurality of different types of dynamic random access memories, each different type of dynamic random access memory needs to be replaced, so that the outstanding problems of large maintenance amount and poor compatibility of the system firmware of the system-level chip are caused.
Disclosure of Invention
The application provides a method, a device and equipment for compatibility of a dynamic random access memory, which are used for reducing maintenance of system firmware of a system-in-chip and improving the compatibility of the dynamic random access memory.
In a first aspect, the present application provides a method for dynamic random access memory compatibility, including:
reading a mark value of a target dynamic random access memory matched with a system-level chip in an electronic fuse module of the system-level chip;
and acquiring the firmware of the target dynamic random access memory according to the corresponding relation between the mark value of the dynamic random access memory and the firmware stored in the universal flash memory, wherein the firmware of each dynamic random access memory matched with the system-in-chip is stored in the universal flash memory.
Optionally, the reading the flag value of the target dynamic random access memory in the electronic fuse module of the system-in-chip specifically includes:
reading the bit number of the address area in an electronic fuse module of the system-in-chip;
and determining the mark value of the target dynamic random access memory according to the bit number of the address area.
Optionally, before the flag value of the target dynamic random access memory is read in the electronic fuse module of the system-on-chip, the method further includes:
and writing the mark value of the target dynamic random access memory matched with the system-level chip into the address area of the electronic fuse module.
Optionally, before the obtaining the firmware of the target dynamic random access memory according to the correspondence between the flag value of the general flash memory and the dynamic random access memory firmware, the method further includes:
and packaging the firmware of each dynamic random access memory matched with the system-level chip into the whole package firmware of the system-level chip, and storing the whole package firmware of the system-level chip into the universal flash memory.
Optionally, writing the flag value of the target dynamic random access memory matched with the system-level chip into the address area of the electronic fuse module specifically includes:
writing the mark value of the target dynamic random access memory matched with the system-level chip into the address area of the electronic fuse module;
reading back the mark value of the address area of the electronic fuse module, and comparing the read-back mark value with the mark value to be read;
and if the mark values are inconsistent, writing the mark values to be written into the standby address area.
Optionally, the packaging the firmware of each dynamic random access memory matched with the system-level chip into the whole package firmware of the system-level chip, and storing the whole package firmware of the system-level chip into the general flash memory, which specifically includes:
receiving the time sequence configuration of each dynamic random access memory matched with the system-level chip;
analyzing the time sequence configuration to obtain parameters of each dynamic random access memory, and writing the parameters of each dynamic random access memory into corresponding firmware of the dynamic random access memory, wherein the parameters comprise controller parameters, physical layer protocol parameters and algorithm operation parameters;
packaging the firmware of each dynamic random access memory into the whole package firmware of the system-in-chip;
and downloading the whole package firmware of the system-in-chip to the universal flash memory.
Optionally, before the flag value of the target dynamic random access memory is read in the electronic fuse module of the system-on-chip, the method further includes:
after the system-level chip is electrified, a self-starting program in the system-level chip is operated;
loading a bootstrap program into a static random access memory within the system-in-chip;
running the bootstrap program to initialize the general flash memory;
the method for obtaining the firmware of the target dynamic random access memory according to the corresponding relation between the flag value of the dynamic random access memory stored in the general flash memory and the firmware specifically comprises the following steps:
and running the bootstrap program, acquiring the firmware of the target dynamic random access memory according to the corresponding relation between the mark value of the dynamic random access memory stored in the general flash memory and the firmware, and loading the firmware of the target dynamic random access memory into the static random access memory.
Optionally, after the loading the firmware of the target dynamic random access memory into the static random access memory, the method further includes:
analyzing the firmware of the target dynamic random access memory in the static random access memory, acquiring parameters of the target dynamic random access memory, and storing the parameters into a structural body variable corresponding to a controller of the static random access memory;
setting parameters in the structural body variables into a drive of the target dynamic random access memory, and storing capacity value marks of the target dynamic random access memory into the static random access memory;
and setting a memory starting address and an ending address of the target dynamic random access memory according to the capacity value mark, and setting the memory starting address and the ending address into a device tree of the kernel.
In a second aspect, the present application provides a dynamic random access memory compatible device, the device comprising:
the reading module is used for reading the mark value of the target dynamic random access memory in the electronic fuse module of the system-in-chip;
and the acquisition module is used for acquiring the firmware of the target dynamic random access memory according to the corresponding relation between the mark value of the dynamic random access memory and the firmware stored in the universal flash memory, wherein the firmware of each dynamic random access memory matched with the system-in-chip is stored in the universal flash memory.
In a third aspect, the present application provides an electronic device, comprising: a memory and a processor;
the memory is used for storing instructions; the processor is configured to invoke instructions in the memory to perform the dynamic random access memory compatible method of the first aspect and any of the possible designs of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium having stored therein computer instructions which, when executed by at least one processor of an electronic device, perform the dynamic random access memory compatible method of the first aspect and any one of the possible designs of the first aspect.
In a fifth aspect, the present application provides a computer program product comprising computer instructions which, when executed by at least one processor of an electronic device, perform the dynamic random access memory compatible method of the first aspect and any of the possible designs of the first aspect.
According to the dynamic random access memory compatible method, the mark value of the target dynamic random access memory matched with the system-level chip is read from the electronic fuse module of the system-level chip, and then the firmware of the target dynamic random access memory is obtained from the corresponding relation between the mark value of the dynamic random access memory stored in the general flash memory and the firmware. Therefore, when a certain dynamic random access memory is needed, the firmware of the dynamic random access memory can be obtained from the general flash memory according to the mark value of the dynamic random access memory, the system firmware of the system-in-chip does not need to be changed in the whole process, the maintenance amount of the system firmware of the system-in-chip is reduced, and the compatibility, expansibility and flexibility of the dynamic random access memory are improved.
Drawings
For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for DRAM compatibility according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a correspondence relationship of a DRAM according to an embodiment of the present application;
FIGS. 3-8 are schematic flow diagrams illustrating a method for DRAM compatibility according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a DRAM compatible device according to an embodiment of the present application;
fig. 10 is a schematic hardware structure of an electronic device according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
From the software level, it is understood that the DRAM is a bridge for communicating with the SOC in the embedded system, all the programs are run in the DRAM, and the SOC needs to operate and read and write data through the DRAM; from the hardware level, the DRAM is a generic term for different types of memory chips, and may be a DRAM chip containing different types of different capacities, such as an LPDDR5 type DRAM chip with 8GB capacity, and an LPDDR4 type DRAM chip with 4GB capacity. These DRAM chips are designed by hardware circuits to provide memory for the system in an embedded system.
In an embedded platform, a DRAM chip is usually matched with an SOC chip to form a system core unit, and a complete embedded system is formed by hardware design and some peripheral devices (such as a camera and a sensor).
When the substantial demands of stopping production of DRAM chips, project energy saving and cost reduction, scheme function expansion and the like are met, more proper DRAM chips are usually considered to be replaced, but each time a new DRAM chip is replaced, the DRAM driver needs to be re-adapted and the SOC system firmware needs to be updated, and the set of SOC system firmware can be understood to correspond to a specific type of DRAM chip.
When the SOC system needs to be adapted to a plurality of different types of DRAM chips, each different type of DRAM chip needs to be replaced, and corresponding SOC system firmware needs to be replaced, so that the outstanding problems of large maintenance amount and poor compatibility of the SOC system firmware are caused.
Aiming at the problems, the application provides a dynamic random access memory compatible method, which stores all the firmware of the dynamic random access memory which is needed to be matched by a system-level chip in a general flash memory, reads the mark value of the dynamic random access memory in an electronic fuse when a certain dynamic random access memory is needed to be matched, acquires the firmware of the dynamic random access memory according to the corresponding relation between the mark value stored in the general flash memory and the firmware of the dynamic random access memory, and reduces the maintenance amount of the system firmware of the system-level chip without changing the system firmware of the system-level chip in the whole process, thereby improving the compatibility of the dynamic random access memory.
The technical scheme of the present application is described in detail below with specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Fig. 1 is a flowchart of a method for dynamic random access memory compatibility according to an embodiment of the present application. As shown in fig. 1, with the electronic device as an execution body, the method of the present embodiment may include the following steps:
s101, reading a mark value of a target dynamic random access memory matched with the system-in-chip in an electronic fuse module of the system-in-chip.
An Electronic Fuse (EFUSE) module is a separate Flash unit inside a system-on-chip, and is a non-volatile memory device for storing information and protecting the chip, and is also a one-time programmable memory.
In this embodiment, the flag value of the target dynamic random access memory matched with the system-level chip is stored in the electronic fuse module of the system-level chip, and the flag values of all dynamic random access memories matched with the system-level chip can be stored in the electronic fuse module, but only the flag value of one dynamic random access memory matched with the system-level chip at present is written into the address area of the electronic fuse module, and as one system-level chip can only be matched with one model of dynamic random access memory at the same time. For example, the first item currently matches the system-on-chip model DRAM1, and the flag value of DRAM1 chip can be written into the address area of the electronic fuse module; and if the second item is matched with the system-level chip and is the type of the DRAM5 chip, writing the mark value of the corresponding DRAM5 chip into the address area of the electronic fuse module.
Therefore, when the firmware of a certain dynamic random access memory needs to be acquired, the flag value of the dynamic random access memory can be acquired in the electronic fuse module, that is, the flag value of the target dynamic random access memory can be read in the electronic fuse module. It will be appreciated that the target dynamic random access memory may be any of all dynamic random access memories that the system on chip needs to match.
By way of example, the electronic fuse module includes an address field (EFUSE ADDR), which is a register start address field of the electronic fuse module that is 2 bytes in size and can be used to store flag values for different dynamic random access memories that match the system on chip. The address area may be divided into a plurality of sections, and each section may store a flag value of a dynamic random access memory, for example, the address area may be divided into an address area 1 (EFUSE REGION 1), an address area 2 (EFUSE REGION 2), and an address area 3 (EFUSE REGION 3), as shown in fig. 2. The flag value of the dynamic random access memory matched with the system level chip is usually only required to be written into the address area 1, the bit number of the area can meet the number of the dynamic random access memories required to be compatible, for example, the bit number of the area is 4 bits, the compatibility of 16 numbers of dynamic random access memories can be met, it can be understood that the flag value of any dynamic random access memory matched with the system level chip can be written into the address area 1, and as shown in fig. 2, the flag value 1 of the DRAM1, the flag value 2 of the DRAM2 and the flag value 3 of the DRAM3 can be written into the address area 1. For the address area 2 and the address area 3, they can be used as fault tolerant areas or spare address areas, when the EFUSE tool is used to write the flag values of different dynamic random access memories, the EFUSE tool needs to be subjected to data configuration, if the flag values of the dynamic random access memories configured by the EFUSE tool are inconsistent with the flag values of the dynamic random access memories actually required to be configured, the address area 1 is burned, the flag values are inconsistent when the tool is used to read back, at this time, the new correct flag values can be written into the address area 2, and similarly, if the flag values written into the address area 2 are inconsistent with the read-back flag values, the correct flag values can be written into the address area 3 again. In practical application, the number of fault-tolerant processing times can be determined according to practical situations.
S102, acquiring the firmware of the target dynamic random access memory according to the corresponding relation between the flag value stored in the general flash memory and the firmware of the dynamic random access memory.
The general flash memory stores the firmware of each dynamic random access memory matched with the system-level chip.
The universal flash memory (Universal Flash Storage, UFS) is a storage device, and in this embodiment, the universal flash memory may store firmware of all dynamic random access memories matched by the system-in-chip, and correspondence between flag values and firmware of all dynamic random access memories matched by the system-in-chip.
Therefore, when the firmware of the target dynamic random access memory needs to be acquired, the firmware of the target dynamic random access memory can be acquired according to the mark value of the target dynamic random access memory and the corresponding relation between the mark value of the dynamic random access memory stored in the general flash memory and the firmware.
According to the method for compatibility of the dynamic random access memory, the corresponding relation between the mark values and the firmware of all dynamic random access memory chips matched by the system-in-chip is stored in the universal flash memory, when a certain dynamic random access memory is needed to be matched, the mark value of the dynamic random access memory is read from the electronic fuse module of the system-in-chip, then the corresponding firmware of the dynamic random access memory is obtained from the universal flash memory according to the mark value, and the system firmware of the system-in-chip does not need to be changed in the whole process, so that compatibility, expansibility and flexibility are improved.
Fig. 3 is a flowchart of a method for dynamic random access memory compatibility according to an embodiment of the present application. As shown in fig. 3, with the electronic device as an execution body, the method of the present embodiment may include the following steps:
s201, writing the mark value of the target dynamic random access memory matched with the system-in-chip into the address area of the electronic fuse module.
In this embodiment, before the flag value of the target dynamic random access memory is read in the electronic fuse module of the system-in-chip, the flag value of the target dynamic random access memory matched with the system-in-chip is written into the address area of the electronic fuse module.
For example, different dynamic random access memories set different bit numbers, and the bit number of the target dynamic random access memory can be written in the address area of the electronic fuse module, where the bit number of the target dynamic random access memory corresponds to a flag (KEY) value, and the flag value is an integer number.
In some embodiments, after writing the flag value of the target dynamic random access memory matched with the system-in-chip into the address area of the electronic fuse module, the flag value of the address area may be read back, the read-back flag value is compared with the flag value to be written, and if the read-back flag value is inconsistent, the flag value to be written is written into the spare address area. It should be noted that the flag value to be written may be understood as a flag value actually required to be written to the address area.
In practical application, writing the flag value of the target dynamic random access memory matched with the system-in-chip into the address area of the electronic fuse module includes: as shown in fig. 4, after the system is powered on, S211, the system-on-chip is set to enter a download (download) mode; s221, writing a mark value of a target dynamic random access memory matched with a system-level chip into an address area of the electronic fuse by using a special downloading tool; s231, using an Electronic Fuse (EFUSE) tool to read back the mark value of the address area, and comparing the read-back mark value with the mark value of the target dynamic random access memory; s241, if the target dynamic random access memory is inconsistent, the mark value of the target dynamic random access memory is written into the standby address area.
In step S221, a system on chip electronic fuse (SOC EFUSE) specific download tool is used to write the tag value of the target DRAM that the system on chip needs to match into the specified address area of the electronic fuse module. In step S231, the electronic fuse tool is used to read back the flag value of the address area to determine whether the flag value of the address area is correct, if so, the correct flag value is rewritten in the spare address area, and if so, it is determined that the writing of the flag value is completed in the address area.
S202, reading a mark value of the target dynamic random access memory in an electronic fuse module of the system-in-chip.
S203, obtaining the firmware of the target dynamic random access memory according to the corresponding relation between the flag value of the dynamic random access memory stored in the general flash memory and the firmware.
The system-level chip is used for storing the firmware of each dynamic random access memory matched with the system-level chip in the universal flash memory.
Step S202 is similar to the implementation of step S101 in the embodiment of fig. 1, and step S203 is similar to the implementation of step S102 in the embodiment of fig. 1, which is not described here again.
According to the method for compatibility of the dynamic random access memory, the mark value of the target dynamic random access memory matched with the system-level chip is written into the address area of the electronic fuse module, when a certain dynamic random access memory is needed to be matched, the mark value of the dynamic random access memory is read from the electronic fuse module of the system-level chip, and as the corresponding relation between the mark values of all dynamic random access memories matched with the system-level chip and the firmware is stored in the universal flash memory, the firmware of the corresponding dynamic random access memory can be obtained from the universal flash memory according to the mark value, and the system firmware of the system-level chip does not need to be changed in the whole process, so that compatibility, expansibility and flexibility are improved.
Fig. 5 shows a flowchart of a method for dynamic random access memory compatibility according to an embodiment of the present application. As shown in fig. 5, the method for compatibility of a dynamic random access memory provided in this embodiment includes:
s301, packaging the firmware of each dynamic random access memory matched with the system-level chip into the whole package firmware of the system-level chip, and storing the whole package firmware of the system-level chip into the general flash memory.
In this embodiment, the firmware of all the dynamic random access memories matched with the system-level chip is packaged into the whole package firmware of the system-level chip, and the whole package firmware of the system-level chip is stored into the general flash memory, so that the firmware of all the dynamic random access memories matched with the system-level chip is stored in the general flash memory.
In some embodiments, as shown in fig. 6, packaging the firmware of each dynamic random access memory matched by the system-on-chip into the whole package firmware of the system-on-chip, and storing the whole package firmware of the system-on-chip into the value general flash memory comprises: s311, receiving time sequence configuration of each dynamic random access memory matched with the system-in-chip; s321, analyzing time sequence configuration, obtaining parameters of each dynamic random access memory, and writing the parameters of each dynamic random access memory into corresponding firmware of the dynamic random access memory; s331, packaging the firmware of each dynamic random access memory into the whole package firmware of the system-in-chip; s341, downloading the whole package firmware of the system-in-chip to the general flash memory.
In step S311, the timing configuration of the dynamic random access memory includes various necessary parameters of the dynamic random access memory, so that the dynamic random access memory can operate normally and stably on the system-on-chip. In step S321, each of the dynamic random access memories has a different timing configuration, and the timing configuration of the dynamic random access memories includes controller parameters, physical layer Protocol (PHY) parameters, and algorithm operation parameters. For each dynamic random access memory, after each parameter of the dynamic random access memory is acquired, each parameter is sequentially written into firmware of the dynamic random access memory. In step S331, the loading order of the firmware of each dynamic random access memory may be sequentially specified in the editing system script of the system-in-chip, and the firmware of all dynamic random access memories matched with the system-in-chip may be packaged into the whole package firmware of the system-in-chip according to the loading order. In step S341, the whole package of firmware of the system on chip is downloaded to the general-purpose flash memory using the SOC specific download tool.
S302, reading a mark value of the target dynamic random access memory in an electronic fuse module of the system-in-chip.
S303, acquiring the firmware of the target dynamic random access memory according to the corresponding relation between the flag value of the dynamic random access memory stored in the general flash memory and the firmware.
Step S302 is similar to the implementation of step S101 in the embodiment of fig. 1, step S303 is similar to the implementation of step S102 in the embodiment of fig. 1, and the description of this embodiment is omitted here.
According to the method for compatibility of the dynamic random access memory, all the firmware of the dynamic random access memory matched with the system-level chip is stored in the universal flash memory, when the target dynamic random access memory is needed to be matched, the mark value of the target dynamic random access memory is obtained from the mark value stored by the electronic fuse module, then the corresponding firmware of the dynamic random access memory can be obtained from the universal flash memory according to the mark value, the system firmware of the system-level chip does not need to be changed in the whole process, and compatibility, expansibility and flexibility are improved.
Fig. 7 is a flowchart of a method for dynamic random access memory compatibility according to an embodiment of the present application. As shown in fig. 7, the method for compatibility of dynamic random access memory provided in this embodiment includes:
s401, writing the mark value of the target dynamic random access memory matched with the system-in-chip into the address area of the electronic fuse module.
S402, the firmware of each dynamic random access memory matched with the system-level chip is packaged into the whole package firmware of the system-level chip, and the whole package firmware of the system-level chip is stored into the general flash memory.
The system-level chip is used for storing the firmware of each dynamic random access memory matched with the system-level chip in the universal flash memory.
In the present embodiment, the steps S401 and S402 are not limited by the described operation sequence, and the steps S401 and S402 may be performed in other sequences or simultaneously.
S403, reading the mark value of the target dynamic random access memory in the electronic fuse module of the system-in-chip.
S404, obtaining the firmware of the target dynamic random access memory according to the corresponding relation between the flag value of the dynamic random access memory stored in the general flash memory and the firmware.
Step S302 is similar to the implementation of step S101 in the embodiment of fig. 1, step S303 is similar to the implementation of step S102 in the embodiment of fig. 1, and the description of this embodiment is omitted here.
According to the method for compatibility of the dynamic random access memory, the mark value of the target dynamic random access memory matched with the system-level chip is written into the address area of the electronic fuse module, the firmware of all the dynamic random access memories matched with the system-level chip is stored into the universal flash memory, when the target dynamic random access memory is needed to be matched, the mark value of the target dynamic random access memory is obtained from the electronic fuse module, then the firmware of the corresponding dynamic random access memory can be obtained from the universal flash memory according to the mark value, and the system firmware of the system-level chip does not need to be changed in the whole process, so that compatibility, expansibility and flexibility are improved.
Fig. 8 is a flowchart of a method for dynamic random access memory compatibility according to an embodiment of the present application. As shown in fig. 8, the method for compatibility of a dynamic random access memory provided in this embodiment includes:
s501, after the system-on-chip is powered on, a self-starting program in the system-on-chip is operated.
In this embodiment, after the system-on-chip is powered on, a bootstrapping program (Bootrom) cured in the system-on-chip is started to operate so as to operate the system-on-chip to an optimal initialization state.
S502, loading a bootstrap program into a static random access memory of a system-in-chip.
In this embodiment, after the start program is executed, a second stage boot program (BL 2) is loaded into a Static Random-Access Memory (SRAM), which is a Memory inside the system-in-chip, and the size of the Memory is limited, so that the Memory is only used by the resources necessary for the system-in-chip.
It should be noted that, after the system-on-chip is powered on or reset, the self-priming program may load the second stage boot program (BL 2) from the fixed location into the SRAM to initialize the SRAM.
S503, running a boot program to initialize the general flash memory.
In this embodiment, the second stage of boot program is executed, and the ufs related function may be called to perform a driving initialization to initialize the general flash memory, so as to prepare for loading the firmware of the dynamic random access memory in the general flash memory.
S504, reading a mark value of the target dynamic random access memory in an electronic fuse module of the system-in-chip.
In this embodiment, the boot program in the second stage can read the specified address of the register in the electronic fuse to obtain the flag value of the target dynamic random access memory. Illustratively, the flag value of the target dynamic random access memory is determined by the number of bits of the specified address of the register.
S505, the firmware of the target dynamic random access memory is obtained according to the corresponding relation between the mark value of the dynamic random access memory stored in the general flash memory and the firmware, and the firmware of the target dynamic random access memory is loaded into the static random access memory.
In this embodiment, the boot program in the second stage can load the firmware of the target dynamic random access memory from the general flash memory into the specified address in the static random access memory according to the flag value of the target dynamic random access memory.
S506, analyzing the firmware of the target dynamic random access memory in the static random access memory, obtaining the parameters of the target dynamic random access memory, and storing the parameters into the structural body variables corresponding to the controller of the static random access memory.
In this embodiment, the firmware of the target dynamic random access memory is parsed in the static random access memory, the corresponding parameter configuration is obtained, and the parameter is saved in the structure variable corresponding to the controller (SOC SRAM controller) of the static random access memory of the system-in-chip.
S507, setting parameters in the structural body variables into a drive of the target dynamic random access memory, and storing capacity value marks of the target dynamic random access memory into the static random access memory.
In this embodiment, the controller of the sram of the system-in-chip sets the parameters in the structure variables to the driving of the target dram, and saves the capacity value flag of the target dram to an address specified by the sram as a basis for the layout of the dram, and at this time, the driving initialization of the target dram is completed.
So far, the target dynamic random access memory operates normally and provides memory for the system-on-chip. After that, the system-level chip can continue to load other relevant firmware into the target dynamic random access memory, and the initialization of the system-level chip is completed.
S508, setting the initial address and the end address of the memory of the target dynamic random access memory according to the capacity value mark, and setting the initial address and the end address of the memory into the equipment tree of the kernel.
In this embodiment, uboot starts initialization, and since the capacity value flag of the target dynamic random access memory is set in the specified address in the static random access memory in the above steps, in this embodiment, the capacity value flag of the target dynamic random access memory may be taken out from the specified address of the static random access memory, the memory start address and the memory end address of the target dynamic random access memory are set according to the capacity value flag, and the start address and the end address are set in the device tree of the linux kernel through the fdt (flatted device tree, flat device tree) library operation function, so as to implement the kernel dynamic memory layout.
So far, the setting is completed, and the system level chip is normally started.
According to the method for compatibility of the dynamic random access memory, after the corresponding firmware of the dynamic random access memory is obtained from the universal flash memory according to the flag value, parameters in the firmware of the target dynamic random access memory can be loaded into a driver of the target dynamic random access memory to newly provide memory for a system level, and the memory starting address and the memory ending address of the target dynamic random access memory are set according to the capacity value flag of the target dynamic random access memory, so that the dynamic memory layout of a kernel is realized, and the normal starting of a system level chip is realized.
Fig. 9 is a schematic structural diagram of a dynamic random access memory compatible device according to an embodiment of the present application, as shown in fig. 9, a dynamic random access memory compatible device 10 according to the present embodiment is used to implement operations corresponding to an electronic apparatus in any of the above method embodiments, where the dynamic random access memory compatible device 10 according to the present embodiment includes:
a reading module 11, configured to read, in an electronic fuse module of a system-on-chip, a flag value of a target dynamic random access memory matched with the system-on-chip;
and the obtaining module 12 is configured to obtain the firmware of the target dynamic random access memory according to the correspondence between the flag value of the dynamic random access memory and the firmware stored in the general flash memory, where the firmware of each dynamic random access memory matched with the system-in-chip is stored in the general flash memory.
The embodiment of the present application provides the dynamic random access memory compatible device 10, which can execute the above embodiment of the method, and the specific implementation principle and technical effects of the embodiment of the method can be referred to the above embodiment, and the detailed description of the embodiment is omitted here.
Fig. 10 shows a schematic hardware structure of an electronic device according to an embodiment of the present application. As shown in fig. 10, the electronic device 20, configured to implement operations corresponding to the electronic device in any of the above method embodiments, the electronic device 20 of this embodiment may include: a memory 21, a processor 22 and a communication interface 23.
A memory 21 for storing computer instructions. The Memory 21 may include a high-speed random access Memory (Random Access Memory, RAM), and may further include a Non-Volatile Memory (NVM), such as at least one magnetic disk Memory, and may also be a U-disk, a removable hard disk, a read-only Memory, a magnetic disk, or an optical disk.
A processor 22 for executing the computer instructions stored in the memory to implement the dynamic random access memory compatible method of the above embodiment. Reference may be made in particular to the relevant description of the embodiments of the method described above. The processor 22 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.
Alternatively, the memory 21 may be separate or integrated with the processor 22.
The communication interface 23 may be connected to the processor 22. The processor 22 may control the communication interface 23 to perform the functions of receiving and transmitting signals.
The electronic device provided in this embodiment may be used to execute the above-mentioned method for compatibility with a dynamic random access memory, and its implementation manner and technical effects are similar, and this embodiment is not repeated here.
The present application also provides a computer readable storage medium having stored therein computer instructions which, when executed by a processor, are adapted to carry out the methods provided by the various embodiments described above.
The present application also provides a computer program product comprising computer instructions stored in a computer readable storage medium. The computer instructions may be read from a computer-readable storage medium by at least one processor of the device, and executed by the at least one processor, cause the device to implement the methods provided by the various embodiments described above.
The embodiment of the application also provides a chip, which comprises a memory and a processor, wherein the memory is used for storing computer instructions, and the processor is used for calling and running the computer instructions from the memory, so that a device provided with the chip executes the method in various possible implementation manners.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents. Such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A method of dynamic random access memory compatibility, the method comprising:
reading a mark value of a target dynamic random access memory matched with a system-level chip in an electronic fuse module of the system-level chip;
and acquiring the firmware of the target dynamic random access memory according to the corresponding relation between the mark value of the dynamic random access memory and the firmware stored in the universal flash memory, wherein the firmware of each dynamic random access memory matched with the system-in-chip is stored in the universal flash memory.
2. The method according to claim 1, wherein the reading the flag value of the target dynamic random access memory in the electronic fuse module of the system-on-chip specifically comprises:
reading the bit number of the address area in an electronic fuse module of the system-in-chip;
and determining the mark value of the target dynamic random access memory according to the bit number of the address area.
3. The method of claim 1, wherein prior to reading the flag value of the target dynamic random access memory in the electronic fuse module of the system-on-chip, the method further comprises:
and writing the mark value of the target dynamic random access memory matched with the system-level chip into the address area of the electronic fuse module.
4. A method according to any one of claims 1-3, wherein before the obtaining the firmware of the target dynamic random access memory according to the correspondence between the flag value of the general flash memory and the dynamic random access memory firmware, the method further comprises:
and packaging the firmware of each dynamic random access memory matched with the system-level chip into the whole package firmware of the system-level chip, and storing the whole package firmware of the system-level chip into the universal flash memory.
5. The method of claim 3, wherein writing the flag value of the target dynamic random access memory matched by the system-on-chip to the address area of the electronic fuse module specifically comprises:
writing the mark value of the target dynamic random access memory matched with the system-level chip into the address area of the electronic fuse module;
reading back the mark value of the address area of the electronic fuse module, and comparing the read-back mark value with the mark value to be written;
and if the mark values are inconsistent, writing the mark values to be written into the standby address area.
6. The method according to claim 4, wherein the packaging the firmware of each dynamic random access memory matched with the system-on-chip into the whole package firmware of the system-on-chip, and storing the whole package firmware of the system-on-chip into the general-purpose flash memory, specifically comprises:
receiving the time sequence configuration of each dynamic random access memory matched with the system-level chip;
analyzing the time sequence configuration to obtain parameters of each dynamic random access memory, and writing the parameters of each dynamic random access memory into corresponding firmware of the dynamic random access memory, wherein the parameters comprise controller parameters, physical layer protocol parameters and algorithm operation parameters;
packaging the firmware of each dynamic random access memory into the whole package firmware of the system-in-chip;
and downloading the whole package firmware of the system-in-chip to the universal flash memory.
7. A method according to any one of claims 1-3, wherein before reading the flag value of the target dynamic random access memory in the electronic fuse module of the system-on-chip, the method further comprises:
after the system-level chip is electrified, a self-starting program in the system-level chip is operated;
loading a bootstrap program into a static random access memory within the system-in-chip;
running the bootstrap program to initialize the general flash memory;
the method for obtaining the firmware of the target dynamic random access memory according to the corresponding relation between the flag value of the dynamic random access memory stored in the general flash memory and the firmware specifically comprises the following steps:
and running the bootstrap program, acquiring the firmware of the target dynamic random access memory according to the corresponding relation between the mark value of the dynamic random access memory stored in the general flash memory and the firmware, and loading the firmware of the target dynamic random access memory into the static random access memory.
8. The method of claim 7, wherein after loading the firmware of the target dynamic random access memory into the static random access memory, the method further comprises:
analyzing the firmware of the target dynamic random access memory in the static random access memory, acquiring parameters of the target dynamic random access memory, and storing the parameters into a structural body variable corresponding to a controller of the static random access memory;
setting parameters in the structural body variables into a drive of the target dynamic random access memory, and storing capacity value marks of the target dynamic random access memory into the static random access memory;
and setting a memory starting address and an ending address of the target dynamic random access memory according to the capacity value mark, and setting the memory starting address and the ending address into a device tree of the kernel.
9. A dynamic random access memory compatible device, the device comprising:
the reading module is used for reading the mark value of the target dynamic random access memory in the electronic fuse module of the system-in-chip;
and the acquisition module is used for acquiring the firmware of the target dynamic random access memory according to the corresponding relation between the mark value of the dynamic random access memory and the firmware stored in the universal flash memory, wherein the firmware of each dynamic random access memory matched with the system-in-chip is stored in the universal flash memory.
10. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
the processor executes the computer-executable instructions stored by the memory to implement the dynamic random access memory compatible method of any one of claims 1 to 8.
CN202311467495.4A 2023-11-03 2023-11-03 Dynamic random access memory compatible method, device and equipment Pending CN117524278A (en)

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