CN117497655A - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDF

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CN117497655A
CN117497655A CN202311787246.3A CN202311787246A CN117497655A CN 117497655 A CN117497655 A CN 117497655A CN 202311787246 A CN202311787246 A CN 202311787246A CN 117497655 A CN117497655 A CN 117497655A
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emitting diode
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CN117497655B (en
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印从飞
张彩霞
刘春杨
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/67248—Temperature monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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Abstract

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The multi-quantum well layer is of a periodic structure, the period number is 6-10, and each period comprises a secondary well layer, a secondary barrier layer, a quantum well layer, a composite cover layer and a quantum barrier layer which are sequentially stacked; the sub-well layer includes In laminated In sequence a Ga 1‑a An N layer and an InN layer, the sub barrier layer comprising a GaN layer, the quantum well layer comprising In b Ga 1‑b The composite cover layer comprises a first GaN layer, a second GaN layer and a third GaN layer which are sequentially stacked, and the quantum barrier layer comprises a Si doped GaN layer. By implementing the invention, the luminous efficiency and antistatic capability of the light-emitting diode can be improved, and the working voltage can be reduced.

Description

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
GaN-based materials are semiconductor materials with direct band gaps, and the energy gap can be changed between 0.7eV (InN) and 6.2eV (AlN) by adjusting the duty ratio of series alloy compounds, so that the light emitting range can cover partial ultraviolet, infrared and whole visible light wave bands; therefore, gaN-based materials are ideal materials for preparing semiconductor light emitting devices. Compared with the traditional light source, the GaN-based LED has the advantages of high light efficiency, long service life, easy bandwidth adjustment, quick response and the like.
Currently, the mainstream GaN-based LEDs are based on a Multiple Quantum Well (MQW) layer structure formed by periodically overlapping InGaN quantum well layers and GaN quantum barrier layers; the desired emission wavelength is adjusted by varying the In composition content In the well. However, the InGaN quantum well layer with high In composition is usually realized by low temperature growth, which causes NH 3 The cracking efficiency is low, the atom mobility is reduced, the crystal quality is poor, and then a non-radiative recombination center formed by more defects is formed in an active region, so that the internal quantum efficiency of a corresponding green light LED is reduced; and, there is a large polarized electric field In the InGaN/GaN active region with high In composition, which can cause energy band bending, so that electrons and holes In the well move In opposite directions, resulting In spatial separation of electrons and holes and reduced overlap of wave functions, and finally resulting In reduced light efficiency and red shift of wavelength.
Based on the above problems, some researchers have adopted to insert a low-temperature GaN cap layer between the InGaN quantum well layer and the GaN quantum barrier layer to protect the crystal quality of the low-temperature InGaN quantum well layer, and the improvement of the crystal quality of the multiple quantum well layer is limited due to the simple structure; in addition, some scholars use r-plane sapphire substrates or m-plane SiC substrates for growing nonpolar GaN materials to reduce polarization electric fields and stresses, however, the technology is not mature enough, and has not been applied to the industrialization process.
Disclosure of Invention
The invention aims to solve the technical problem of providing a light-emitting diode epitaxial wafer and a preparation method thereof, which can improve the light-emitting efficiency of a light-emitting diode, improve the antistatic capability and reduce the working voltage.
The invention also solves the technical problem of providing a light-emitting diode which has high luminous efficiency, high antistatic capability and low working voltage.
In order to solve the problems, the invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a multiple quantum well layer, an electron blocking layer, a P-type GaN layer and an ohmic contact layer which are sequentially arranged on the substrate, wherein the multiple quantum well layer is of a periodic structure, the number of periods is 6-10, and each period comprises a secondary well layer, a secondary barrier layer, a quantum well layer, a composite cover layer and a quantum barrier layer which are sequentially laminated;
the sub-well layer comprises In laminated In sequence a Ga 1-a An N layer and an InN layer, the sub barrier layer comprising a GaN layer, the quantum well layer comprising In b Ga 1-b The composite cover layer comprises a first GaN layer, a second GaN layer and a third GaN layer which are sequentially stacked, and the quantum barrier layer comprises a Si doped GaN layer;
wherein a < b;
the growth temperature of the first GaN layer is less than or equal to the growth temperature of the second GaN layer and less than the growth temperature of the third GaN layer;
the growth pressure of the first GaN layer is less than that of the second GaN layer and less than or equal to that of the third GaN layer;
the growth temperature of the auxiliary barrier layer is greater than the growth temperature of the auxiliary well layer, and the growth temperature of the auxiliary barrier layer is greater than the growth temperature of the quantum well layer.
As a modification of the above scheme, 0.18 < a < 0.25,0.2 < b < 0.3.
As an improvement of the scheme, the growth temperature of the auxiliary well layer is 700-750 ℃, the growth temperature of the auxiliary barrier layer is 750-800 ℃, the growth temperature of the quantum well layer is 700-750 ℃, the growth temperature of the first GaN layer is 700-730 ℃, the growth temperature of the second GaN layer is 700-730 ℃, and the growth temperature of the third GaN layer is 760-800 ℃.
As an improvement of the scheme, the growth pressure of the first GaN layer is 100-150 torr, the growth pressure of the second GaN layer is 150-200 torr, and the growth pressure of the third GaN layer is 150-200 torr.
As an improvement of the scheme, the thickness of the auxiliary well layer is less than or equal to 1nm.
As an improvement of the scheme, the thickness ratio of the auxiliary well layer to the quantum well layer is 0.2-0.4.
As an improvement of the above scheme, the In a Ga 1-a The thickness of the N layer is 0.1-0.7 nm, the thickness of the InN layer is 0.05-0.25 nm, the thickness of the GaN layer is 0.05-2 nm, and the In b Ga 1-b The thickness of the N layer is 1-5 nm, the thickness of the first GaN layer is 0.5-1 nm, the thickness of the second GaN layer is 0.5-1 nm, the thickness of the third GaN layer is 0.5-1 nm, and the thickness of the Si doped GaN layer is 10-15 nm.
Correspondingly, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate, and sequentially growing a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a multiple quantum well layer, an electron blocking layer, a P-type GaN layer and an ohmic contact layer on the substrate, wherein the multiple quantum well layer is of a periodic structure, the number of periods is 6-10, and each period comprises a secondary well layer, a secondary barrier layer, a quantum well layer, a composite cover layer and a quantum barrier layer which are sequentially laminated;
the sub-well layer comprises In laminated In sequence a Ga 1-a An N layer and an InN layer, the sub barrier layer comprising a GaN layer, the quantum well layer comprising In b Ga 1-b The composite cover layer comprises a first GaN layer, a second GaN layer and a third GaN layer which are sequentially stacked, and the quantum barrier layer comprises a Si doped GaN layer;
wherein a < b;
the growth temperature of the first GaN layer is less than or equal to the growth temperature of the second GaN layer and less than the growth temperature of the third GaN layer;
the growth pressure of the first GaN layer is less than that of the second GaN layer and less than or equal to that of the third GaN layer;
the growth temperature of the auxiliary barrier layer is greater than the growth temperature of the auxiliary well layer, and the growth temperature of the auxiliary barrier layer is greater than the growth temperature of the quantum well layer.
As an improvement of the scheme, the growth temperature of the quantum barrier layer is 850-900 ℃;
the growth pressure of the auxiliary well layer is 100-200 torr, the growth pressure of the auxiliary barrier layer is 100-200 torr, the growth pressure of the quantum well layer is 100-200 torr, and the growth pressure of the quantum barrier layer is 100-150 torr.
Correspondingly, the invention also discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
1. in the light-emitting diode epitaxial wafer, the multiple quantum well layer comprises a secondary well layer, a secondary barrier layer, a quantum well layer, a composite cover layer and a quantum barrier layer which are periodically and sequentially laminated.
Firstly, an indium gallium nitride quantum dot layer in a multi-quantum well region is formed through the introduction of a sub-well layer and a sub-barrier layer, so that mismatch stress between part of the quantum well layer and the quantum barrier layer can be counteracted, a polarization electric field is reduced, the space coincidence ratio of electrons and holes in the multi-quantum well region is improved, the luminous efficiency is improved, the working voltage is reduced, and the antistatic capability is improved; on the other hand, the formation of local states in the multi-quantum well region is facilitated, the radiation recombination efficiency is improved, and the luminous efficiency is improved;
secondly, a composite cover layer grown at variable temperature and pressure is introduced, so that the quantum well layer with high In component can be protected, the In component segregation of the quantum well layer caused by the high temperature of the quantum barrier layer is prevented, the crystal quality of the quantum well layer is improved, the interface definition of the well barrier is also improved, the crystal quality of the quantum barrier layer is improved, the luminous efficiency is further improved, the working voltage is reduced, and the antistatic capability is improved;
and finally, the growth temperature of the auxiliary barrier layer is larger than that of the auxiliary well layer, the growth temperature of the auxiliary barrier layer is larger than that of the quantum well layer, the auxiliary barrier layer adopts a slightly higher growth temperature, the In component segregation of the auxiliary well layer and the quantum well layer is avoided, the crystal quality of the auxiliary barrier layer is ensured, and the luminous efficiency is improved.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a multi-quantum well layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a sub-well layer according to an embodiment of the present invention;
FIG. 4 is a schematic illustration of the structure of a composite overlay according to an embodiment of the invention;
fig. 5 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1 to 4, the invention discloses a light emitting diode epitaxial wafer, which comprises a substrate 1, and a buffer layer 2, an intrinsic GaN layer 3, an N-type GaN layer 4, a stress release layer 5, a multiple quantum well layer 6, an electron blocking layer 7, a P-type GaN layer 8 and an ohmic contact layer 9 which are sequentially arranged on the substrate 1. The multiple quantum well layer 6 has a periodic structure, and the number of periods is 6 to 10, and each period includes a sub-well layer 61, a sub-barrier layer 62, a quantum well layer 63, a composite cap layer 64, and a quantum barrier layer 65, which are sequentially stacked.
Wherein the sub-well layer 61 includes In laminated In order a Ga 1-a An N layer 611 and an InN layer 612, a sub barrier layer 62 comprising a GaN layer, and a quantum well layer 63 comprising In b Ga 1-b The N layer, the composite cap layer 64 includes a first GaN layer 641, a second GaN layer 642, and a third GaN layer 643 sequentially stacked, and the quantum barrier layer 65 includes a Si doped GaN layer. Wherein a < b; the growth temperature of the first GaN layer 641 is less than or equal to the growth temperature of the second GaN layer 642 < the growth temperature of the third GaN layer 643; the growth pressure of the first GaN layer 641 < the growth pressure of the second GaN layer 642 is less than or equal to the growth pressure of the third GaN layer 643; auxiliary barrier layer 62The growth temperature > the growth temperature of the sub-well layer 61, and the growth temperature of the sub-barrier layer 62 > the growth temperature of the quantum well layer 63.
Firstly, the indium gallium nitride quantum dot layer in the multi-quantum well region is formed by introducing the auxiliary well layer 61 and the auxiliary barrier layer 62, so that mismatch stress between part of the quantum well layer 63 and the quantum barrier layer 65 can be counteracted, a polarization electric field is reduced, the space coincidence ratio of electrons and holes in the multi-quantum well region is improved, the luminous efficiency is improved, the working voltage is reduced, and the antistatic capability is improved; on the other hand, the formation of local states in the multi-quantum well region is facilitated, the radiation recombination efficiency is improved, and the luminous efficiency is improved;
secondly, the composite cover layer 64 grown at variable temperature and pressure is introduced, so that the quantum well layer 63 with high In component can be protected, the In component segregation of the quantum well layer 63 caused by the high temperature of the quantum barrier layer 65 is prevented, the crystal quality of the quantum well layer 63 is improved, the interface definition of the well barrier is improved, the crystal quality of the quantum barrier layer 65 is improved, the luminous efficiency is further improved, the working voltage is reduced, and the antistatic capability is improved;
finally, the growth temperature of the auxiliary barrier layer 62 is greater than that of the auxiliary well layer 61, the growth temperature of the auxiliary barrier layer 62 is greater than that of the quantum well layer 63, the auxiliary barrier layer 62 adopts a slightly higher growth temperature, the In component segregation of the auxiliary well layer 61 and the quantum well layer 63 is avoided, the crystal quality of the auxiliary barrier layer 62 is ensured, and the luminous efficiency is improved.
Specifically, a is more than 0.15 and less than 0.28,0.18 and b is less than 0.35, the In component In the auxiliary well layer 61 is relatively low, the In component In the quantum well layer 63 is relatively high, and a is less than b, so that the auxiliary well layer 61 and the quantum well layer 63 are prevented from overlapping In light emission. Illustratively, a is 0.17, 0.2, 0.22, or 0.25, but is not limited thereto. Illustratively, b is 0.2, 0.22, 0.25, 0.3, or 0.32, but is not limited thereto. Preferably, 0.18 < a < 0.25,0.2 < b < 0.3.
Specifically, the growth temperature of the sub-well layer 61 is 680 ℃ to 770 ℃, and is exemplified by 700 ℃, 720 ℃, 740 ℃, or 760 ℃, but is not limited thereto. Preferably, the growth temperature of the sub-well layer 61 is 700 ℃ to 750 ℃.
Specifically, the growth temperature of the secondary barrier layer 62 is 730 ℃ to 820 ℃, and is exemplified by, but not limited to, 750 ℃, 770 ℃, 780 ℃, or 800 ℃. Preferably, the growth temperature of the secondary barrier layer 62 is 750 ℃ to 800 ℃.
Specifically, the growth temperature of the quantum well layer 63 is 680 ℃ to 770 ℃, and is exemplified by 700 ℃, 720 ℃, 740 ℃, or 760 ℃, but not limited thereto. Preferably, the growth temperature of the quantum well layer 63 is 700 ℃ to 750 ℃.
Specifically, the growth temperature of the first GaN layer 641 is 680 to 750 ℃, and is exemplified by 700 ℃, 710 ℃, 720 ℃, or 740 ℃, but not limited thereto. Preferably, the growth temperature of the first GaN layer 641 is 700-730 ℃.
Specifically, the growth pressure of the first GaN layer 641 is 100torr to 150torr, and is exemplified by 110torr, 120torr, 130torr or 140torr, but not limited thereto.
Specifically, the growth temperature of the second GaN layer 642 is 680 to 750 ℃, and is exemplified by 700 ℃, 710 ℃, 720 ℃, or 740 ℃, but not limited thereto. Preferably, the growth temperature of the second GaN layer 642 is 700 ℃ to 730 ℃.
Specifically, the growth pressure of the second GaN layer 642 is 150torr to 200torr, and exemplary is 160torr, 170torr, 180torr or 190torr, but is not limited thereto.
Specifically, the growth temperature of the third GaN layer 643 is 740 ℃ to 820 ℃, and is exemplified by 760 ℃, 780 ℃, 800 ℃ or 810 ℃, but not limited thereto. Preferably, the growth temperature of the third GaN layer 643 is 760 ℃ to 800 ℃.
Specifically, the growth pressure of the third GaN layer 643 is 150torr to 200torr, and exemplary is 160torr, 170torr, 180torr or 190torr, but is not limited thereto.
Specifically, the thickness of the sub-well layer 61 is 1.5nm or less. The thickness of the sub-well layer 61 is thin, and an In cluster phenomenon is avoided. Preferably, the thickness of the sub-well layer 61 is 1nm or less. Further preferably, the ratio of the thickness of the sub-well layer 61 to the quantum well layer 63 is 0.2 to 0.4, and the light emission efficiency is further improved.
Specifically, in a Ga 1-a The thickness of the N layer 611 is 0.1nm to 0.9nm, and exemplary is 0.2nm, 0.4nm, or 0.6nm, but is not limited thereto. Preferably, in a Ga 1-a The thickness of the N layer 611 is 0.1nm to 0.7nm.
Specifically, the InN layer 612 has a thickness of 0.05nm to 0.5nm, and exemplary thicknesses are, but not limited to, 0.1nm, 0.12nm, 0.14nm, 0.18nm, or 0.2 nm. Preferably, the InN layer 612 has a thickness of 0.05nm to 0.25nm.
Specifically, the thickness of the GaN layer is 0.05nm to 2.5nm, and if the thickness is less than 0.05nm, it is difficult to form an indium gallium nitride quantum dot layer in the multiple quantum well region with the sub-well layer 61; if the thickness is > 2.5nm, the polarization effect is increased. The thickness of the GaN layer is, but not limited to, 0.1nm, 0.5nm, 1nm, 1.5nm, or 2nm, for example. Preferably, the thickness of the GaN layer is 0.05 nm-2 nm.
Specifically, in b Ga 1-b The thickness of the N layer is 1 nm-7 nm, and if the thickness is less than 1nm, carriers are easy to leak; if the thickness is more than 7nm, the polarization effect is increased, and the luminous efficiency is reduced. Exemplary, in b Ga 1-b The thickness of the N layer is 2nm, 3nm, 5nm or 6nm, but is not limited thereto. Preferably, in b Ga 1-b The thickness of the N layer is 1 nm-5 nm.
Specifically, the thickness of the first GaN layer 641 is 0.5nm to 1.5nm, and if the thickness is less than 0.5nm, the effect of protecting the quantum well layer is weakened; if the thickness is > 1.5nm, the light extraction efficiency is reduced. The thickness of the first GaN layer 641 is, but not limited to, 0.6nm, 0.8nm, 1nm, or 1.2nm, for example. Preferably, the thickness of the first GaN layer 641 is 0.5nm to 1nm.
Specifically, the thickness of the second GaN layer 642 is 0.5nm to 1.5nm, and if the thickness is less than 0.5nm, the effect of protecting the quantum well layer is weakened; if the thickness is > 1.5nm, the light extraction efficiency is reduced. The second GaN layer 642 has a thickness of 0.6nm, 0.8nm, 1nm, or 1.2nm, by way of example, but is not limited thereto. Preferably, the thickness of the second GaN layer 642 is 0.5nm to 1nm.
Specifically, the thickness of the third GaN layer 643 is 0.5nm to 1.5nm, and if the thickness is less than 0.5nm, the effect of protecting the quantum well layer is weakened; if the thickness is > 1.5nm, the light extraction efficiency is reduced. The thickness of the third GaN layer 643 is, but not limited to, 0.6nm, 0.8nm, 1nm, or 1.2nm, for example. Preferably, the thickness of the third GaN layer 643 is 0.5nm to 1nm.
Wherein in the quantum barrier layer 65Doping with a small amount of Si can increase the conductivity of the quantum barrier layer 65, reduce the resistance, and lower the operating voltage. Specifically, the doping concentration of Si is 8×10 16 cm -3 ~7×10 17 cm -3 If the doping concentration of Si is less than 8×10 16 cm -3 It is difficult to effectively reduce the operating voltage; if the doping concentration of Si is more than 7×10 17 cm -3 Excessive drawbacks can be brought about. Exemplary, the doping concentration of Si is 1×10 17 cm -3 、2×10 17 cm -3 、3×10 17 cm -3 、5×10 17 cm -3 Or 6X 10 17 cm -3 But is not limited thereto. Preferably, the doping concentration of Si in the Si-doped GaN layer is 1×10 17 cm -3 ~5×10 17 cm -3 。
Specifically, the thickness of the Si doped GaN layer is 8 nm-17 nm. If the thickness is less than 8nm, carrier leakage can be caused, so that the luminous effect of the LED is affected; if the thickness is more than 17nm, the polarization effect is increased, and the luminous efficiency is reduced. The thickness of the Si-doped GaN layer is, but not limited to, 10nm, 12nm, 14nm, or 16nm, for example. Preferably, the thickness of the Si doped GaN layer is 10 nm-15 nm.
Among them, the substrate 1 may be a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto. A sapphire substrate is preferred.
The buffer layer 2 may be an AlN layer and/or an AlGaN layer, but is not limited thereto. The thickness of the buffer layer 2 is 20nm to 100nm, and exemplary is 40nm, 50nm, 60nm, 70nm, 80nm or 90nm, but is not limited thereto.
The thickness of the intrinsic GaN layer 3 is 2.5 μm to 3.8 μm, and is exemplified by, but not limited to, 2.6 μm, 2.8 μm, 3 μm, or 3.2 μm.
The doping element of the N-type GaN layer 4 is Si, but is not limited thereto. The doping concentration of the N-type GaN layer 4 was 2.6X10 18 cm -3 ~2.6×10 19 cm -3 . The thickness of the N-type GaN layer 4 is 1 μm to 2.5 μm, and exemplary thicknesses are 1.2 μm, 1.4 μm, 2 μm, 2.2 μm, or 2.4 μm, but not limited thereto.
Wherein the stress release layer 5 is of a periodic structure, the period number is 3-7, and each period comprises I which are sequentially laminatedn x Ga 1-x An N layer and an N-GaN layer. Specifically, x is 0.1 to 0.2, and the doping element of the n-GaN layer is Si, but is not limited thereto. The doping concentration of the N-GaN layer was 3.5X10 17 cm -3 ~5.5×10 17 cm -3 . Single In x Ga 1-x The thickness of the N layer is 3-6 nm, and the thickness of the single N-GaN layer is 8-15 nm.
The electron blocking layer 7 is, but not limited to, an AlGaN layer. The thickness of the electron blocking layer 7 is 30 nm-100 nm, and the ratio of Al component is 0.4-0.7.
The doping element of the P-type GaN layer 8 is Mg, but is not limited thereto. The doping concentration of Mg in the P-type GaN layer 8 was 3.5×10 18 cm -3 ~3.5×10 19 cm -3 . The thickness of the P-type GaN layer 8 is 20 nm-200 nm.
The ohmic contact layer 9 is a P-type InGaN layer, and the P-type doping element is Mg, but is not limited thereto. The doping concentration of Mg is 2.5X10 19 cm -3 ~5.5×10 19 cm -3 The doping concentration of the In component was 3.2X10 2 cm -3 ~4.8×10 2 cm -3 The ohmic contact layer 9 has a thickness of 5nm to 30nm.
Correspondingly, referring to fig. 5, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
s100: providing a substrate;
s200: growing a buffer layer on a substrate;
specifically, the MOCVD grown AlGaN layer may be used as a buffer layer, or the PVD grown AlN layer may be used as a buffer layer, but is not limited thereto. Preferably, the AlN layer is grown by a magnetron sputtering method (PVD) as a buffer layer, the growth temperature is 500-650 ℃, the power is 3000-5000W, ar is used as sputtering gas, and N is used during growth 2 Al is used as a sputtering target material, and a small amount of O is introduced 2 And adjusting the crystal quality.
S300: growing an intrinsic GaN layer on the buffer layer;
specifically, an intrinsic GaN layer is grown in MOCVD, the growth temperature is 1080-1180 ℃, the growth pressure is 200-300 torr, and during growth, M is the temperature of the MOCVDNH is introduced into the OCVD reaction chamber 3 As an N source; by H 2 And N 2 As carrier gas, introducing TMGa as Ga source, and growing for 1-5 min; and switching the pressure to 100-200 torr, and continuously growing for 5-10 min under the other conditions without changing the pressure to obtain the intrinsic GaN layer.
S400: growing an N-type GaN layer on the intrinsic GaN layer;
specifically, an N-type GaN layer is grown in MOCVD, the growth temperature is 1100-1200 ℃, and the growth pressure is 100-150 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S500: growing a stress release layer on the N-type GaN layer;
specifically, in is periodically grown In MOCVD x Ga 1-x An N layer and an N-GaN layer to form a stress relief layer. Wherein In x Ga 1-x The growth temperature of the N layer is 800-850 ℃, the growth pressure is 100-200 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Wherein the growth temperature of the N-GaN layer is 850-900 ℃, the growth pressure is 100-200 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, siH is introduced 4 As Si source, H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
S600: growing a multi-quantum well layer on the stress release layer;
wherein, the auxiliary well layer, the auxiliary barrier layer, the quantum well layer, the composite cap layer and the quantum barrier layer are periodically and sequentially laminated and grown in MOCVD to form the multi-quantum well layer. Specifically, growing the multiple quantum well layer of a single period includes the steps of:
s610: growing a secondary well layer;
wherein In is grown sequentially In a layered manner In MOCVD a Ga 1-a An N layer and an InN layer as sub-well layers. Specifically, the growth temperature of the auxiliary well layer is 680-770 ℃, and the growth pressure is 100-200 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Preferably, the growth temperature of the auxiliary well layer is 700-750 ℃.
S620: growing a secondary barrier layer on the secondary well layer;
wherein, a GaN layer is grown in MOCVD as a secondary barrier layer. Specifically, the growth temperature of the GaN layer is 730-820 ℃, and the growth pressure is 100-200 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As carrier gas, TEGa was introduced as a Ga source. Preferably, the growth temperature of the GaN layer is 750-800 ℃.
S630: growing a quantum well layer on the secondary barrier layer;
wherein In is grown In MOCVD b Ga 1-b And an N layer serving as a quantum well layer. Wherein In b Ga 1-b The growth temperature of the N layer is 680-770 ℃, the growth pressure is 100-200 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Preferably, in b Ga 1-b The growth temperature of the N layer is 700-750 ℃.
S640: growing a composite cover layer on the quantum well layer;
wherein, the first GaN layer, the second GaN layer and the third GaN layer are sequentially laminated and grown in MOCVD to be used as a composite cover layer. The growth temperature of the first GaN layer is 680-750 ℃, and the growth pressure is 100-150 torr; the growth temperature of the second GaN layer is 680-750 ℃, and the growth pressure is 150-200 torr; the growth temperature of the third GaN layer is 740-820 ℃, and the growth pressure is 150-200 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As carrier gas, TEGa was introduced as a Ga source. Preferably, the growth temperature of the first GaN layer is 700-730 ℃, the growth temperature of the second GaN layer is 700-730 ℃, and the growth temperature of the third GaN layer is 760-800 ℃.
S650: growing a quantum barrier layer on the composite cover layer;
wherein, a Si doped GaN layer is grown in MOCVD as a quantum barrier layer. Specifically, the growth temperature of the Si-doped GaN layer is 850The temperature is between 900 ℃ and 150torr, and the growth pressure is between 100torr and 150torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As Si source, N 2 As carrier gas, TEGa was introduced as a Ga source.
S700: growing an electron blocking layer on the multiple quantum well layer;
specifically, an AlGaN layer is grown in MOCVD as an electron blocking layer. Wherein the growth temperature is 1000-1100 ℃, and the growth pressure is 150-250 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
S800: growing a P-type GaN layer on the electron blocking layer;
specifically, a P-type GaN layer is grown in MOCVD, the growth temperature is 950-1050 ℃, and the growth pressure is 200-400 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, let in CP 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S900: growing an ohmic contact layer on the P-type GaN layer;
specifically, a P-type InGaN layer is grown in MOCVD and used as an ohmic contact layer, the growth temperature is 800-900 ℃, and the growth pressure is 200-400 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, let in CP 2 Mg is used as a P-type doping source, TMGa is introduced as a Ga source, TMIn is introduced as an In source, and H is used 2 And N 2 As a carrier gas.
The invention is further illustrated by the following examples:
example 1
The embodiment provides a light emitting diode epitaxial wafer, referring to fig. 1-4, which comprises a substrate 1, and a buffer layer 2, an intrinsic GaN layer 3, an N-type GaN layer 4, a stress release layer 5, a multiple quantum well layer 6, an electron blocking layer 7, a P-type GaN layer 8 and an ohmic contact layer 9 which are sequentially arranged on the substrate 1.
Wherein the substrate 1 is a sapphire substrate, the buffer layer 2 is an AlN layer with a thickness of 32nm, and the intrinsic GaN layer 3 has a thickness of 2.8 μm. The thickness of the N-type GaN layer 4 was 1.6. Mum, the doping element is Si, the doping concentration of Si is 1×10 19 cm -3 。
Wherein the stress release layer 5 has a periodic structure, the period is 5, and each period comprises In laminated In turn x Ga 1-x An N layer and an N-GaN layer. x is 0.12, the doping element of the N-GaN layer is Si, and the doping concentration of the N-GaN layer is 5×10 17 cm -3 . Single In x Ga 1-x The thickness of the N layer was 3.5nm, and the thickness of the single N-GaN layer was 7.5nm.
The multiple quantum well layer 6 has a periodic structure, and the number of periods is 9, and each period includes a sub-well layer 61, a sub-barrier layer 62, a quantum well layer 63, a composite cap layer 64, and a quantum barrier layer 65, which are sequentially stacked.
Wherein the sub-well layer 61 is In sequentially laminated a Ga 1-a N layer 611 and InN layer 612, sub barrier layer 62 is a GaN layer, and quantum well layer 63 is In b Ga 1-b The N layer, the composite cap layer 64 is a first GaN layer 641, a second GaN layer 642, and a third GaN layer 643 stacked in this order, and the quantum barrier layer 65 is a Si doped GaN layer.
Wherein the growth temperature of the sub-well layer 61 is 770 ℃, in a Ga 1-a A is 0.28 and in the N layer 611 a Ga 1-a The thickness of the N layer 611 is 0.8nm and the thickness of the InN layer 612 is 0.3nm. The growth temperature of the secondary barrier layer 62 was 820 deg.c and the thickness of the GaN layer was 2.5nm. The growth temperature of the quantum well layer 63 was 770 ℃, in b Ga 1-b B in the N layer is 0.35, in b Ga 1-b The thickness of the N layer was 7nm. The growth temperature of the first GaN layer 641 is 750 ℃, the growth pressure of the first GaN layer 641 is 120torr, and the thickness of the first GaN layer 641 is 1.5nm; the growth temperature of the second GaN layer 642 is 750 ℃, the growth pressure of the second GaN layer 642 is 170torr, and the thickness of the second GaN layer 642 is 1.5nm; the growth temperature of the third GaN layer 643 was 820 ℃, the growth pressure of the third GaN layer 643 was 170torr, and the thickness of the third GaN layer 643 was 1.5nm. The thickness of the Si doped GaN layer is 17nm, and the doping concentration of Si is 3×10 17 cm -3 。
The electron blocking layer 7 was an AlGaN layer with a thickness of 40nm and an Al composition ratio of 0.56. The doping element of the P-type GaN layer 8 is Mg, and the doping concentration is 1 multiplied by 10 19 cm -3 The thickness of the P-type GaN layer 8 was 35nm. The ohmic contact layer 9 is a P-type InGaN layer, the P-type doping element is Mg, and the doping concentration of Mg is 4 multiplied by 10 19 cm -3 The doping concentration of the In component was 4×10 2 cm -3 The ohmic contact layer 9 had a thickness of 10nm.
Referring to fig. 5, the method for preparing the light emitting diode epitaxial wafer in the embodiment includes the following steps:
(1) Providing a substrate;
(2) Growing a buffer layer on a substrate;
wherein, a magnetron sputtering method (PVD) is adopted to grow the buffer layer, the growth temperature is 600 ℃, the power is 5000W, ar is used as sputtering gas, and N is used as 2 Al is used as a sputtering target material, and a small amount of O is introduced 2 And adjusting the crystal quality.
(3) Growing an intrinsic GaN layer on the buffer layer;
wherein, the intrinsic GaN layer is grown in MOCVD, the growth temperature is 1120 ℃, the growth pressure is 250torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As an N source; by H 2 And N 2 As carrier gas, TMGa is introduced as Ga source, and the growth time is 3min; and switching the pressure to 150torr, and continuing to grow for 8 minutes under the other conditions without changing the pressure, so as to obtain the intrinsic GaN layer.
(4) Growing an N-type GaN layer on the intrinsic GaN layer;
wherein, the N-type GaN layer is grown in MOCVD, the growth temperature is 1160 ℃, and the growth pressure is 120torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, N 2 And H 2 As carrier gas, TMGa is introduced as Ga source, siH is introduced 4 As an N-type dopant source.
(5) Growing a stress release layer on the N-type GaN layer;
wherein In is periodically grown In MOCVD x Ga 1-x An N layer and an N-GaN layer to form a stress relief layer. Wherein In x Ga 1-x The growth temperature of the N layer is 820 ℃, the growth pressure is 150torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As carrier gas, TEGa as Ga source and TMIn as IAnd n sources. Wherein the growth temperature of the N-GaN layer is 880 ℃, the growth pressure is 150torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, siH is introduced 4 As Si source, H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
(6) Growing a multi-quantum well layer on the stress release layer;
wherein, the auxiliary well layer, the auxiliary barrier layer, the quantum well layer, the composite cap layer and the quantum barrier layer are periodically and sequentially laminated and grown in MOCVD to form the multi-quantum well layer. Specifically, growing the multiple quantum well layer of a single period includes the steps of:
growing a secondary well layer;
wherein In is grown sequentially In a layered manner In MOCVD a Ga 1-a An N layer and an InN layer as sub-well layers. Specifically, the growth temperature of the auxiliary well layer is 770 ℃, and the growth pressure is 150torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
(II) growing a secondary barrier layer on the secondary well layer;
wherein, a GaN layer is grown in MOCVD as a secondary barrier layer. Specifically, the growth temperature of the GaN layer is 820 ℃, and the growth pressure is 150torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As carrier gas, TEGa was introduced as a Ga source.
(iii) growing a quantum well layer on the secondary barrier layer;
wherein In is grown In MOCVD b Ga 1-b And an N layer serving as a quantum well layer. Wherein In b Ga 1-b The growth temperature of the N layer is 770 ℃, the growth pressure is 150torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
(iv) growing a composite cap layer over the quantum well layer;
wherein, the first GaN layer, the second GaN layer and the third GaN layer are sequentially laminated and grown in MOCVD to be used as a composite cover layer. Wherein the growth temperature of the first GaN layer is 750 DEG CThe long pressure is 120torr; the growth temperature of the second GaN layer is 750 ℃, and the growth pressure is 170torr; the growth temperature of the third GaN layer was 820℃and the growth pressure was 170torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As carrier gas, TEGa was introduced as a Ga source.
(v) growing a quantum barrier layer on the composite cap layer;
wherein, a Si doped GaN layer is grown in MOCVD as a quantum barrier layer. Specifically, the growth temperature of the Si-doped GaN layer is 870 ℃, and the growth pressure is 120torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As Si source, N 2 As carrier gas, TEGa was introduced as a Ga source.
(7) Growing an electron blocking layer on the multiple quantum well layer;
wherein an AlGaN layer is grown in MOCVD as an electron blocking layer. Wherein the growth temperature is 1050 ℃, and the growth pressure is 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(8) Growing a P-type GaN layer on the electron blocking layer;
wherein, the P-type GaN layer is grown in MOCVD, the growth temperature is 1000 ℃, and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, let in CP 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(9) Growing an ohmic contact layer on the P-type GaN layer;
specifically, a P-type InGaN layer was grown in MOCVD as an ohmic contact layer at 850 ℃ and at a growth pressure of 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, let in CP 2 Mg is used as a P-type doping source, TMGa is introduced as a Ga source, TMIn is introduced as an In source, and H is used 2 And N 2 As a carrier gas.
Example 2
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 In that In a Ga 1-a A in N layer 611 is 0.2 and in b Ga 1-b B in the N layer is 0.25.
The remainder was the same as in example 1.
Example 3
This embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 2 in that the growth temperature of the sub-well layer 61 is 725 ℃, the growth temperature of the sub-barrier layer 62 is 775 ℃, the growth temperature of the quantum well layer 63 is 725 ℃, the growth temperature of the first GaN layer 641 is 715 ℃, the growth temperature of the second GaN layer 642 is 715 ℃, and the growth temperature of the third GaN layer 643 is 775 ℃.
The remainder was the same as in example 2.
Example 4
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 3 In that In a Ga 1-a The thickness of the N layer 611 is 0.4nm, the thickness of the InN layer 612 is 0.15nm, the thickness of the GaN layer is 1.2nm, in b Ga 1-b The thickness of the N layer was 3nm, the thickness of the first GaN layer 641 was 0.8nm, the thickness of the second GaN layer 642 was 0.8nm, the thickness of the third GaN layer 643 was 0.8nm, and the thickness of the Si doped GaN layer was 12nm.
The remainder was the same as in example 3.
Example 5
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 4 In that In b Ga 1-b The thickness of the N layer is 2nm, so that the thickness ratio of the sub-well layer 61 to the quantum well layer 63 is 0.2-0.4.
Comparative example 1
The present comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the sub-well layer 61, the sub-barrier layer 62, and the composite cap layer 64 are not included in the multi-quantum well layer 6. Accordingly, the preparation method does not comprise the preparation steps of the three layers. The remainder was the same as in example 1.
Comparative example 2
The present comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the sub-well layer 61 and the sub-barrier layer 62 are not included in the multi-quantum well layer 6, and the second GaN layer 642 and the third GaN layer 643 are not included in the composite cap layer 64. Accordingly, the preparation steps of the above layers are not included in the preparation method. The remainder was the same as in example 1.
Comparative example 3
The present comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the sub-well layer 61 and the sub-barrier layer 62 are not included in the multi-quantum well layer 6. Accordingly, the preparation steps of the above layers are not included in the preparation method. The remainder was the same as in example 1.
Comparative example 4
The present comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the sub barrier layer 62 is not included in the multiple quantum well layer 6. The remainder was the same as in example 1.
Comparative example 5
The present comparative example provides a light emitting diode epitaxial wafer, which is different from example 1 in that a=b=0.2. The remainder was the same as in example 1.
The light emitting diode epitaxial wafers obtained in examples 1 to 5 and comparative examples 1 to 5 were tested by the following specific test methods:
(1) Preparing an epitaxial wafer into a chip with the size of 3mil multiplied by 5mil, and testing the luminous brightness of the chip under the current of 3 mA;
(2) Operating voltage: operating voltage testing was performed using a Keithley2450 digital source meter;
(3) Antistatic ability test: and testing the antistatic performance of the base chip by using an electrostatic instrument under an HBM (human body discharge model) model, wherein the test chip can bear the passing proportion of reverse 4000V static electricity.
The specific results are as follows:
as can be seen from the table, when the conventional multi-quantum well layer structure (comparative example 1) of the light-emitting diode is changed into the multi-quantum well layer structure of the present invention, the light-emitting brightness is increased from 1.912mW to 1.956mW, the operating voltage is reduced from 2.773V to 2.721V, and the antistatic ability is increased from 93.34% to 97.14%, which indicates that the multi-quantum well layer of the present invention can improve the light-emitting efficiency, reduce the operating voltage, and improve the antistatic ability.
In addition, as can be seen from the comparison of example 1 and comparative examples 2 to 5, when the multiple quantum well layer structure in the present invention is changed, it is difficult to effectively achieve the effects of improving luminance, lowering operating voltage, and improving antistatic ability.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a multiple quantum well layer, an electron blocking layer, a P-type GaN layer and an ohmic contact layer which are sequentially arranged on the substrate, and is characterized in that the multiple quantum well layer is of a periodic structure, the number of periods is 6-10, and each period comprises a secondary well layer, a secondary barrier layer, a quantum well layer, a composite cover layer and a quantum barrier layer which are sequentially stacked;
the sub-well layer comprises In laminated In sequence a Ga 1-a An N layer and an InN layer, the sub barrier layer comprising a GaN layer, the quantum well layer comprising In b Ga 1-b The composite cover layer comprises a first GaN layer, a second GaN layer and a third GaN layer which are sequentially stacked, and the quantum barrier layer comprises a Si doped GaN layer;
wherein a < b;
the growth temperature of the first GaN layer is less than or equal to the growth temperature of the second GaN layer and less than the growth temperature of the third GaN layer;
the growth pressure of the first GaN layer is less than that of the second GaN layer and less than or equal to that of the third GaN layer;
the growth temperature of the auxiliary barrier layer is greater than the growth temperature of the auxiliary well layer, and the growth temperature of the auxiliary barrier layer is greater than the growth temperature of the quantum well layer.
2. The light-emitting diode epitaxial wafer of claim 1, wherein 0.18 < a < 0.25,0.2 < b < 0.3.
3. The light-emitting diode epitaxial wafer according to claim 1, wherein the growth temperature of the sub-well layer is 700 ℃ -750 ℃, the growth temperature of the sub-barrier layer is 750 ℃ -800 ℃, the growth temperature of the quantum well layer is 700 ℃ -750 ℃, the growth temperature of the first GaN layer is 700 ℃ -730 ℃, the growth temperature of the second GaN layer is 700 ℃ -730 ℃, and the growth temperature of the third GaN layer is 760 ℃ -800 ℃.
4. The light-emitting diode epitaxial wafer of claim 1, wherein the growth pressure of the first GaN layer is 100torr to 150torr, the growth pressure of the second GaN layer is 150torr to 200torr, and the growth pressure of the third GaN layer is 150torr to 200torr.
5. The light-emitting diode epitaxial wafer of claim 1, wherein the thickness of the secondary well layer is less than or equal to 1nm.
6. The light-emitting diode epitaxial wafer of claim 5, wherein a thickness ratio of the sub-well layer to the quantum well layer is 0.2 to 0.4.
7. The light-emitting diode epitaxial wafer of claim 6, wherein the In a Ga 1-a The thickness of the N layer is 0.1-0.7 nm, the thickness of the InN layer is 0.05-0.25 nm, the thickness of the GaN layer is 0.05-2 nm, and the In b Ga 1- b The thickness of the N layer is 1-5 nm, the thickness of the first GaN layer is 0.5-1 nm, the thickness of the second GaN layer is 0.5-1 nm, the thickness of the third GaN layer is 0.5-1 nm, and the thickness of the Si doped GaN layer is 10-15 nm.
8. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 7, and is characterized by comprising the following steps:
providing a substrate, and sequentially growing a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a multiple quantum well layer, an electron blocking layer, a P-type GaN layer and an ohmic contact layer on the substrate, wherein the multiple quantum well layer is of a periodic structure, the number of periods is 6-10, and each period comprises a secondary well layer, a secondary barrier layer, a quantum well layer, a composite cover layer and a quantum barrier layer which are sequentially laminated;
the sub-well layer comprises In laminated In sequence a Ga 1-a An N layer and an InN layer, the sub barrier layer comprising a GaN layer, the quantum well layer comprising In b Ga 1-b The composite cover layer comprises a first GaN layer, a second GaN layer and a third GaN layer which are sequentially stacked, and the quantum barrier layer comprises a Si doped GaN layer;
wherein a < b;
the growth temperature of the first GaN layer is less than or equal to the growth temperature of the second GaN layer and less than the growth temperature of the third GaN layer;
the growth pressure of the first GaN layer is less than that of the second GaN layer and less than or equal to that of the third GaN layer;
the growth temperature of the auxiliary barrier layer is greater than the growth temperature of the auxiliary well layer, and the growth temperature of the auxiliary barrier layer is greater than the growth temperature of the quantum well layer.
9. The method for preparing the light-emitting diode epitaxial wafer according to claim 8, wherein the growth temperature of the quantum barrier layer is 850-900 ℃;
the growth pressure of the auxiliary well layer is 100-200 torr, the growth pressure of the auxiliary barrier layer is 100-200 torr, the growth pressure of the quantum well layer is 100-200 torr, and the growth pressure of the quantum barrier layer is 100-150 torr.
10. A light emitting diode comprising the light emitting diode epitaxial wafer according to any one of claims 1 to 7.
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