CN117497578B - IGBT with low electric leakage and preparation method - Google Patents

IGBT with low electric leakage and preparation method Download PDF

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CN117497578B
CN117497578B CN202311824666.4A CN202311824666A CN117497578B CN 117497578 B CN117497578 B CN 117497578B CN 202311824666 A CN202311824666 A CN 202311824666A CN 117497578 B CN117497578 B CN 117497578B
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CN117497578A (en
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蔡文哲
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Shenzhen Sirius Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]

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Abstract

The invention provides an IGBT with low electric leakage and a preparation method thereof, wherein the IGBT comprises the following components: a heterojunction substrate; the heterojunction substrate comprises a base and a first N+ buffer layer; the substrate is positioned below the first N+ buffer layer and is adjacent to the first N+ buffer layer; the first N+ buffer layer is located between the drift layer and the substrate and is adjacent to the drift layer. The invention replaces the traditional silicon substrate with the material with higher forbidden band width and better heat conduction performance, such as silicon carbide material, because the third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, the invention can be suitable for high-temperature and high-frequency environments, and the invention introduces the N-type heavily doped layer above the silicon carbide layer as a buffer layer, and the silicon-based N+ doped layer can form an electron trap, thereby further weakening the electric leakage phenomenon at the bottom of the substrate and reducing the integral thermal effect of the device.

Description

IGBT with low electric leakage and preparation method
Technical Field
The invention relates to the technical field of semiconductors, in particular to an IGBT with low electric leakage and a preparation method thereof.
Background
IGBT (Insulated Gate Bipolar Transistor) is an insulated gate bipolar transistor (igbt) for short, which is composed of a Bipolar Junction Transistor (BJT) and a metal oxide field effect transistor (MOSFET), is a composite fully-controlled voltage-driven switching power semiconductor device, is a core device for realizing electric energy conversion, and is one of the main development directions of the current MOS-bipolar power devices. The IGBT has the characteristics of high MOSFET input impedance, easy driving of a grid electrode and the like, has the advantages of high current density, high power density and the like of a bipolar transistor, and is widely applied to the fields of high voltage and high current such as rail transit, new energy automobiles, smart grids, wind power generation and the like, and the fields of low-power household appliances such as microwave ovens, washing machines, electromagnetic ovens, electronic rectifiers, cameras and the like. The IGBT is basically the same as the MOSFET in driving method, the IGBT is a three-terminal device, the front surface is provided with two electrodes, namely an emitter (Emitter) and a Gate (Gate), the back surface is provided with a Collector (Collector), and in a forward working state, the emitter is grounded or connected with negative voltage, the Collector is connected with positive voltage, and the voltage Vce between the two electrodes is >0, so the emitter and the Collector of the IGBT are respectively called a Cathode (Cathode) and an Anode (Anode). The IGBT can control the on/off/blocking state of the IGBT by controlling the magnitudes of its collector-emitter voltage Vce and gate-emitter voltage Vge.
For power devices, it is critical to achieve enhanced and high voltage operation. From the standpoint of safety and energy consumption, it is necessary that no extra leakage occurs in the event of a power outage. The preparation of enhanced devices with superior performance is one research direction of great research value. Under the condition that the conventional IGBT is turned off, if the emitter and the collector are continuously pressurized, the condition of large-area electric leakage of the IGBT can occur, the electric leakage channel layer is mainly located in the drift layer, electric leakage phenomenon that current flows from the drift layer to the substrate can be further caused, the electric leakage phenomenon can further cause internal heating of the device to cause failure of the IGBT device, the problem of circuit damage is solved, the performance and reliability of the power device are directly affected by the selection of the substrate material of the semiconductor power device, silicon, quartz, sapphire and the like are usually selected as the substrate material in the prior art, but the conventional substrate material cannot meet insulation requirements under the high-voltage working condition of the power device, and the application field of the IGBT is severely limited.
Disclosure of Invention
The invention aims to provide an IGBT with low electric leakage and a preparation method thereof, wherein the traditional silicon substrate is replaced by a material with higher forbidden bandwidth and better heat conduction performance, such as a silicon carbide material, and because the third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, the IGBT can be suitable for high-temperature, high-frequency, high-power and extreme environments, compared with the silicon material, the silicon carbide has larger forbidden bandwidth and higher critical breakdown field strength, and an N-type heavily doped layer is introduced above the silicon carbide layer to serve as a buffer layer, and the silicon-based N+ doped layer can form an electronic trap, so that the electric leakage phenomenon at the bottom end of the substrate is further weakened, and the integral heat effect of a device is reduced.
An IGBT with low leakage comprising: a heterojunction substrate;
The heterojunction substrate comprises a base and a first N+ buffer layer;
The substrate is positioned below the first N+ buffer layer and is adjacent to the first N+ buffer layer;
the first N+ buffer layer is located between the drift layer and the substrate and is adjacent to the drift layer.
Preferably, the forbidden bandwidth of the filling material of the substrate is larger than that of silicon.
Preferably, the filling material of the substrate includes: silicon carbide.
Preferably, the doping concentration of the first n+ buffer layer is greater than the doping concentration of the drift layer.
Preferably, the thickness of the first n+ buffer layer is 3um.
Preferably, the thickness of the substrate is 25um.
Preferably, the thermal conductivity of the filler material of the substrate is equal to or greater than the thermal conductivity of silicon carbide.
Preferably, the method further comprises: a second n+ buffer layer;
The second N+ buffer layer is positioned in the drift layer and coats the P+ region.
Preferably, the method further comprises: an emitter, a collector, a gate, a drift layer, an n+ region, a p+ region, and a body region;
The drift layer is positioned above the heterojunction substrate;
the body region is positioned on the upper layer of the drift layer;
The P+ region is positioned on the upper layer of the drift layer;
The N+ region is covered by the body region;
The collector electrode is located above the P+ region;
The emitter is located above the body region and the n+ region;
the gate is located over the body region, the drift layer, and the n+ region.
A preparation method of an IGBT with low electric leakage comprises the following steps:
a layer of N-type heavily doped silicon layer is epitaxially grown on the substrate to form a first N+ buffer layer;
Epitaxially forming a drift layer over the first n+ buffer layer;
forming an N+ region, a P+ region, a second N+ buffer layer and a body region on the upper layer of the drift layer by ion implantation;
a gate, a collector and an emitter are deposited.
The invention replaces the silicon substrate of the traditional IGBT with a material with higher forbidden band width than the silicon substrate, because the material with higher forbidden band width can form higher potential barrier difference with the drift layer, electrons are difficult to pass through the potential barrier, the current leaked from the drift layer to the substrate direction is reduced, the replaced substrate material also has high heat dissipation performance, the heat in the IGBT can be effectively led out, the heating condition in the IGBT is improved, the condition of IGBT failure caused by overheat in the IGBT is avoided, an N+ buffer layer with heavily doped N type is additionally arranged below the drift layer, and an electronic trap can be manufactured on the N+ doped layer with silicon base, thereby further weakening the leakage phenomenon at the bottom end of the substrate and reducing the integral heat effect of the IGBT device.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic diagram of an IGBT structure of the present invention;
fig. 2 is a schematic diagram of an IGBT manufacturing process according to the present invention;
Fig. 3 is a schematic diagram of the IGBT manufacturing flow structure of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
For power devices, it is critical to achieve enhanced and high voltage operation. From the standpoint of safety and energy consumption, it is necessary that no extra leakage occurs in the event of a power outage. The preparation of enhanced devices with superior performance is one research direction of great research value. Under the condition that the conventional IGBT is turned off, if the emitter and the collector are continuously pressurized, the condition of large-area electric leakage of the IGBT can occur, the electric leakage channel layer is mainly located in the drift layer, electric leakage phenomenon that current flows from the drift layer to the substrate can be further caused, the electric leakage phenomenon can further cause internal heating of the device to cause failure of the IGBT device, the problem of circuit damage is solved, the performance and reliability of the power device are directly affected by the selection of the substrate material of the semiconductor power device, silicon, quartz, sapphire and the like are usually selected as the substrate material in the prior art, but the conventional substrate material cannot meet insulation requirements under the high-voltage working condition of the power device, and the application field of the IGBT is severely limited.
In the prior art, in order to prevent the substrate from leaking electricity, methods are generally adopted including: the surface treatment of the substrate is enhanced, and common surface treatment methods include cleaning, oxidation, film deposition, and the like. The cleaning can remove impurities and pollutants on the surface, so that the purity of the surface is improved; oxidation can form a layer of oxide film, so that the insulating property is enhanced; the film deposition can form an insulating layer on the surface, so that the insulating capability is further improved. By these surface treatment methods, occurrence of leakage problems can be effectively prevented. The structural design of the semiconductor device is also an important link for preventing electric leakage. For example, in transistor design, the distance between the gate, the source and the drain is reasonably set, and the gap is filled with a proper insulating material, so that current leakage can be effectively prevented. In addition, the insulation performance of the device can be improved by adding structures such as a protective layer and an isolation layer, and the electric leakage is further reduced. Reinforcing electrical insulation is an important means of preventing electrical leakage. In the manufacturing process of the semiconductor device, electrical insulation may be achieved by using materials such as an insulating layer, an insulating substrate, an insulating paste, and the like. The insulating materials have good electrical insulation performance, and can effectively isolate current and prevent leakage. Strict quality control is critical to prevent leakage problems. In the production process of the semiconductor device, a perfect quality control system needs to be established to ensure that each link meets the standard requirements. For example, in the material purchasing process, materials meeting the standard are selected; in the manufacturing process, the process parameters are strictly controlled; during the test, a tight electrical performance test is performed. However, the above method is relatively expensive to produce and is not suitable for mass production.
The invention replaces the silicon substrate of the traditional IGBT with a material with higher forbidden band width than the silicon substrate, because the material with higher forbidden band width can form higher potential barrier difference with the drift layer, electrons are difficult to pass through the potential barrier, the current leaked from the drift layer to the substrate direction is reduced, the replaced substrate material also has high heat dissipation performance, the heat in the IGBT can be effectively led out, the heating condition in the IGBT is improved, the condition of IGBT failure caused by overheat in the IGBT is avoided, an N+ buffer layer with heavily doped N type is additionally arranged below the drift layer, and an electronic trap can be manufactured on the N+ doped layer with silicon base, thereby further weakening the leakage phenomenon at the bottom end of the substrate and reducing the integral heat effect of the IGBT device.
Example 1
An IGBT with low leakage, with reference to fig. 1, comprising: a heterojunction substrate;
The substrate is a material for supporting crystal formation, and the substrate plays a role of mechanical support. In the present invention, the substrate is made of silicon carbide material, and its mechanical strength and stability can effectively support various stresses and distortions during crystal growth. This is critical to ensure uniformity and integrity of crystal growth. In addition, the substrate can also prevent impurities and defects during crystal growth. Second, the substrate plays an important role in the electrical performance of the IGBT. In fabricating an IGBT, the electrical properties of the substrate determine the performance and stability of the device. For example, the conductivity of the substrate directly affects the efficiency and speed of current transport. In addition, the electron affinity and the forbidden band width of the substrate are also important for adjusting the threshold voltage and the electron mobility of the IGBT. In addition, the substrate plays an important role in isolating the insulating layer of the IGBT. In IGBT fabrication, the insulating layer of the substrate is typically composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulating properties of the IGBT, such as electrical insulation and capacitance characteristics. The good insulating layer can effectively isolate different electrodes in the IGBT structure and reduce leakage current and capacitive coupling effect.
The heterojunction substrate comprises a base and a first N+ buffer layer;
the heterojunction of the semiconductor is a special PN junction, and is formed by sequentially depositing more than two layers of different semiconductor material films on the same base, wherein the materials have different energy band gaps, and can be compounds such as gallium arsenide or semiconductor alloys such as silicon-germanium. The heterojunction is an interfacial region formed by the contact of two different semiconductors. Heterojunctions can be classified into homoheterojunctions (P-junctions or N-junctions) and heteroheterojunctions (P-N or P-N) according to the conductivity types of the two materials, and multilayer heterojunctions are called heterostructures. The conditions under which the heterojunction is typically formed are: the two semiconductors have similar crystal structures, similar atomic spacing and thermal expansion coefficients. Heterojunction can be fabricated by interfacial alloy, epitaxial growth, vacuum deposition, etc. The heterojunction has excellent photoelectric characteristics which cannot be achieved by PN junctions of two semiconductors, so that the heterojunction is suitable for manufacturing ultra-high-speed switching devices, solar cells, semiconductor lasers and the like.
Because the heterojunction is formed by contacting semiconductor single crystal materials of two different materials, and lattice constants of the two different materials are often different, lattice mismatch results are generated, dangling bonds are generated at the interface of the two semiconductor materials, the dangling bonds are a part of unsaturated bonds in the semiconductor materials with smaller lattice constants at the interface, the dangling bonds can seriously affect the movement of carriers, so that the heterojunction has the characteristics that the heterojunction does not have, the heterojunction energy band may have abrupt change of the energy band, or an electron potential barrier (upward peak) exists at the interface, or an electron potential well (downward peak) exists at the interface.
In the embodiment of the invention, the heterojunction substrate consists of an N-type semiconductor first N+ buffer layer made of a silicon material and a P-type semiconductor made of a semiconductor material with higher forbidden band width than the silicon material and strong heat conduction performance.
The substrate is positioned below the first N+ buffer layer and is adjacent to the first N+ buffer layer;
the first N+ buffer layer is positioned between the drift layer and the substrate and is adjacent to the drift layer.
The substrate and the first N+ buffer layer form a heterojunction substrate together, in fig. 1, the substrate, the first N+ buffer layer and the drift layer are respectively arranged from bottom to top in the vertical direction, the substrate is tightly connected with the first N+ buffer layer, the first N+ buffer layer is tightly connected with the drift layer, in a conventional IGBT, the electron moving direction is from an emitter to an N+ region, then the electron moves from the channel to the drift layer through a channel which is opened by a grid and can be in a body region, the electron passes through a P+ region and finally reaches a collector, in the process, leakage current from the drift layer to the substrate exists in the drift layer, when electrons of the drift layer leak to the substrate, the device generates heat, the circuit is damaged, the working performance of the IGBT is seriously affected.
Preferably, the fill material of the substrate has a forbidden bandwidth greater than that of silicon.
The forbidden band width refers to a band gap width (the unit is electron volt (ev)), and the energy of electrons in the solid cannot be continuously valued, but is discontinuous energy bands, free electrons or holes exist in order to conduct electricity, the energy band in which the free electrons exist is called a conduction band, and the energy band in which the free holes exist is called a valence band. To be a free electron or hole, the bound electron must acquire enough energy to transition from the valence band to the conduction band, the minimum of which is the forbidden bandwidth.
The forbidden bandwidth is an important characteristic parameter of a semiconductor, and its size is mainly determined by the energy band structure of the semiconductor, that is, the binding property of the crystal structure and atoms. A large number of electrons in the semiconductor valence band are electrons on the valence bond (referred to as valence electrons) and are not capable of conducting electricity, i.e., are not carriers. Conduction can only occur after the valence electrons have transitioned to the conduction band (i.e., intrinsic excitation) to generate free electrons and free holes. Holes are in fact valence vacancies left after a valence electron transition to the conduction band (the motion of one hole is equivalent to the motion of a large group of valence electrons). Therefore, the magnitude of the forbidden bandwidth reflects a physical quantity of how strongly or weakly valence electrons are bound, i.e., the minimum energy required to generate intrinsic excitation. The energy between the lowest energy level of the conduction band and the highest energy level of the valence band. The electrons stay mostly in the valence band due to the lower energy level of the valence band. The valence band is typically predominantly holes, nonconductive, and conduction band electrons can move and conduct. The forbidden band width is the separation between the conduction band and the valence band, which is one of the electron transitions. Electrons bound in the valence band must gain enough energy to transition to the conduction band to become free electrons.
Because the forbidden bandwidth of the filling material of the base is larger than that of the silicon, the current can be prevented from being remained from the buffer layer to the substrate, and the formation of the heterojunction enables electrons to have energy band offset between the silicon and the filling material of the base, so that an electron barrier is formed, and the electron barrier can control the movement of electrons between the two materials, so that the purpose of blocking the electrons outside the substrate is achieved.
Materials having a larger forbidden band width than silicon mainly include silicon carbide (SiC), cubic boron nitride (C-BN), gallium nitride (GaN) aluminum nitride (AlN), zinc selenide (ZnSe), diamond, and the like. The material has the forbidden band width of more than 2eV, the forbidden band width of silicon is 1.12eV, and the wide forbidden band semiconductor material has the characteristics of wide band gap, high critical breakdown electric field, high thermal conductivity, high carrier saturation drift speed and the like, and can be applied to the aspects of high temperature, high frequency, high power, photoelectrons, radiation resistance and the like.
Preferably, the filler material of the substrate comprises: silicon carbide.
Because the forbidden bandwidth of silicon carbide is far greater than that of silicon, and other properties of silicon carbide are also superior to that of silicon, for example, the breakdown field strength of silicon carbide is 3MV/cm, while the breakdown field strength of silicon is only 0.3MV/cm, the forbidden bandwidth of silicon carbide is far greater than that of silicon, the corresponding intrinsic carrier concentration is smaller than that of silicon, and the highest working temperature of a wide forbidden bandwidth semiconductor is higher than that of a silicon material. The breakdown field strength is much greater than silicon. As a preferred embodiment, the present invention uses silicon carbide as the filler material for the substrate.
Preferably, the doping concentration of the first n+ buffer layer is greater than the doping concentration of the drift layer.
The doping concentration of the first n+ buffer layer affects the energy band difference between the drift layer and the substrate, the higher the doping concentration of the first n+ buffer layer, the more difficult the electrons reach the first n+ buffer layer from the drift layer, the larger the energy band difference between the first n+ buffer layer and the substrate, and the better the anti-creeping performance of the IGBT, so the doping concentration of the first n+ buffer layer is set to be larger than the doping concentration of the drift layer, so that the electron barrier is larger, and the anti-creeping performance of the substrate is better.
Preferably, the thickness of the first n+ buffer layer is 3um.
The greater the thickness of the first n+ buffer layer, the more difficult it is for electrons to pass through the first n+ buffer layer to reach the substrate, and the better the anti-leakage performance of the IGBT, if the thickness of the first n+ buffer layer is increased, the doping concentration of the first n+ buffer layer may be reduced, and correspondingly, if the thickness of the first n+ buffer layer is smaller, the doping thickness of the first n+ buffer layer needs to be increased in order to block electrons from passing through the first n+ buffer layer, and if the thickness of the first n+ buffer layer is too large, the defect that the chip area increases may be caused, so the thickness of the first n+ buffer layer is not too large, and as a preferred embodiment, the invention sets the doping concentration of the first n+ buffer layer to 10 19cm-3, thereby significantly improving the anti-leakage performance of the substrate.
Preferably, the thickness of the substrate is 25um.
The substrate provides mechanical support for the whole IGBT, can conduct heat with the external environment, can discharge heat generated by the IGBT when the IGBT normally works to the outside, and the thickness of the substrate cannot be smaller than 20um because the substrate needs to provide mechanical support for the IGBT, if the substrate is too thick, the chip area is increased, and the thickness of the substrate is set to be 25um as a preferable embodiment.
Preferably, the thermal conductivity of the filler material of the substrate is equal to or greater than the thermal conductivity of silicon carbide.
The thermal conductivity is the thermal conductivity coefficient of the semiconductor material, reflects the thermal conductivity capability of the semiconductor material, is defined as the heat transferred by a unit thermal gradient (the temperature is reduced by 1K in 1m length) through a unit thermal conducting surface in unit time, and an object with high thermal conductivity is an excellent thermal conductor; while the thermal conductivity is small is a poor conductor of heat or a thermal insulator. The value of the thermal conductivity is also affected by the temperature, the density of the material is high and its thermal conductivity is also generally high. The heat conductivity of the metal is reduced when the metal contains impurities, the heat conductivity of the alloy is lower than that of pure metal, and the heat conductivity of various substances is in the range of: the metal is 50-415W/(mXK), the alloy is 12-120W/(mXK), the heat insulating material is 0.03-0.17W/(mXK), the liquid is 0.17-0.7W/(mXK), the gas is 0.007-0.17W/(mXK), and the carbon nano tube is up to 1000W/(mXK) or more. The traditional semiconductor material silicon has the thermal conductivity of 150W/(m×K), and the thermal conductivity of 490W/(m×K) which is far greater than that of silicon, so that the material with the thermal conductivity greater than or equal to that of silicon carbide and the forbidden bandwidth greater than that of silicon can be used as the filling material of the substrate in the selection of the substrate filling material.
Preferably, the method further comprises: a second n+ buffer layer;
The second N+ buffer layer is located in the drift layer and coats the P+ region.
The second N+ buffer layer is used for improving electric field distribution near the collector, and because the phenomenon of electric field line concentration often occurs near the collector, the too high electric field strength can lead to the defect of IGBT breakdown in advance.
Preferably, the method further comprises: an emitter, a collector, a gate, a drift layer, an n+ region, a p+ region, and a body region;
the drift layer is located above the heterojunction substrate;
The electric field distribution of the drift layer plays a key role in the on-characteristics and current control of the IGBT. When a gate voltage is applied to the IGBT, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the current flow between the source and the drain. When the IGBT works, current between the source electrode and the drain electrode is mainly transmitted through the N-drift layer. The doping type and concentration of the drift layer determine the conduction type (N-type or P-type) and the magnitude of the current. The structure and characteristics of the drift layer directly affect the current control capability of the IGBT. By adjusting the shape, size and doping concentration of the drift layer, accurate control of current can be achieved, so that the requirements of different applications are met.
The body region is positioned on the upper layer of the drift layer;
the P+ region is positioned on the upper layer of the drift layer;
the N+ region is covered by the body region;
The collector electrode is positioned above the P+ region;
the collector is used for collecting and outputting electrons and converting the electron flow into current output.
The emitter is positioned above the body region and the N+ region;
The emitter is used for supplying electrons and controlling current.
The gate is located over the body region, the drift layer and the n+ region.
The grid electrode is a control electrode in the IGBT, is separated from the channel by an insulating layer and is a key part of the IGBT. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the emitter and collector.
Example 2
A method for manufacturing an IGBT with low leakage, referring to fig. 2, fig. 3, comprising:
S100, an N-type heavily doped silicon layer is epitaxially grown on the substrate to form a first N+ buffer layer;
The epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate, and the epitaxial process is a process of growing a crystal layer in the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. The epitaxial growth modes are classified into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy according to the different phase states of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During ion implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, amorphization occurs, and a surface amorphous silicon layer is formed; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The principle of chemical vapor epitaxy is basically the same as that of Chemical Vapor Deposition (CVD), and the process of depositing a film is carried out by mixing gases and then carrying out chemical reaction on the surface of a wafer; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processing in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like.
S200, forming a drift layer on the upper part of the first N+ buffer layer in an epitaxial manner;
S300, forming an N+ region, a P+ region, a second N+ buffer layer and a body region on the upper layer of the drift layer by ion implantation;
The invention adopts an ion implantation mode to form an N+ region, a P+ region, a second N+ buffer layer and a body region on the upper layer of the drift layer by ion implantation. The doping concentration and thickness of the silicon-based N+ buffer layer are controlled by controlling the times, the doses and the energy of ion implantation. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The mass selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocking aperture or slit which only allows ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S400, depositing a grid electrode, a collector electrode and an emitter electrode.
The deposited grid adopts a polysilicon deposition method, namely, a grid electrode and local connection lines are formed on the silicide stack on the first layer of polysilicon (Poly 1), and the second layer of polysilicon (Poly 2) forms contact plugs between the source electrode/drain electrode and the unit connection lines. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) that can be performed in situ by directly introducing a dopant gas of arsine (AH 3), phosphine (PH 3), or diborane (B 2H6) into the silicon material gas of silane or DCS in a reaction chamber (i.e., in a furnace). Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100-200 a/min, which is determined primarily by the temperature at which the deposition is performed.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like.
The invention replaces the silicon substrate of the traditional IGBT with a material with higher forbidden band width than the silicon substrate, because the material with higher forbidden band width can form higher potential barrier difference with the drift layer, electrons are difficult to pass through the potential barrier, the current leaked from the drift layer to the substrate direction is reduced, the replaced substrate material also has high heat dissipation performance, the heat in the IGBT can be effectively led out, the heating condition in the IGBT is improved, the condition of IGBT failure caused by overheat in the IGBT is avoided, an N+ buffer layer with heavily doped N type is additionally arranged below the drift layer, and an electronic trap can be manufactured on the N+ doped layer with silicon base, thereby further weakening the leakage phenomenon at the bottom end of the substrate and reducing the integral heat effect of the IGBT device.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (5)

1. A lateral IGBT with low leakage comprising: a heterojunction substrate;
The heterojunction substrate comprises a base and a first N+ buffer layer;
The substrate is made of silicon carbide;
the first N+ buffer layer is an N-type heavily doped silicon layer;
The substrate is positioned below the first N+ buffer layer and is adjacent to the first N+ buffer layer;
the first N+ buffer layer is positioned between the drift layer and the substrate and is adjacent to the drift layer;
Further comprises: an emitter, a collector, a gate, an n+ region, a p+ region, and a body region;
The drift layer is positioned above the heterojunction substrate;
the body region is positioned on the upper layer of the drift layer;
The P+ region is positioned on the upper layer of the drift layer;
The N+ region is covered by the body region;
The collector electrode is located above the P+ region;
The emitter is located above the body region and the n+ region;
the grid electrode is positioned above the body region, the drift layer and the N+ region;
Further comprises: a second n+ buffer layer;
the second N+ buffer layer is located in the drift layer and wraps the P+ region.
2. The lateral IGBT with low leakage of claim 1 wherein the doping concentration of the first n+ buffer layer is greater than the doping concentration of the drift layer.
3. The lateral IGBT with low leakage of claim 1 wherein the first n+ buffer layer has a thickness of 3 microns.
4. The lateral IGBT with low leakage of claim 1 wherein the substrate has a thickness of 25 microns.
5. A method for manufacturing a lateral IGBT with low leakage using a lateral IGBT with low leakage according to any one of claims 1 to 4, comprising:
an N-type heavily doped silicon layer is epitaxially grown on the substrate to form a first N+ buffer layer;
epitaxially forming the drift layer over the first n+ buffer layer;
forming the N+ region, the P+ region, the second N+ buffer layer and the body region on the upper layer of the drift layer by ion implantation;
a gate, a collector and an emitter are deposited.
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Publication number Priority date Publication date Assignee Title
CN1925158A (en) * 2005-08-30 2007-03-07 日产自动车株式会社 Semiconductor device
CN108258040A (en) * 2017-12-26 2018-07-06 西安电子科技大学 Igbt with wide band gap semiconducter substrate material and preparation method thereof
CN108365006A (en) * 2018-02-10 2018-08-03 重庆大学 A kind of high speed super-junction laterally insulated gate bipolar transistor
CN110010678A (en) * 2018-01-04 2019-07-12 中兴通讯股份有限公司 Lateral insulated gate bipolar transistor and preparation method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2495949B (en) * 2011-10-26 2015-03-11 Anvil Semiconductors Ltd Silicon carbide epitaxy

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1925158A (en) * 2005-08-30 2007-03-07 日产自动车株式会社 Semiconductor device
CN108258040A (en) * 2017-12-26 2018-07-06 西安电子科技大学 Igbt with wide band gap semiconducter substrate material and preparation method thereof
CN110010678A (en) * 2018-01-04 2019-07-12 中兴通讯股份有限公司 Lateral insulated gate bipolar transistor and preparation method thereof
CN108365006A (en) * 2018-02-10 2018-08-03 重庆大学 A kind of high speed super-junction laterally insulated gate bipolar transistor

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