CN117497418A - Technological method of super-junction MOSFET cell structure - Google Patents

Technological method of super-junction MOSFET cell structure Download PDF

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Publication number
CN117497418A
CN117497418A CN202311277951.9A CN202311277951A CN117497418A CN 117497418 A CN117497418 A CN 117497418A CN 202311277951 A CN202311277951 A CN 202311277951A CN 117497418 A CN117497418 A CN 117497418A
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epitaxial layer
type epitaxial
layer
type
cell structure
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李东升
马彪
高伟
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Shanghai Lanxin Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H01L21/041—Making n- or p-doped regions
    • H01L21/0415—Making n- or p-doped regions using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

The invention discloses a super-junction MOSFET cell structure and a process method, wherein the super-junction P column is formed by injecting light-atomic-weight N-type impurities to invert a P-type epitaxial layer; the light-weight N-type impurity can form deeper P column under the same injection energy to form deeper P column super junction structure, the process is simplified, the product reliability is higher, and the cost is lower.

Description

Technological method of super-junction MOSFET cell structure
Technical Field
The invention relates to the field of semiconductor devices and process manufacturing, in particular to a process method of a super-junction MOSFET cell structure based on a silicon carbide substrate.
Background
The SiC MOSFET technology is a power semiconductor device technology based on silicon carbide materials, has excellent characteristics of high temperature, high voltage, high frequency and the like, and gradually becomes one of research hot spots of next-generation power electronic devices.
Silicon carbide has long been considered to have unique characteristics that make it superior to other commonly used semiconductor materials such as silicon (Si), gallium arsenide (GaAs), and indium phosphide (InP) formed semiconductor devices. Silicon carbide has a wide band gap, a high melting point, a low dielectric constant, a high breakdown field strength, a high thermal conductivity, and a high saturated electron drift velocity. These characteristics make it possible for devices made of silicon carbide to operate at higher temperatures, higher operating frequencies, and higher power levels, as well as other devices made of other semiconductor materials. Silicon carbide is a subverted technology, and with the development of new energy automobiles and photovoltaic energy storage fields, silicon-based technology is being replaced, and the silicon carbide is beginning to be widely focused on the market. The process and structure of SiC MOSFETs of different manufacturers are continually advancing, and product performance is continually improving.
The device structure of the SiC MOSFET mainly comprises: a channel region, source and drain regions, and a gate region. The channel region is composed of P-type SiC, the source region is composed of N+ type SiC, the drain region is composed of an N+ doped SiC substrate and a metal contact layer, and the gate region is composed of metal or polysilicon (Poly).
A vertical channel SiC MOSFET has a low on-resistance and a high temperature range formed on the front side of a silicon carbide substrate, an N-drift layer formed over an N+ substrate, and then a P-channel layer. The trench gate penetrates the P-channel layer and forms an n+ source region. The metal source and drain electrodes are located at the top and bottom of the die, respectively. This trench architecture is sometimes referred to as a UMOS (U-shaped gate) to distinguish it from a planar DMOS (VDMOS) design.
Since 2010, the silicon carbide power MOSFET market has expanded significantly, and as SiC has replaced silicon technology in multiple markets such as automobiles, photovoltaics, railways, etc., many new participants have entered the market, hopefully achieving a two-digit composite annual growth rate. Typically, siC power MOSFETs operate at 1200 or 1700V, which is intended to replace IGBT technology in some areas.
At present, the planar SiC MOSFET technology is switched to a trench gate structure through gradual development, the cell size can be reduced to 2um, and the structure cell size of a TMOS trench SiC MOSFET can also reach 3.3um.
In recent years, siC MOSFET technology has been developed, mainly in the following aspects:
1. the device performance is improved: by optimizing the technological process of the SiC MOSFET and the pitch (cell) structure of the device, such as a groove structure, a superjunction structure and the like, the performance improvement of the SiC MOSFET, such as low leakage current, high switching speed, low on-resistance, low switching loss and the like, is realized.
2. Improvement of packaging technology: packaging technology is one of the important factors affecting SiC MOSFET performance and reliability. At present, common SiC MOSFET packaging technologies comprise TO-220, TO-247, D2PAK and the like, and the latest packaging technologies adopt high-end technologies such as SiC substrate, silver-free solder, sintering and the like, so that the working junction temperature and heat dissipation performance of the device can be effectively improved.
3. Application expansion: siC MOSFET technology is widely used in the fields of electric automobiles, solar inverters, wind energy inverters, high-speed trains, power grid power transmission, and the like. As technology continues to develop, siC MOSFETs will find application in more application scenarios.
The specific on-resistance (Ron, sp) is an important index for evaluating the performance of a unipolar power device, and the physical meaning is that the on-resistance of the device is multiplied by the area of an active area (effective on-area) of a chip, and the smaller the value is, the higher the technical level is, namely the smaller the area of the chip required by the product with the same on-resistance is.
The super junction (super junction) structure is a structure of alternately arranged N-type columns and P-type columns. If the super junction structure is used to replace an N-type drift region in a VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor) device, a turn-on path is provided in an on state (only an N-type pillar provides a path, and a P-type pillar does not provide a path), and a reverse bias voltage is applied in an off state (PN pillars are commonly applied), so that the super junction MOSFET is formed. The super junction MOSFET can greatly reduce the on-resistance of the device by using an epitaxial layer with low resistivity under the condition that the reverse breakdown voltage is consistent with that of a traditional VDMOS device. In the superjunction structure, the N-type impurity distribution in the N-type pillar, the P-type impurity distribution in the P-type pillar, and the matching of the N-type impurity distribution in the N-type pillar and the P-type impurity distribution in the P-type pillar, which are alternately arranged, may affect the characteristics of the superjunction semiconductor device, including the reverse breakdown voltage and avalanche current tolerance and turn-off characteristics thereof. The general super-junction semiconductor device adopts a design that the N-type upright posts and the P-type upright posts which are alternately arranged reach the optimal charge balance so as to obtain the maximum reverse breakdown voltage, but the avalanche current tolerance of the device is insufficient under the condition, and the time is too short in the turn-off process, so that the oscillation of a loop in the application is easy to be caused, the electromagnetic interference of an application system is large, and even the circuit is damaged.
Minimizing the cell size of MOSFET devices while ensuring device performance is a direction of industry effort. A conventional planar SiC MOSFET cell structure is shown in FIG. 1, in which the cell structure shown in FIG. 1 is a trench gate structure in order to reduce the specific on-resistance of the device, and P-type pillar structures are formed on both sides of the trench in order to reduce the gate oxide electric field strength.
In the prior art, the fabrication process of the cell structure of the trench gate structure in fig. 1 is to implant AL on both sides of the trench to form a P-type Pillar (P-pilar) structure, which serves to reduce the field of the trench gate oxide. Because the atomic weight of AL is larger, the junction depth of implantation is generally 0.5-2.0 um, the depth is not very large, and the effect is not ideal.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a super-junction MOSFET cell structure with higher performance and reliability.
The invention also solves the technical problem of providing a process method for manufacturing the super-junction MOSFET cell structure.
In order to solve the above problems, the present invention provides a super junction MOSFET cell structure, which comprises:
the super junction MOSFET is formed in an epitaxial layer on a semiconductor substrate, and the epitaxial layer comprises an N-type epitaxial layer on the lower layer and a P-type epitaxial layer positioned on the N-type epitaxial layer; the thickness of the P-type epitaxial layer is determined by the injection depth of the N-type impurities;
the P-type epitaxial layer comprises a gate groove, and the inner wall of the gate groove covers the gate dielectric layer and is filled with polysilicon to form a trench gate;
the super junction structure of the super junction MOSFET cell structure is arranged on two sides of the grid electrode groove, the super junction structure is that the P type epitaxial layer of the injection area is inverted to be N type through high-energy N type ion injection in the P type epitaxial layer, and the rest P type epitaxial layers form a super junction P column.
The doping concentration of the epitaxial layer is 8E 15-1E 16CM -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the N-type epitaxial layer is 3-10 um, and the thickness of the P-type epitaxial layer is 2-7 um; the combined total thickness of the N-type epitaxial layer and the P-type epitaxial layer is 10-12 um.
The concentration of the N-type epitaxial layer and the concentration of the P-type epitaxial layer are consistent, or the N-type epitaxial layer and the P-type epitaxial layer are multiple layers of P-type epitaxial layers with different doping concentrations or graded doping concentrations; the thickness of the P-type epitaxial layer depends on the implantation energy of the ion implanter, and when the implantation energy of the ion implanter is higher, the P-type epitaxial layer adopts a thicker thickness to realize a deeper P column.
The technological method of the super junction MOSFET cell structure comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a front surface and a back surface opposite to the front surface; the front surface of the semiconductor substrate is also covered with an N-type epitaxial layer; forming a P-type epitaxial layer on the surface of the N-type epitaxial layer;
forming a first hard mask layer, performing photoetching and etching processes, opening an injection window of an N+ injection region of an active region on the hard mask, and performing ion injection to form a heavily doped N-type injection region; then opening an injection window of a P+ injection region of the active region on the hard mask, and performing ion injection to form a heavily doped P-type injection region;
depositing a second hard mask layer, opening an injection region of the super junction structure of the second hard mask layer, and injecting high-energy N-type ions into the P-type epitaxial layer to enable the inversion of the injection region to be N-type, wherein the rest P-type epitaxial layers outside the injection region form a super junction P column;
and finishing the manufacture of the trench gate, and forming a front-side interconnection and a back-side process.
Further, the semiconductor substrate and the epitaxial layer comprise a silicon carbide substrate or a gallium nitride substrate and a germanium-silicon substrate; the outer partThe doping concentration of the extension layer is 8E 15-1E 16CM -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the N-type epitaxial layer is 3-10 um, and the thickness of the P-type epitaxial layer is 2-7 um; the thickness of the P-type epitaxial layer is determined according to the injection depth of the N-type impurity; the combined total thickness of the N-type epitaxial layer and the P-type epitaxial layer is 10-12 um.
Further, the concentrations of the N-type epitaxial layer and the P-type epitaxial layer are consistent, or the N-type epitaxial layer and the P-type epitaxial layer are multiple layers of P-type epitaxial layers with different doping concentrations or graded doping concentrations.
Further, the second hard mask layer is made of metal, and the thickness of the second hard mask layer is 2-5 um.
Further, the metal material is nickel.
Further, the second hard mask layer is a silicon oxide layer or a polysilicon layer, and when high-energy N-type ion implantation is performed, a thicker thickness is required to use the silicon oxide layer or the polysilicon layer as the second hard mask layer.
Further, the process of forming the front-side interconnection and the back-side process includes:
depositing a third hard mask layer, photoetching and etching an etching window of the groove, etching the epitaxial layer to form a grid groove of the super-junction MOSFET cell structure, and depositing a sacrificial oxide layer and a grid dielectric layer; filling polycrystalline silicon in the grid electrode groove and etching back to form a groove grid electrode of the super-junction MOSFET cell structure;
depositing an interlayer medium, forming a source electrode leading-out contact hole, forming a contact leading-out silicide and annealing; forming a contact lead-out of a trench gate; depositing a metal layer and etching to form a front interconnection; depositing a passivation layer;
and carrying out a wafer back thinning process, and depositing a back metal layer to form a back electrode.
Further, the high-energy N-type ion implantation is nitrogen ions with smaller atomic weight; deeper depths can be implanted at the same implant energy, with a correspondingly deeper P-pillar.
The super-junction pitch structure is innovative in that the forming process is not to form a P-type Pillar structure by injecting AL, but to form an inverted P-type epitaxial layer by injecting nitrogen (N); the same implantation energy can form deeper pilar due to lower atomic weight of nitrogen (N), and can form deeper P-Pillar (pilar) superjunction SiC MOSFETs; on the basis of optimizing the specific on-resistance, compared with a multilayer epitaxial super-junction pitch structure, the method has lower cost and simpler process flow.
Drawings
Fig. 1 is a schematic diagram of a superjunction process for forming P-pillars by Al implantation in the prior art, in which the depth of the formed P-pillars is shallow.
Fig. 2 is a schematic diagram of a super junction structure of a P column formed by N ion implantation according to the present invention, in which the N ion has a smaller mass and a deeper P column can be formed at the same implantation energy.
FIG. 3 is a flow chart of the process of the present invention.
Description of the reference numerals
1 is an epitaxial layer (1-1 is an N-type epitaxial layer, 1-2 is a P-type epitaxial layer), 2 is a superjunction P column, 3 is a gate dielectric layer, 4 is a body region, 5 is a source region, and 6 is polysilicon (gate).
Detailed Description
The following description of the embodiments of the present invention will be given with reference to the accompanying drawings, in which the technical solutions of the present invention are clearly and completely described, but the present invention is not limited to the following embodiments. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. Advantages and features of the invention will become more apparent from the following description and from the claims. It is noted that the drawings are in a very simplified form and use non-precise ratios for convenience and clarity in assisting in illustrating embodiments of the invention. All other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present invention.
This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for the same elements throughout. In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The super junction MOSFET cell structure adopts a super junction structure. The super junction structure is formed by forming a plurality of P-type columnar structures in an N-type epitaxial layer (the structure is the same but the manufacturing method is different). And staggered comb-tooth-shaped structures are formed between the plurality of P-type columnar structures and the N-type epitaxial layer at intervals. According to the invention, a layer of P-type epitaxial layer with a certain thickness is formed on the N new epitaxial layer, then N-type nitrogen ions with lighter weight are injected through an ion injection process, under the same injection energy, the lighter nitrogen ions can reach deeper injection depth than the traditional AL ion injection, N-type nitrogen ions are injected into the P-type epitaxial layer under a high-energy and high-dosage window, so that the P-type epitaxial layer under the injection window is reversely N-type, and a P-type column which can be relatively deeper is formed on the P-type epitaxial layer outside the inversion region. The structure of which is shown in figure 2.
The technological method of the super junction MOSFET cell structure is as follows:
a semiconductor substrate may be provided, which includes a silicon substrate, a silicon germanium substrate, a gallium nitride substrate, a silicon carbide substrate, or the like. The invention is not limited to the material of the semiconductor substrate. In this specification, a silicon carbide substrate is described as an example. The thickness of the SiC substrate is 300um, and the doping concentration is 0.01-0.02 ohm cm -3 . The substrate is covered with an N-type epitaxial layer, and the sum of the thickness of the N-type epitaxial layer and the depth of the P column is kept at10-12 um. The doping concentration of the N-type epitaxial layer is 8E 15-1E 16cm -3 . In a process flow, it is assumed that the thickness of the N-type epitaxial layer is set to be 5um (3-10 um), a P-type epitaxial layer with a thickness of 5um is further epitaxially grown on the N-type epitaxial layer of SiC, aluminum (Al) is doped (the thickness range is 2-7 um, the thickness of the P-type epitaxial layer is determined according to the implantation depth of N-type (nitrogen N), the general empirical value is 4Mev approximately 3um,10Mev approximately 7 um), and the total thickness after the two epitaxial layers are overlapped is 10 um). For the 1200V SiC MOSFET,N type epitaxial layer and the P type epitaxial layer, the superposition thickness of the two layers of epitaxial layers is 10-12 um, and for the 750V SiC MOSFET,N type epitaxial layer and the P type epitaxial layer, the superposition thickness of the two layers of epitaxial layers is 6-8 um.
The doping concentration of the N-type epitaxial layer and the P-type epitaxial layer can be consistent, and the N-type epitaxial layer and the P-type epitaxial layer can also be formed by a plurality of layers of epitaxial layers with different doping concentrations or graded doping concentrations.
Depositing a hard mask layer, patterning the hard mask layer through photoetching and etching processes, and opening an ion implantation window of an N+ region of the active region to form an N+ ion implantation region; the N+ ion implantation region is used as a source region and a drain region of the MOSFEI device; and opening the P+ ion implantation region by using a hard mask again, and performing heavily doped P-type ion implantation to form a P+ implantation region, wherein the P+ implantation region is used as a P-type extraction region of the MOSFET device.
And depositing a metal layer, and forming a patterned metal hard mask layer through photoetching and etching processes, wherein an injection window opened by the metal hard mask layer is used for forming a super junction P column. When the implantation window opened by the metal hard mask layer is used for carrying out ion implantation to form a P column, the implanted ions are implanted into the metal hard mask layer by high-energy N-type nitrogen to form the P column, and the same implantation energy can form a deeper P column and a SiC MOSFET with a deeper P column (Pliar) super junction structure, so that the specific on-resistance of the device can be greatly optimized. The super junction SiC MOSFET structure can be realized at lower cost by forming the P-type Pillar through one-time injection. The ion implantation energy can be continuously adjusted in the process of N-type nitrogen ion implantation, so that the nitrogen ions are uniformly distributed in the depth range. Finally, the P column and the high-energy injection N type (nitrogen) are injected to reach charge balance in the transverse direction; the charge balance only needs to match the concentration distribution of the P-type epitaxial layer by different implantation energies and different implantation doses to achieve complete charge balance.
And etching the substrate by taking the hard mask layer as a shielding layer to form a groove, wherein the groove is used for forming a groove grid electrode. After the groove etching is finished, a sacrificial oxide layer is formed on the inner wall of the groove, polysilicon is filled in the groove, and the groove is etched back, so that the groove grid electrode of the super junction MOSFET is formed.
Depositing a dielectric layer ILD, completing etching of a contact hole of the source electrode lead-out and performing nickel silicidation to form a contact lead-out of the source electrode; forming a gate lead-out by performing contact etching on the polysilicon gate; and forming a front passivation layer after completion to protect the front structure of the substrate.
And performing a back side process, including a back side thinning process, depositing back side metal, and forming the drain electrode of the MOSFET.
The super-junction cell structure is technically characterized in that the P column forming process is not a P-type Pillar structure formed by injecting AL in the traditional process, but a P column super-junction structure is formed by injecting N-type nitrogen (N) inversion P-type epitaxial layer. The same implantation energy can form deeper pilar due to lower atomic weight of nitrogen (N), form a deeper P column (Pliar) super junction structure of the SiC MOSFET, and compared with a super junction structure formed by multi-layer epitaxy multi-layer implantation, the N type and P type epitaxy can be formed at one time in an epitaxy factory, so that the process is simplified, the reliability of the product is higher, and the cost is lower.
The depth of the P-type epitaxial layer P-pillar (the epitaxy process is achieved by doping Al) (Pliiar) depends on the depth of the nitrogen (N) implant, i.e. the highest implant energy of the ion implanter, and thus the P-type epitaxial layer thickness defined by the present invention depends on the maximum implant energy of the ion implanter used. The thickness of the P-type epitaxial layer is 3-7 um in the invention, which is obtained under the implantation energy of 10Mev, and if the ion implantation energy is higher, the P-type epitaxial layer can be correspondingly thicker.
In the process of forming the P column by implanting high-energy ion nitrogen (N), because the ion implantation energy is Mev, the Hard mask has higher requirements, and metal Hard mask photoetching, such as nickel Ni 2-5 um, can be adopted; the actual thickness is determined by the implant maximum energy level. Hard masks, if made of silicon dioxide or polysilicon, require a greater thickness and are more difficult to implement.
The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (11)

1. A process method of a super junction MOSFET cell structure is characterized in that: comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a front surface and a back surface opposite to the front surface; the front surface of the semiconductor substrate is also covered with an N-type epitaxial layer; forming a P-type epitaxial layer on the surface of the N-type epitaxial layer;
forming a first hard mask layer, performing photoetching and etching processes, opening an injection window of an N+ injection region of an active region on the hard mask, and performing ion injection to form a heavily doped N-type injection region; then opening an injection window of a P+ injection region of the active region on the hard mask, and performing ion injection to form a heavily doped P-type injection region;
depositing a second hard mask layer, opening an injection region of the super junction structure of the second hard mask layer, and injecting high-energy N-type ions into the P-type epitaxial layer to enable the inversion of the injection region to be N-type, wherein the rest P-type epitaxial layers outside the injection region form a super junction P column;
and finishing the manufacture of the trench gate, and forming a front-side interconnection and a back-side process.
2. The process of claim 1, wherein the super junction MOSFET cell structure comprises: the semiconductor substrate and the epitaxial layer comprise a silicon carbide substrate or a gallium nitride substrate and a germanium-silicon substrate; the doping concentration of the epitaxial layer is 8E 15-1E 16CM -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the N-type epitaxial layer is 3-10 um, and the thickness of the P-type epitaxial layer is 2-7 um; the thickness of the P-type epitaxial layer is based on the injection of N-type impuritiesDepth of penetration; the combined total thickness of the N-type epitaxial layer and the P-type epitaxial layer is 10-12 um.
3. The process of claim 1, wherein the super junction MOSFET cell structure comprises: the concentration of the N-type epitaxial layer and the concentration of the P-type epitaxial layer are consistent, or the N-type epitaxial layer and the P-type epitaxial layer are multiple layers of P-type epitaxial layers with different doping concentrations or graded doping concentrations.
4. The process of claim 3, wherein the super junction MOSFET cell structure comprises: the second hard mask layer is made of metal and has a thickness of 2-5 um.
5. The process of claim 4, wherein the super junction MOSFET cell structure comprises: the metal material is nickel.
6. The process of claim 1, wherein the super junction MOSFET cell structure comprises: the second hard mask layer is a silicon oxide layer or a polysilicon layer, and when high-energy N-type ion implantation is performed, a thicker thickness is required by taking the silicon oxide layer or the polysilicon layer as the second hard mask layer.
7. The process of claim 1, wherein the super junction MOSFET cell structure comprises: the process for forming the front interconnection and the back comprises the following steps of:
depositing a third hard mask layer, photoetching and etching an etching window of the groove, etching the epitaxial layer to form a grid groove of the super-junction MOSFET cell structure, and depositing a sacrificial oxide layer and a grid dielectric layer; filling polycrystalline silicon in the grid electrode groove and etching back to form a groove grid electrode of the super-junction MOSFET cell structure;
depositing an interlayer medium, forming a source electrode leading-out contact hole, forming a contact leading-out silicide and annealing; forming a contact lead-out of a trench gate; depositing a metal layer and etching to form a front interconnection; depositing a passivation layer;
and carrying out a wafer back thinning process, and depositing a back metal layer to form a back electrode.
8. The process of claim 1, wherein the super junction MOSFET cell structure comprises: the high-energy N-type ion implantation is nitrogen ions with smaller atomic weight; deeper depths can be implanted at the same implant energy, with a correspondingly deeper P-pillar.
9. The super junction MOSFET cell structure is characterized in that: the super junction MOSFET is formed in an epitaxial layer on a semiconductor substrate, and the epitaxial layer comprises an N-type epitaxial layer on the lower layer and a P-type epitaxial layer positioned on the N-type epitaxial layer; the thickness of the P-type epitaxial layer is determined by the injection depth of the N-type impurities;
the P-type epitaxial layer comprises a gate groove, and the inner wall of the gate groove covers the gate dielectric layer and is filled with polysilicon to form a trench gate;
the super junction structure of the super junction MOSFET cell structure is arranged on two sides of the grid electrode groove, the super junction structure is that the P type epitaxial layer of the injection area is inverted to be N type through high-energy N type ion injection in the P type epitaxial layer, and the rest P type epitaxial layers form a super junction P column.
10. The superjunction MOSFET cell structure of claim 9, wherein: the doping concentration of the epitaxial layer is 8E 15-1E 16CM -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the N-type epitaxial layer is 3-10 um, and the thickness of the P-type epitaxial layer is 2-7 um; the combined total thickness of the N-type epitaxial layer and the P-type epitaxial layer is 10-12 um.
11. The superjunction MOSFET cell structure of claim 10, wherein: the concentration of the N-type epitaxial layer and the concentration of the P-type epitaxial layer are consistent, or the N-type epitaxial layer and the P-type epitaxial layer are multiple layers of P-type epitaxial layers with different doping concentrations or graded doping concentrations; the thickness of the P-type epitaxial layer depends on the implantation energy of the ion implanter, and when the implantation energy of the ion implanter is higher, the P-type epitaxial layer adopts a thicker thickness to realize a deeper P column.
CN202311277951.9A 2023-09-28 2023-09-28 Technological method of super-junction MOSFET cell structure Pending CN117497418A (en)

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