CN117494648A - Multichannel analog signal gathers micro-assembly circuit board - Google Patents
Multichannel analog signal gathers micro-assembly circuit board Download PDFInfo
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- CN117494648A CN117494648A CN202311272239.XA CN202311272239A CN117494648A CN 117494648 A CN117494648 A CN 117494648A CN 202311272239 A CN202311272239 A CN 202311272239A CN 117494648 A CN117494648 A CN 117494648A
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- 230000008054 signal transmission Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000012858 packaging process Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 14
- 238000013461 design Methods 0.000 abstract description 10
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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Abstract
The invention discloses a multichannel analog signal acquisition micro-assembly circuit board, which relates to the technical field of data acquisition and comprises at least one double-channel ADC (analog-to-digital converter), a clock buffer and a rewiring layer, wherein external interfaces of the double-channel ADC converter and the clock buffer are led to the surface of the rewiring layer, the double-channel ADC converter is used for acquiring and processing analog signals and outputting converted digital signals externally, and the clock buffer is used for providing sampling clocks for the double-channel ADC converter through the rewiring layer. The invention uses rewiring technology to combine FANOUT technology and RDL-First technology, reduces the volume of the micro component through the substrate-free design, reduces the weight of the micro component, improves the product yield through the RDL-First technology, and further simplifies the design of peripheral circuits by an internally integrated clock buffer, thereby meeting the requirements of miniaturization of new-generation aerospace devices and equipment.
Description
Technical Field
The invention relates to the technical field of data acquisition, in particular to a multichannel analog signal acquisition micro-assembly circuit board.
Background
In the 5G era of today, the miniaturization of equipment and the high integration of equipment functions become the great direction of industry development, the concept of "data king" is deep, and the demand for faster, smaller and more powerful data acquisition systems is induced.
However, the hardware design mode of the traditional digital signal acquisition system is to arrange a signal acquisition core chip, namely an AD converter chip and a corresponding configuration circuit on a PCB, so that the system is complicated to arrange and large in size, and the application scene of the system is limited. Such a set of analog signal acquisition systems is often cumbersome, with complex configuration circuitry, power supply circuitry.
In addition, clock distribution of high-speed IC devices has been a serious challenge, and high-speed logic devices often support sampling frequencies up to GHz, and therefore, have very high requirements on clock sources, and have severe requirements on level standards and jitter of clock signals.
Disclosure of Invention
Aiming at the problems and the technical requirements, the inventor provides a multichannel analog signal acquisition micro-assembly circuit board, and the technical scheme of the invention is as follows:
the utility model provides a multichannel analog signal gathers micro-assembly circuit board, includes at least one binary channels ADC converter, clock buffer and rewiring layer, and the external interface of binary channels ADC converter and clock buffer all leads to rewiring layer surface, and binary channels ADC converter is used for gathering and handling analog signal, the digital signal after the external output conversion, and clock buffer is used for providing the sampling clock to binary channels ADC converter through rewiring layer.
The external interface of the double-channel ADC converter comprises a SerDes interface supporting JESD204B protocol, a synchronous output interface and an analog input interface to realize external communication and information exchange; the analog input interface is used for two-way analog signal input, the SerDes interface is used for digital signal output, and the synchronous output interface is used for synchronous signal output.
The external interface of the clock buffer comprises a character clock interface and a reference clock interface, wherein the character clock interface is used for outputting LVDS character clocks required by JESD204B signal transmission protocols externally, and the reference clock interface is used as a clock signal input port of a phase-locked loop in the clock buffer.
The further technical scheme is that the external interfaces of the two-channel ADC converter and the clock buffer also comprise a power interface, a grounding interface, a working state indication interface and an SPI interface, wherein the working state indication interface is used for outputting the working state of the two-channel ADC converter or the clock buffer, and the SPI interface is used for configuring the working mode of the two-channel ADC converter or the clock buffer.
The further technical scheme is that the external interfaces of the double-channel ADC converter and the clock buffer are fanned out to the outside of the micro-assembly circuit board through rewiring and FANOUT process, and then are connected with external components.
The circuit board is manufactured by adopting an RDL-First technology.
The further technical scheme is that after the rewiring layer is obtained through processing, the double-channel ADC converter and the clock buffer are attached to one surface of the rewiring layer, and the ball is planted on the other surface through processing.
The further technical scheme is that the rewiring layer is formed by alternately superposing a plurality of dielectric layers and metal layers based on a wafer level packaging process.
The further technical scheme is that the model of the double-channel ADC converter is AD9680BCPZ-1000, and the model of the clock buffer is AD9516-1BCPZ.
The beneficial technical effects of the invention are as follows:
the invention adopts a double-channel ADC converter as a core, and a clock buffer is combined to obtain the multi-channel analog signal acquisition micro-component circuit board. The invention adopts a substrate-free design, and has the advantages that: (1) The rewiring technology is combined with the FANOUT process and the RDL-First process, so that the size of the circuit board is greatly reduced; (2) The low-jitter ultra-fast clock buffer is integrated inside, so that the design complexity of a peripheral circuit is simplified, and the requirements of miniaturization of new-generation aerospace devices and equipment are met; (3) The FOWLP (Fan-Out Wafer Level Packaging ) technology is adopted, the design and processing period is short, and the iteration of the product is fast; (4) Compared with the TSV technology, the RDL-First technology is adopted, and the product yield is further improved.
Drawings
Fig. 1 is a schematic block diagram of an eight-channel analog signal acquisition micro-component circuit board provided herein.
Fig. 2 is a three-view of an eight-channel analog signal acquisition micro-assembly circuit board provided herein.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings.
Referring to fig. 1 and 2, the embodiment of the present application provides a multi-channel analog signal acquisition micro-component circuit board, which includes four dual-channel ADC converters 1, one clock buffer 2 and a Rewiring (RDL) layer 3, wherein external interfaces (i.e. input and output ends) of all the dual-channel ADC converters 1 and the clock buffer 2 are led to the surface of the rewiring layer 3, and the dual-channel ADC converters 1 and the clock buffer 2 are interconnected through the rewiring layer 3. Optionally, the model of the dual-channel ADC converter 1 selected in this embodiment is AD9680BCPZ-1000, and the model of the clock buffer 2 is AD9516-1BCPZ, so that the dual-channel ADC converter 1 has the characteristic of high speed, and the clock buffer 2 has the characteristic of low jitter and ultra-high speed.
The double-channel ADC converter 1 is used as a core chip of a circuit board and is used for collecting and processing eight-channel analog signals and outputting converted digital signals to the outside. The external interfaces of the dual-channel ADC converter 1 comprise an analog input interface, a SerDes interface supporting JESD204B protocol, a synchronous output interface and other functional interfaces, so as to realize external communication and information exchange. The analog input interface is used for two-way analog signal input, the SerDes interface is used for digital signal output, and the synchronous output interface is used for synchronous signal output. The other functional interfaces comprise a power interface, a grounding interface, a working state indicating interface and an SPI interface, wherein the working state indicating interface is used for outputting the working state of the double-channel ADC converter, and the level logic of the interface is CMOS level and LVDS level, because the interface comprises a plurality of state indicating pins, the level logic of different pins is inconsistent, and the driving capability and the signal rate of the pins are different; the SPI interface is used for realizing the configuration of the dual-channel ADC converter 1, namely, the configuration of the dual-channel ADC converter 1 is realized through an external configuration circuit, the configuration circuit is not integrated in the circuit board, the design difficulty of the circuit board is reduced, and the volume of the circuit board is reduced.
The LVPECL interface of the Clock buffer 2 is used to provide a high-speed sampling Clock (Device Clock) to each two-channel ADC converter 1 through the rewiring layer 3. The external interfaces of the Clock buffer 2 comprise a Character Clock interface, a reference Clock interface and other functional interfaces, wherein the Character Clock interface is used for outputting LVDS Character clocks (Character Clock) required by the JESD204B signal transmission protocol externally, and the reference Clock interface is used as a Clock signal input port of a phase-locked loop in the Clock buffer and is used for inputting a reference Clock required by the Clock buffer. The other functional interfaces also comprise a power interface, a grounding interface, a working state indicating interface and an SPI interface, wherein the working state indicating interface is used for outputting the working state of the clock buffer, the SPI interface is used for realizing the configuration of the clock buffer 2, and the design difficulty of the circuit board is reduced and the volume of the circuit board is reduced.
Fig. 2- (a), (b) and (c) are top view, bottom view and side view of the circuit board respectively, and the specific dimensions of the circuit board are marked, the volume of the circuit board is 20mm x 1.34mm, the laying range of the implant ball 4 is 18mm x 18mm, the distance between two balls is 1.0mm, the diameter is 0.6mm, and the thickness of the rewiring layer 3 is 0.8mm. The circuit board is manufactured by adopting an RDL-First process, and specifically comprises the following steps: processing and preparing a rewiring layer 3 on a glass carrier plate, wherein the rewiring layer 3 is formed by alternately superposing a plurality of dielectric layers and metal layers based on a Wafer Level Packaging (WLP) process; after the single rewiring layer 3 is peeled off from the carrier plate, the four double-channel ADC converters 1 and the clock buffer 2 are attached to one surface of the rewiring layer 3, and the RDL is used for manufacturing the processing ball-planting 4 on the other surface.
The external interfaces of the two-channel ADC converter 1 and the clock buffer 2 are fanned out to the outside of the micro-component circuit board by rewiring and FANOUT technology, and then connected with external components. The invention uses rewiring technology to combine FANOUT technology and RDL-First technology, reduces the volume of the micro-assembly circuit board through the substrate-free design, reduces the weight of the micro-assembly circuit board, improves the product yield through the RDL-First technology, and further simplifies the peripheral circuit design by the internal integrated clock buffer, thereby meeting the requirements of miniaturization of new-generation aerospace devices and equipment.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present invention are deemed to be included within the scope of the present invention.
Claims (9)
1. The utility model provides a multichannel analog signal gathers micro-assembly circuit board which characterized in that includes at least one binary channels ADC converter, clock buffer and rewiring layer, binary channels ADC converter with the external interface of clock buffer all leads to rewiring layer surface, binary channels ADC converter is used for gathering and handling analog signal, the digital signal after the external output conversion, clock buffer is used for through rewiring layer provides the sampling clock for binary channels ADC converter.
2. The multi-channel analog signal acquisition micro-component circuit board according to claim 1, wherein the external interface of the dual-channel ADC converter comprises a SerDes interface supporting JESD204B protocol, a synchronous output interface, and an analog input interface to realize external communication and information exchange; the analog input interface is used for two-way analog signal input, the SerDes interface is used for digital signal output, and the synchronous output interface is used for synchronous signal output.
3. The multi-channel analog signal acquisition micro-component circuit board of claim 1, wherein the external interface of the clock buffer comprises a character clock interface and a reference clock interface, the character clock interface is used for outputting LVDS character clocks required by JESD204B signal transmission protocol externally, and the reference clock interface is used as a clock signal input port of a phase-locked loop in the clock buffer.
4. The multi-channel analog signal acquisition micro-component circuit board of claim 1, wherein the external interfaces of the two-channel ADC converter and the clock buffer each further comprise a power interface, a ground interface, an operating state indication interface and an SPI interface, wherein the operating state indication interface is configured to output an operating state of the two-channel ADC converter or the clock buffer, and the SPI interface is configured to configure an operating mode of the two-channel ADC converter or the clock buffer.
5. The multi-channel analog signal acquisition micro-component circuit board according to any one of claims 1-4, wherein the external interfaces of the two-channel ADC converter and the clock buffer fan out to the outside of the micro-component circuit board by rewiring and combining with a FANOUT process, and are connected with external components.
6. The multi-channel analog signal acquisition micro-component circuit board of claim 1, wherein the circuit board is fabricated using an RDL-First process.
7. The multi-channel analog signal acquisition micro-component circuit board according to claim 6, wherein after the rewiring layer is processed, the two-channel ADC converter and the clock buffer are attached to one surface of the rewiring layer, and the ball is processed on the other surface.
8. The multi-channel analog signal acquisition micro-component circuit board of claim 1, wherein the rewiring layer is a staggered stack of multiple dielectric layers and metal layers based on a wafer level packaging process.
9. The multi-channel analog signal acquisition micro-component circuit board of claim 1, wherein the dual-channel ADC converter is model AD9680BCPZ-1000 and the clock buffer is model AD9516-1BCPZ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311272239.XA CN117494648A (en) | 2023-09-27 | 2023-09-27 | Multichannel analog signal gathers micro-assembly circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311272239.XA CN117494648A (en) | 2023-09-27 | 2023-09-27 | Multichannel analog signal gathers micro-assembly circuit board |
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| Publication Number | Publication Date |
|---|---|
| CN117494648A true CN117494648A (en) | 2024-02-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311272239.XA Pending CN117494648A (en) | 2023-09-27 | 2023-09-27 | Multichannel analog signal gathers micro-assembly circuit board |
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- 2023-09-27 CN CN202311272239.XA patent/CN117494648A/en active Pending
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