JP2009246246A - Three-dimensional multilayer structure having low capacity through electrode and computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tree-dimensional multilayer structure having low capacity through electrodes that enables direct connection of an interconnect between chips through a buffer gate which is indispensable for conventional two-dimensional packaging by significantly reducing the capacitance of a through electrode of a semiconductor LSI chip and to provide a computer system that achieves much more low power dissipation by actively promoting low frequency by using the three-dimensional multilayer structure. <P>SOLUTION: In a semiconductor LSI chip having low capacity through electrodes, the periphery of the through electrode is insulated by electrodeposition type polyimide. An electric capacity is equal to or smaller than that originated from an interconnect of 1 mm or less in the LSI chip. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention has a heterogeneous multi-core architecture, such as a three-dimensional stacked structure in which stacked semiconductor LSI chips are connected through low-capacitance through electrodes, and a multi-core chip and a special-purpose processor having the three-dimensional stacked structure. It relates to a computer system.

  In recent years, multi-core chips that integrate multiple processors on an SoC and special-purpose processors (ASIP) that can pursue efficient processing by specializing processor cores in application fields have been proposed, and product development has progressed. Yes. Since these technologies can meet a wide range of technical needs for embedded systems, major developments can be expected in the future, centered on the information home appliances field, where Japan holds a global leadership.

  However, in multi-core chips and ASIPs, multiple cores developed on the premise of operating as a single processor, such as CPUs and DSPs, are integrated on the same chip. Increased operating frequency, such as the need for a compatible cache memory and the need to improve operating frequency and complicated on-chip bus circuits to avoid memory access bottlenecks caused by sharing of cache memory and on-chip memory In addition, an increase in power consumption due to additional circuits becomes a problem.

  Furthermore, the leakage current is increasing due to the miniaturization of the process technology, and there is a problem that the leakage exceeds the dynamic power consumption in the technology of 90 nm or less.

  In addition, by sharing and reusing software assets and hardware assets, platform technology has been proposed to improve development efficiency and design efficiency of embedded systems, and system-on-chip (SoC) development has been promoted. Yes. These platform technologies flexibly respond to the wide range of functions and performance requirements of information appliances in the information home appliance field, and also facilitate system deployment. However, the basic improvement in the performance of these platforms is an improvement in operating frequency and parallel processing by a plurality of processor cores, and an increase in power consumption becomes a problem. For this reason, a method of suppressing unnecessary energy consumption by dynamic frequency and power supply voltage control in units of functional blocks has been proposed.

  Further, the mainstream of multi-core is homogeneous multi-core in which a plurality of existing processors are integrated, and the software is load-balancing parallel programming. However, in the field of embedded systems, software development is easy and function-distributed programming suitable for highly reliable object orientation is desirable. Especially for low power consumption, high-efficiency heterogeneous multi-core is expected. Is done.

  By the way, when looking at the development of individual semiconductor chips, the ubiquitous electronics era represented by mobile phones, network home appliances, RFICs, etc., has entered a further downsizing of electronic devices, lower power consumption, and higher functionality. In particular, with regard to the power consumption of information equipment, the ratio of total power consumption in society as a whole is expected to increase rapidly with the spread of information equipment, leading to ultra-low power consumption technology for semiconductor chips. Expectation is great.

  In order to achieve this, downsizing of the LSI system is an essential technology. In recent years, in addition to the conventional method of two-dimensionally integrating electronic devices on a large-scale, high density, multiple LSI chips System-in-package (SiP) technology has been proposed and developed that enables large-scale, high-density integration in a three-dimensional manner using packaging technology, and allows one electronic system to be accommodated within the same dimensions as a single chip. Is underway. Since this technology can meet a wide range of technical needs for electronic systems, it can be expected to develop greatly in the future with the electronic packaging technology field as the core.

  However, in the SiP technology, the LSI chip is mounted using a conventional package using wire bonding connection, so signal amplification (buffer) for external connection corresponding to the capacitance of the bonding pad and the inductance of the bonding wire ) A circuit is required. Since these additional circuits are driven by a larger power supply voltage than the internal signal processing circuit, an increase in power consumption becomes a problem.

  On the other hand, research and development of 3D LSI chip stacking technology, in which LSI chips are directly stacked in 3D, is advanced as an advanced technology aimed at ultra-high speed, ultra-high density, and low power consumption. (See Patent Documents 1, 2, and 3). Since this technology is positioned as a technology that achieves ultimate high-density integration beyond the conventional planar integration technology, it has been attracting attention.

  In general, the power consumption P of a CMOS LSI gate is expressed by P = f · CL · V, where f is an operating frequency, CL is a load capacitance, and V is a power supply voltage. Of these, the present invention achieves low power consumption by reducing the operating frequency f by an architecture on firmware. There are two types of power supply voltage V for internal circuits and external interfaces, but they are almost fixed depending on the device and the usage environment. In the internal circuit, the power supply voltage and the load capacitance CL are determined by the device configuration, internal wiring, etc., and decrease with the progress of miniaturization.

  On the other hand, in the external interface connecting the LSI chips, the power supply voltage does not decrease so much and the load capacitance CL has a very large value. For example, using a 130nm-CMOS process technology and an LSI with 55 million transistors, the ratio of the power consumption cost of one external connection interface to one gate of the internal circuit is 100 assuming that the external load capacitance is 50pF. More than double. In addition, the ratio of the external connection interface to the total power consumption of such an LSI is about one third, and it can be seen that reducing the load capacity of the chip-to-chip connection is an important issue for reducing the power consumption.

  Therefore, by applying 3D LSI chip stacking, it is possible to reduce the load capacity of chip-to-chip connection, which greatly contributes to the realization of not only miniaturization but also a low power consumption system.

  In 3D LSI chip stack mounting, through electrodes are stacked and mounted on thin processed LSI chips, the distance between devices becomes extremely short, and the wiring length of the interface between chips can be greatly shortened. . Therefore, the load capacity can be greatly reduced. In addition, signal degradation and attenuation are almost eliminated, and a buffer circuit used for waveform shaping and amplification is not necessary, so that the circuit amount can be greatly reduced. Ultimately, a significant power saving effect is expected.

  There are still many issues to be solved regarding the research and development of 3D LSI chip stack packaging technology. However, three-dimensional stacking of memory LSIs such as DRAM and flash is steadily being developed for commercialization as an essential technology for exceeding the limit of planar integration (see Non-Patent Document 1). As for image sensors, MEMS elements, etc., examples of the production of through electrodes have been reported by various methods, and developments are being made with a view to a wide range of application fields.

  On the other hand, for three-dimensional integration of digital LSIs with high power consumption, such as DSP and CUP, heat dissipation becomes a major issue because power consumption doubles in proportion to the number of layers. Further, since it is necessary to improve the current supply capability in proportion to the number of layers for the power supply wiring, it is difficult to ensure stable supply.

In the heterogeneous multi-core chip described above, it is possible to reduce the clock frequency without degrading the calculation performance by linking different calculation IP cores in the LSI chip and effectively using the effective calculation function. As a result, a significant reduction in power consumption can be achieved. As a result, it is expected that the problem of heat dissipation will be solved, and the ratio of the power consumption in the buffer circuit in the above-described inter-chip interface to the power consumption of the entire LSI system will be apparently increased. For this, it is considered that the application of 3D LSI chip stacking which does not require an input / output buffer circuit due to a significant reduction in the capacity of the interface part will be an effective means to achieve the final reduction in power consumption. It is done.
JP 2003-243396 A JP 2003-309121 A JP 2002-299836 A Satoshi Matsui, et al., "Thermal Management in 8-Strata 4Gb DRAM SIP", 2007 Proceedings of IMPS 40th International Symposium on Microelectronics, 2007.11.11, pp.310-316.

  The present invention has been made in view of the above circumstances, and the capacitance of a fine through-via electrode formed on a semiconductor LSI chip is greatly reduced, which is essential for conventional two-dimensional mounting. The present invention provides a three-dimensional laminated structure having a low-capacitance through electrode, which enables direct connection of inter-chip wiring via a buffer gate, and further uses the three-dimensional laminated structure, It is easy to develop software and adopts function-distributed programming suitable for reliable object orientation, and can actively lower the frequency to achieve even lower power consumption. It is an object to provide a computer system having a heterogeneous multi-core chip with high processing efficiency.

  In order to solve the above-mentioned problems, the present invention firstly has a through electrode that is insulated by electrodeposition type polyimide, and has an electric capacity caused by wiring of 1 mm or less inside the LSI chip. A semiconductor LSI chip having a low-capacitance through electrode having the following values is provided.

  Second, the semiconductor LSI chip having a value equal to or less than the electric capacity of 0.1 pF is provided.

  Thirdly, the present invention provides a three-dimensional laminated structure having a low-capacitance through electrode formed by laminating a plurality of the semiconductor LSI chips on a substrate.

  Fourth, a multi-core chip computer system using a low-capacitance through electrode as a common bus on the semiconductor LSI chip is provided.

  Fifth, there is provided the multi-core chip computer system connected by a common bus including a clock by a tristate signal, a bus use request, an address, a command, data, and a status.

  Sixth, the present invention provides a three-dimensional stacked structure computer system, which is a processor for a specific application in which a plurality of the semiconductor LSI chips are stacked on a substrate, and each semiconductor LSI chip is designed for a different application. .

  Seventhly, the processor for each specific application has the instruction set according to the application, and provides the three-dimensional stacked structure computer system in which the format of data exchanged with each other is common.

  Eighth, the three-dimensional stacked structure computer system having a circuit for converting the endian in the bus interface is provided as means for sharing the data format.

  Ninth, the present invention provides the three-dimensional stacked structure computer system in which the exchange between the separately designed semiconductor LSI chips is automatically ensured.

  Tenth, the guarantee is performed by arbitrating access to the bus of each chip by a bus interface circuit based on the bus ID of each chip set at the time of stacking the chips. A computer system is provided.

  11thly, the said three-dimensional laminated structure computer system provided with the circuit which controls transmission / reception between the arbitrary semiconductor LSI chips of the data from which bit width differs is provided.

  Twelfth, the three-dimensional stacked structure computer system according to the present invention, which recognizes the setting of data having different bit widths as an initial setting.

  Thirteenth, the recognition is performed by reading information of each chip connected to the bus using the initialization mode by a system initialization program that operates on a host chip that is a host when the system is started. The three-dimensional laminated structure computer system is provided.

  Fourteenth, the information on each chip is at least one of product ID, vendor ID, class, subclass, data size, power supply, and current.

  Fifteenth, the three-dimensional stacked structure computer system, wherein the host chip has a master bus ID = 0, and in the initialization mode, the host host chip designates an access destination chip using the bus ID I will provide a.

  Sixteenth, there is provided the three-dimensional stacked structure computer system, wherein a distributed arbitration circuit is provided in each of the semiconductor LSI chips constituting the three-dimensional stacked structure.

  Seventeenth, the distributed arbitration circuit provides the three-dimensional stacked structure computer system including a master arbitration circuit for issuing a request and a slave arbitration circuit for receiving the request.

  Eighteenth, the three-dimensional stacked structure computer system is provided, wherein the master arbitration circuit is mounted on a bus master chip that spontaneously accesses another chip using a bus interface.

  Nineteenth, the three-dimensional stacked structure computer system is provided in which the bus master chip is a processor chip.

  20thly, the slave arbitration circuit is mounted on a bus slave chip accessed from another chip using a bus interface), and provides the three-dimensional stacked structure computer system.

  Twenty-first, the three-dimensional stacked structure computer system according to the present invention, wherein the bus slave chip is a memory.

  Twenty-second, the arbitration circuit has the unique ID, and provides the three-dimensional stacked structure computer system.

  In the 23rd, a semiconductor LSI chip constituting a three-dimensional stacked structure is composed of at least one of a core processor, a memory, wireless communication, an interface, a sensor, a man-machine interface, and a cryptographic processing chip, and is controlled by a distributed parallel processing program. The three-dimensional laminated structure computer system is provided.

  24thly, each semiconductor chip provides the said three-dimensional laminated structure computer system which has an initialization program for computer system setting as a distributed parallel processing program.

  25thly, in the initialization program, the host chip creates a system address map based on the descriptor and bus ID, which are chip-specific information, and the base address and upper limit of each bus slave chip according to the system address map. The three-dimensional stacked structure computer system is provided for setting an address range defined by an address.

  Twenty-sixth, each bus slave chip provides the three-dimensional stacked structure computer system in which the address range of the bus slave chip is written to the bus interface circuit and access to the bus slave chip is detected.

  According to a twenty-seventh aspect of the present invention, there is provided the above three-dimensional stacked structure computer system in which the system is optimized by recognizing each other chip and performing an initialization operation after stacking the semiconductor chips constituting the three-dimensional stacked structure. .

  According to the present invention having the features as described above, the following effects can be realized.

1) Reduction of clock frequency By connecting core processor chips using a plurality of special-purpose instruction sets with a low-capacitance through-electrode bus and performing parallel operations, it is possible to improve the utilization efficiency of operation performance of each chip. The low-capacity through electrode bus can be directly connected to the internal bus of each chip, and the bus width can be easily expanded. As a result, the data transmission / reception amount between the chips can be increased without increasing the clock frequency, and the same performance as the conventional one can be easily achieved.

  Conventionally, the clock of the bus connected to another chip is one digit or more lower than the clock of the internal bus. However, in the present invention, since the same frequency can be applied in principle, the external system has limited the system performance. The bus clock frequency can be effectively increased, and the system performance can be improved without increasing the clock frequency.

2) Reduction of power consumption With the low-capacitance through electrode bus configuration, it is possible to eliminate the interface buffer circuit between each chip, which requires a large amount of power consumption in the conventional system, and the power consumption can be reduced.

  In addition, it is possible to execute optimum processing suitable for the purpose by applying the instruction set for specific use.

  Further, power consumption can be reduced by reducing the clock frequency.

  Furthermore, in the three-dimensional laminated structure, heat dissipation measures are important. However, according to the present invention, power consumption can be dramatically reduced, which is extremely advantageous for the laminated structure.

  Since the bus signal voltage can be reduced to the same level as the internal bus, power consumption can be reduced.

3) Suitable for large-capacity data processing Since the bus width between the processor and the memory can be increased, the data transfer capacity can be easily increased.

4) Wide flexibility of system construction method A desired system can be constructed by simply connecting variously designed chips with a low-capacitance through electrode bus regardless of the stacking order.

  The system program can be easily configured by using a common operation platform mounted on each chip.

5) Miniaturization By stacking, an n-chip function can be realized with an area of one chip.

6) Simplification of memory chip, high speed and large capacity Since an interface control circuit for speeding up external access which has been mounted on a conventional memory chip is not required, the memory area can be increased and the delay caused by this circuit can be reduced. Therefore, high speed and large capacity can be achieved.

  Here, the three-dimensional laminated structure of the present invention having the above characteristics will be described first.

  In the present invention, for the three-dimensional LSI chip stacking mounting technology, instead of the conventionally proposed silicon oxide film used for the insulating layer of the through electrode, a low-permittivity thick film electrodeposited polyimide is applied. Thus, the load capacity for chip-to-chip connection is reduced to 1/10 or less compared to conventional silicon oxide film insulation.

  Realizing a three-dimensional mounting bus connection interface that enables scalable connection between multiple stacks by configuring a broadband system bus using a large number of low-capacity through electrodes for inter-chip connection it can.

  This interface is based on heterogeneous multi-core and standardized by classifying the number of stacks and the number of connection pins, so that several different LSI chips aiming at high functions can be stacked three-dimensionally according to the application, and redesigned and redesigned. This means that the design can be performed while ensuring flexibility and expandability without development, and it is possible to dramatically expand the application range of the heterogeneous multi-core chip technology in the future.

  The present invention is assumed from the characteristics of the heterogeneous multi-core chip described above, and further reduction in power consumption is possible by combining the heterogeneous multi-core chip and a three-dimensional laminated structure having a low-capacitance through electrode. Make it smooth.

  More specifically, a three-dimensional laminated structure having a low-capacitance through electrode will be described in detail. Generally, when an electrodeposited polyimide is used for a multilayer wiring, a uniform insulating layer is selectively selectively applied to a specific portion by supplying power only to the wiring. Formation is possible. Accordingly, if the ground layer is formed uniformly after the insulating layer is formed, highly accurate control can be achieved with respect to the characteristic impedance of the wiring.

  On the other hand, the through via electrode provided in the LSI device is usually formed by the following procedure. A deep via hole with a large aspect ratio is formed on a silicon substrate, a silicon oxide film is formed on the sidewall of the via hole by CVD, etc., and a seed layer is further formed by sputtering, CVD, etc., and then Cu plating is used. Fill the via hole with metal.

  Electrodeposition type polyimide can be used in this via hole side wall insulating step. After the via hole is formed, a portion other than the hole is covered with a resist, and then the silicon substrate is powered to form a polyimide insulating layer by electrodeposition. After that, after forming a seed layer by sputtering or CVD as in the prior art, the via hole is filled with metal by Cu plating or the like. Electrodeposited polyimide can be formed in a short time even with a thickness of several tens of microns, and the low dielectric constant can be set to a value lower than that of a silicon oxide film.

  Up to now, with regard to improving the performance of semiconductor LSI devices, the degree of integration and processing speed have been improved by the advancement of microfabrication technology. However, as the leakage current increases due to the miniaturization of the transistor gate length, the consumption of useless power not involved in the operation is increasing. It is a major obstacle to achieving the goal of reducing the power consumption of electronic devices to meet the major proposition of CO2 reduction in advanced countries. On the other hand, the three-dimensional stacking technology can improve the degree of integration and processing speed regardless of miniaturization, so it has the potential to achieve low power consumption without increasing leakage current. This is considered a promising technology for reducing power consumption.

  In practical research and development related to the three-dimensional stacking of DRAM memory devices so far, a through hole is formed in a silicon substrate and polysilicon is used as a through electrode (see Non-Patent Document 1). Was about 2 pF / via. In order to improve the insulating property of the through electrode, an effort has been made to form an insulating layer such as SiO2 on the inner surface of the through via. However, since it is premised on providing an I / O gate similar to the chip for two-dimensional placement so far, there has been no discussion on aggressive reduction of capacitance, and it is at a level where devices such as circuits are devised. Not reached. Table 1 shows an example of calculation of the capacitance of the through electrode using SiO2 of the chip under good conditions and an example of calculation using the polyimide insulated through electrode in this proposal. The formation of a polyimide film by electrodeposition is easier to form with a film thickness of 1 μm or more than SiO 2, so that the capacity can be further reduced.

According to the present invention, an ultra-low capacitance that does not affect gate operation and signal transmission even when directly connected to a general LSI internal wiring (capacitance: about 100 fF) or gate (capacitance: about 1 fF). Through-hole via electrode technology can be established. This makes it possible to construct a three-dimensional LSI stacked hard wafer system capable of realizing efficient logic design while ensuring expandability and flexibility, as well as simple connection such as connection between memory chips. As a result, it can make a big impact on a wide range of electronics companies, such as the field of portable electronic devices and robot control, where high-density, high-functionality, and high-efficiency low-power LSI system design is required.

In the current mainstream CMOS-LSI devices, power is consumed by charging / discharging the capacity of each gate and the capacity of the wiring connecting the gates. The power consumption at this time is expressed by P = fCV ² (f: operating frequency, C: capacitance of wiring (inside LSI and mounting system) and gate (inside LSI), V: operating voltage). At this time, the gate capacitance and the wiring capacitance are about 1 fF gate and 100 fF / mm, and can be estimated to be about several pico F in the bus line configuration. In addition, for packages on which devices are mounted and high-frequency strip wiring on printed circuit boards, high capacitance (2 to 4 pF / cm) due to long wiring leads to high driving voltage and high voltage in LSI devices. Had to put an operational I / O buffer gate. This buffer gate needs to have sufficient drive capability for external circuits. For example, in the case of a 100M gate level processor, assuming that an external bus line with a capacitance of 50 pF is driven, it is about 40% of the total power consumption. It will be estimated. In this proposal, as shown in Table 2, it is possible to reduce the capacitance of the through via wiring connecting 10 LSI chips to 1 pF or less, and this 40% power consumption required for the conventional interchip wiring can be reduced. It can be reduced to an almost negligible level. The present invention realizes a three-dimensional stacking technique that can achieve such low power consumption. The image is shown in FIG.

  Electrodeposited polyimide has so far been successful in forming highly reliable insulating films on various metals such as copper and gold, and has accumulated detailed data on the formation process. Already, for the purpose of producing a multilayer wiring structure, a study was conducted to form a smooth electrodeposited polyimide film with a film thickness of about 15 μm. As a result, it became possible to obtain a smooth surface by optimizing the stirring. It was. In addition, it has been confirmed that the reproducibility of film formation is improved and the film thickness can be controlled by the film formation time. Since a smooth insulating layer can be formed even with a thick film, it is possible to fabricate fine multilayer wiring using electrolytic copper plating and electrodeposited polyimide. Using this technology, the characteristic length is 22.4mm and the line width is 30μm. A microstrip line with approximately 50Ω is fabricated and its performance is verified.

  Next, a computer system according to the present invention will be described.

  In the present invention, by reducing the operating frequency of the chip, an unprecedented reduction in power consumption is achieved. The power consumption of the chip is P = 1/2 · α · C · V2 · f. By reducing the operating frequency f, the power consumption voltage V can be reduced by reducing the switching speed of the transistors on the chip, and the power consumption of the entire chip can be reduced by the cube of the operating frequency f. Can do.

  In order to reduce the operating frequency of the chip, the present invention realizes a heterogeneous multi-core architecture specialized for specific applications such as PHS terminals, network home appliances, and RFICs, and a collaborative design of its software algorithm. That is, for example, in the case of a PHS terminal, application software in parallel with defining multiple ASIP specifications for each of its communication functions, application processing functions such as calls and mails, web browsing, and display functions on the LCD By defining a function-distributed and efficient processing method for each function, the number of instruction steps required for each process is significantly reduced.

  Therefore, as a low power consumption-oriented heterogeneous multi-core architecture that realizes high processing capability even at a low operating frequency, the arithmetic processing capability per clock is improved and additional circuits that lead to increased power consumption are reduced. Therefore, the following approach is taken on the architecture.

(1) Shallow instruction execution pipeline: 4 to 5 stages Since the instruction execution pipeline is shallow, the branch penalty is relatively small. Therefore, a branch prediction circuit with many additional circuits is not installed.

(2) Instructions such as superscalar and VLIW are not processed in parallel. The effective parallelism of instructions is 3 to 4 instructions, and the increase in power consumption due to the additional circuit is considered to be more than that.

(3) Effective use of data parallel performance
The improvement of arithmetic processing per clock by data parallel by SIMD instructions and the like has an effect more than the increase of arithmetic circuits. Therefore, the data size (data path width) of each processor core mounted as a heterogeneous multi-core is N bits (32 bits, 64 bits, 128 bits, etc.) according to the application function.

(4) Addition of specialized instructions As application-specific instructions, arithmetic processing amount per clock is improved by implementation of arithmetic cascading and special circuits.

(5) Minimization of cache memory The cache memory has many additional circuits, leading to an increase in power consumption. Therefore, registers and local memory are used as much as possible instead of the cache memory.

(6) Improved locality of data and instructions From the viewpoint of low power consumption, it is advantageous in the order of register file <local memory <cache memory <shared on-chip memory <external memory. Therefore, optimization of register files and local memory in each processor, optimization of size of shared on-chip memory, optimization of interface with external memory, etc. To optimize for.

(7) Compact instruction code size Since a plurality of processor cores are mounted in a multi-core, the bandwidth required for instruction fetch is N times that of a single processor. For this reason, a cache memory or a program memory is provided on the chip, but the capacity and the power consumed by the bus between these memories and the processor are almost proportional to the instruction code size. Therefore, an instruction set architecture with a basic instruction length of 16 bits is defined to minimize the instruction code size of each processor core.

  The computer system of the present invention that employs the approach as described above further includes the following specific configuration.

  First, as illustrated in FIG. 2, for example, semiconductor LSI chip groups that are three-dimensionally stacked via the through electrodes illustrated in FIG. 1 are connected using a bus interface. A group of semiconductor LSI chips to be stacked includes a bus master chip that spontaneously accesses another chip and a bus slave chip that is accessed from another chip using a bus interface. The bus ID (a unique ID for each of the master chip and slave chip) is set for each chip, and access to the bus of each chip is arbitrated by the bus interface circuit based on this bus ID, and each designed separately Various exchanges such as data transmission / reception and program processing between chips are automatically secured. The bus interface circuit will be described later.

  For example, when sending and receiving data with different bit widths, the data transfer size requirement setting for each chip is connected to the bus using the initialization mode by the system initialization program that runs on the host chip that is the host when the system starts up. It is recognized by reading out information of each chip (for example, descriptors such as product ID, vendor ID, class, subclass, data size, power supply, current). The host chip has a bus ID = 0, and in the initialization mode, the host chip specifies an access destination chip using the bus ID.

  Each chip incorporates a distributed arbitration circuit as exemplified in FIG. The distributed arbitration circuit includes an arbitration circuit for a master chip that issues a request and an arbitration circuit for a slave chip that receives a request. For example, an arbitration circuit for a master is mounted on a bus master chip such as a processor chip, and an arbitration circuit for a slave is mounted on a bus slave chip as a memory. Of course, each arbitration circuit has a unique ID. The ID of each arbitration circuit can be given by the configuration illustrated in FIG. 4, for example.

  FIG. 5 shows an example of the arrangement of the semiconductor LSI chip and the through electrodes for power supply and common bus. In the example of FIG. 5, a plurality of through electrodes for a common bus are provided for the arbitration circuit on the chip, and a plurality of through electrodes for power supply are provided in the peripheral area of the chip. FIG. 6 shows an example of a method for assigning power to each laminated chip connected to the power supply through the power supply through electrode. The stacked semiconductor LSI chip group uses only the power supply electrode 1 for each chip during reset. During the reset, the host chip performs an initialization operation to read out current request information of each chip, and sets the number of the power supply electrode used by each chip as a configuration. An example of a power supply selection circuit performed based on the configuration setting in each chip is as shown in FIG. With the power supply allocation shown in FIGS. 6 and 7, after stacking the chips, the mutual chips can be recognized and an initialization operation can be performed to optimize the power supply electrode allocation.

By the way, the bus configuration is connected by a common bus including a clock by a tristate signal, a bus use request, an address, a command, data, and a status. A host chip having a master bus ID = 0 drives a clock signal. Each chip drives a corresponding bus use right request signal (specific example is FIG. 13) according to the bus ID. As a result of arbitration, the master chip that has acquired the bus use right drives the address signal and the command signal. The data signal is driven by the master chip that has acquired the right to use the bus in the case of writing or the slave chip specified by the address in the case of reading, depending on the direction of data transfer. The slave chip specified by the address drives the status signal.
FIG. 8 shows an example of the operation timing of the bus signal. In this example, one data transfer process is performed in three pipeline stages. First, in the first stage (S0: bus use request stage), each chip drives a bus use right request signal as necessary. The arbitration circuit built in each chip performs arbitration by the method shown in FIGS. 10 and 11 based on its own bus use right request signal and the bus use right request signal from another chip, and which chip uses the bus use right. Decide what to have. As a result of the arbitration, the chip that has acquired the bus use right drives the command signal and the address signal in the second stage (S1: bus request creation stage). Data transfer is performed in the third stage (S2: bus data transfer stage). In this three-stage pipeline processing, as shown in FIG. 8, one bus transfer is normally performed in one clock cycle of each stage.

  FIG. 9 shows an example of the bus use mode. In the normal (single transfer) mode, data is read and written only once in three stages of pipeline processing, and occupies one cycle as a bus cycle. In the split transfer mode, when the master chip reads data from the slave chip and the chip has a long access cycle in which data transfer from the slave chip cannot be performed in S2, the transfer is divided into two bus cycles. . In this case, the slave chip obtains the bus use right by driving the bus use right request signal at the timing when the read data can be prepared (in FIG. 8, in S0, the second Master-1 on the left and the Slave- 2. In S1, the second left read and the rightmost split, and in S2, the second left not yet and the rightmost ready). In the burst transfer mode, the chip that has acquired the bus use right locks the bus use right (drives the bus_lock signal in FIG. 13), thereby continuously securing the bus use right, thereby requiring a plurality of bus cycles. The stream data and the like can be transferred continuously. In the cyclic transfer mode, the right to use the bus is regularly acquired by using a high-priority bus use request in the case of transferring sampling data at a fixed cycle by an ADC (A / D converter). be able to.

  An example of arbitration of the bus use right is shown in FIG. A primary round robin is formed between master chips (processors), and an internal state indicating the master chip (processor) having the highest priority is held. If there is no bus use request from the slave chip according to this internal state, arbitration for giving the bus use right to the chip having the highest priority among the master chips that issued the bus use request (see FIG. 11) is performed. Do. The internal state of the next clock cycle efficiently turns round robin by making a transition to a state in which the next processor that has acquired the right to use the bus has priority level 1. Similarly, a secondary round robin is configured between slave chips. The result of the arbitration by the second round robin gives priority to the request from the slave chip in the split transfer mode or the cyclic transfer mode by giving a higher priority than the arbitration by the first round robin. Give usage rights.

  An example of priority control of the bus use right is shown in FIG. Here, regarding the bus use right n priority transition, state (2: 0) is retained when there is no bus use request, and state (2: 0) has acquired the bus use right when there is a bus use request. Transition to chip ID + 1. In addition to the example of the bus use mode in FIG. 8, the priority of the bus use right is adjusted by the slave outputting a bus request at a constant cycle in synchronization with the built-in timer for cyclic transfer. Realize regular transfers.

  FIG. 12 shows a chip mounting example of the common bus interface circuit. In this example, the common bus interface circuit includes an input / output port I / O, a data conversion circuit, a bus arbitration circuit, and a chip identification ID memory. A common bus signal is transmitted and received between the common bus through electrode arranged for the arbitration circuit of the LSI chip and the input / output port I / O of the common bus interface circuit. Data conversion processing such as endian conversion and data word length conversion for the common data format necessary for mutual communication is performed, and the bus arbitration circuit gives priority to the bus use right shown in FIGS. Access to the bus of each chip is arbitrated based on the degree control.

FIG. 13 shows a mounting example of bus signals (master: 8 chips, slave: 8 chips, 16 chips in total). The types in the figure are as follows.
A: Master: 0 drives. Other chips refer to them as input signals.
B: Each chip drives a corresponding signal line based on the ID, and refers to other signals as inputs.
C: A chip having the bus right or an access destination chip drives.

  The present invention having the above-described features can realize the following effects by combining a three-dimensional laminated structure having a low-capacitance through electrode and a heterogeneous multi-core chip.

1) Reduction of clock frequency 2) Reduction of power consumption 3) Suitable for large capacity data processing 4) Wide flexibility of system construction method 5) Miniaturization 6) Simplification of memory chip, high speed and large capacity

The figure which shows an example of the three-dimensional laminated structure using the low capacity | capacitance penetration electrode by this invention. The figure which shows an example of the three-dimensional laminated structure computer system by this invention. The figure which shows an example of a semiconductor LSI chip. The figure explaining ID provision of a semiconductor LSI chip. The figure which shows an example of penetration electrode arrangement | positioning. The figure which shows an example of power supply allocation. The figure which shows an example of the power supply selection circuit in each chip | tip. The figure which shows an example of the operation timing of a bus signal. The figure which shows an example of bus use mode. The figure explaining an example of arbitration of a bus use right. The figure which shows an example of priority control of a bus use right. The figure which shows an example of common bus interface circuit mounting. The figure which shows an example of bus signal mounting.

Claims (27)

  A semiconductor LSI chip having a low-capacitance through electrode, wherein the periphery of the through electrode is insulated by electrodeposited polyimide, and the electric capacity has a value less than or equal to the electric capacity caused by wiring of 1 mm or less inside the LSI chip.   The semiconductor LSI chip according to claim 1, wherein a value equal to or less than the electric capacity is 0.1 pF.   A three-dimensional laminated structure having a low-capacitance through electrode, wherein a plurality of semiconductor LSI chips according to claim 1 or 2 are laminated on a substrate.   A multi-core chip computer system using a low-capacitance through electrode as a common bus on the semiconductor LSI chip according to claim 1.   5. The multi-core chip computer system according to claim 4, wherein the multi-core chip computer system is connected by a common bus including a clock based on a tristate signal, a bus use request, an address, a command, data, and a status.   A three-dimensional stacked structure computer system, wherein a plurality of semiconductor LSI chips according to claim 1 or 2 are stacked on a substrate, and each semiconductor LSI chip is a special-purpose processor designed for different applications.   7. The three-dimensional stacked structure computer system according to claim 6, wherein each of the special purpose processors has an instruction set corresponding to the purpose, and has a common data format.   8. The three-dimensional stacked structure computer system according to claim 7, wherein a circuit for converting the endian is provided in the bus interface as means for sharing the data format.   7. The three-dimensional stacked structure computer system according to claim 6, wherein exchanges between separately designed semiconductor LSI chips are automatically secured.   10. The three-dimensional stacked structure computer according to claim 9, wherein the guarantee is performed by arbitrating access to the bus of each chip by a bus interface circuit based on the bus ID of each chip set at the time of stacking the chips. system.   The three-dimensional stacked structure computer system according to claim 6, further comprising a circuit for controlling transmission / reception of data having different bit widths between arbitrary semiconductor LSI chips.   The three-dimensional stacked structure computer system according to claim 10, wherein setting of data having different bit widths is recognized by an initial setting.   13. The recognition is performed by reading information of each chip connected to the bus using an initialization mode by a system initialization program that operates on a host chip that is a host at the time of system startup. Three-dimensional laminated structure computer system.   14. The three-dimensional stacked structure computer system according to claim 13, wherein the information of each chip is at least one of product ID, vendor ID, class, subclass, data size, power source, and current.   The three-dimensional stacked structure computer system according to claim 13, wherein the host chip has a master bus ID = 0, and in the initialization mode, the host chip specifies an access destination chip using the bus ID.   16. The three-dimensional stacked structure computer system according to claim 6, wherein a distributed arbitration circuit is provided in each of the semiconductor LSI chips constituting the three-dimensional stacked structure.   17. The three-dimensional stacked structure computer system according to claim 16, wherein the distributed arbitration circuit includes an arbitration circuit for a master that issues a request and an arbitration circuit for a slave that receives a request.   14. The three-dimensional stacked structure computer system according to claim 13, wherein the master arbitration circuit is mounted on a bus master chip that spontaneously accesses another chip using a bus interface.   19. The three-dimensional stacked structure computer system according to claim 18, wherein the bus master chip is a processor chip.   The three-dimensional stacked structure computer system according to claim 16, wherein the slave arbitration circuit is mounted on a bus slave chip accessed from another chip using a bus interface.   21. The three-dimensional stacked structure computer system according to claim 20, wherein the bus slave chip is a memory.   The three-dimensional stacked structure computer system according to any one of claims 16 to 21, wherein each arbitration circuit has a unique ID.   The semiconductor LSI chip constituting the three-dimensional stacked structure is composed of at least one of a core processor, a memory, a wireless communication, an interface, a sensor, a man-machine interface, and a cryptographic processing chip, and is controlled by a distributed parallel processing program. 23. The three-dimensional laminated structure computer system according to any one of 6 to 22.   The three-dimensional stacked structure computer system according to claim 23, wherein each semiconductor chip has an initialization program for computer system setting as a distributed parallel processing program.   In the initialization program, the host chip creates a system address map based on the descriptor and bus ID, which are chip-specific information, and is defined by the base address and the upper limit address of each bus slave chip according to the system address map. The three-dimensional stacked structure computer system according to claim 24, wherein an address range is set.   26. The three-dimensional stacked structure computer system according to claim 25, wherein each bus slave chip writes its own address range to a bus interface circuit and detects access to the bus slave chip.   27. The three-dimensional stacked structure computer according to claim 6, wherein the system is optimized by recognizing each other chip and performing an initialization operation after stacking the semiconductor chips constituting the three-dimensional stacked structure. system.