CN216288432U

CN216288432U - High-speed interconnection packaging structure based on switching chip

Info

Publication number: CN216288432U
Application number: CN202122833260.5U
Authority: CN
Inventors: 王波; 明雪飞; 高娜燕
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2021-11-18
Filing date: 2021-11-18
Publication date: 2022-04-12
Anticipated expiration: 2031-11-18

Abstract

The utility model relates to the technical field of high-density and high-speed interconnection packaging of integrated circuits, in particular to a high-speed interconnection packaging structure based on a switching chip, which comprises the switching chip, a functional chip, a double-sided wiring layer and salient points/solder balls; the double-sided wiring layer is connected with the switching chip and the salient points A of the functional chip through the bonding pads on the upper surface, the switching chip is connected with the functional chip through the switching lines, and salient points B/welding balls are uniformly distributed on the lower surface of the double-sided wiring layer through the bonding pads. The utility model realizes high-speed interconnection between functional chips by combining the switching chip with the double-sided wiring layer, and reduces the technical requirement of the packaging scheme on the internal circuit of the substrate. The utility model does not need to manufacture the traditional substrate, and can realize low-cost integrated circuit packaging through the double-sided wiring layer with flexible structure and high interconnection density. The method can realize generalization and adjust the structures of the switching chip and the rewiring layer according to the characteristics of the product so as to meet the customization requirement.

Description

High-speed interconnection packaging structure based on switching chip

Technical Field

The utility model relates to the technical field of high-density and high-speed interconnection packaging of integrated circuits, in particular to a high-speed interconnection packaging structure based on a switching chip.

Background

The wafer level packaging technology is a main technical approach for realizing Chip Scale packaging (Chip Scale Package), and is an effective solution for electronic system miniaturization and high integration. Wafer level packaging techniques can enable high precision fabrication of micron-scale circuits to achieve high density interconnect circuits. The Re-Distribution Line (Re-Distribution Line) is a key technology in the field of wafer-level packaging, and micron-level interconnection among functional chips and accurate transmission of high-speed signals can be realized through the Re-Distribution Line.

With the increasing variety of chips contained in the package structure and the increasing number of chips, the miniaturization of the mems puts higher demands on the miniaturization of the package size. Meanwhile, due to the improvement of the power and the transmission rate of the device, the packaging structure puts higher requirements on the interconnection performance and the interconnection density of the chip. Due to the limitation of physical size, the conventional substrate cannot meet the requirements of high-density, small-size and high-speed interconnection lines. The technical scheme can effectively reduce the dependence of the high-speed interconnection line on the number of the base plate and the wiring layer, and realize high-density and high-speed integration of the electronic packaging system while reducing the cost.

SUMMERY OF THE UTILITY MODEL

Aiming at the defects of the prior art, the utility model provides a high-speed interconnection packaging structure based on switching chips, which adopts the switching chips to realize the high-speed interconnection among functional chips so as to reduce the complexity of a substrate level of the packaging structure. The double-sided wiring layer is manufactured by a rewiring technology to replace a traditional substrate, an electric signal on the upper surface of the double-sided wiring layer is led to the lower surface by the through hole/wiring structure, and the external input and output functions of the packaging structure are realized through solder balls or salient points. The whole packaging structure is completed by a wafer level packaging technology, and can be flexibly adjusted to meet the packaging requirement of high-density interconnection.

The utility model is realized by the following technical scheme:

a high-speed interconnection packaging structure based on a switching chip comprises the switching chip, a functional chip, a double-sided wiring layer and salient points/solder balls; the double-sided wiring layer is connected with the switching chip and the salient points A of the functional chip through the bonding pads on the upper surface, the switching chip is connected with the functional chip through the switching lines, and the salient points B/welding balls are uniformly distributed on the lower surface of the double-sided wiring layer through the bonding pads.

Preferably, when the adaptor chip is processed, the processing technology of the adaptor chip includes, but is not limited to, a CMOS technology, and the inside of the adaptor chip further includes a high-speed signal patch circuit connected to the functional chip.

Preferably, the double-sided wiring layer is processed by a process including, but not limited to, a photolithography-electroplating process, and the stacked structure of different levels is fabricated according to requirements.

Preferably, the functional chip is a flip chip.

Preferably, the functional chip includes but is not limited to FPGA, DSP, CPU, DDR, PROM or DRAM.

Preferably, the functional chip comprises a functional chip a and a functional chip B, which are respectively disposed on the left and right sides of the switching chip.

Preferably, the inside of the double-sided wiring layer is a high-density interconnection line for connecting signals of the upper surface and the lower surface, and the external signal input and output functions of the packaging structure are realized through the bump B/solder ball.

Preferably, when the package structure is used, the bump B/solder ball is used for connecting an external board-level package structure.

The utility model has the beneficial effects that:

1. the switching chips are adopted to realize high-speed interconnection among the functional chips, the defect of wiring size of the traditional substrate is overcome, and high-density and high-speed interconnection packaging of the extremely-multi-leading-out-end chips comprising the FPGA, the DSP, the CPU and the like is realized.

2. By adopting the structure to carry out interconnection packaging, the traditional interconnection substrate does not need to be manufactured, the processing period can be shortened, and the cost can be reduced.

3. Compared with the packaging structure based on the substrate, the packaging structure has higher integration level and more flexible integration mode, and can be generalized and customized. The universal packaging structure can be developed based on core function chips (such as FPGA, DSP and CPU), and different functional circuits can be obtained only by replacing other chips around the functional chips without changing a switching chip and a double-sided wiring layer structure. The number, the positions and the like of the switching chips and the double-sided wiring layer structures can be adjusted according to the characteristics of the product so as to meet the customization requirements.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of the present invention.

In the figure: 1-switching chip, 21-functional chip A, 22-functional chip B, 3-double-sided wiring layer, 4-salient point A and 5-salient point B/solder ball.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, the embodiment specifically discloses and provides a technical solution of a high-speed interconnection package structure based on a switching chip, and the package structure includes a switching chip 1, a functional chip, a double-sided wiring layer 3, bumps a4, and bumps B/solder balls 5; the double-sided wiring layer 3 is connected with the switching chip 1, the functional chip A21 and the salient point A of the functional chip B22 through a bonding pad on the upper surface, the switching chip 1 is connected with the functional chip through a switching circuit, and salient points B/solder balls 5 are uniformly distributed on the lower surface of the double-sided wiring layer 3 through the bonding pad.

According to the technical scheme, the double-sided wiring layer 3 containing the connecting circuit is prefabricated on the silicon or glass carrier plate through a wafer-level packaging technology, the bonding pads used for connecting the functional chip A21, the functional chip B22 and the switching chip 1 are manufactured on the upper surface of the double-sided wiring layer 3, and the chips are connected with the double-sided wiring layer 3 through the salient points A4. The information transmission function between the functional chip a21 and the functional chip B22 is realized by the double-sided wiring layer 3 and the switching chip 1. And the lower surface of the double-sided wiring layer 3 is provided with a bonding pad for ball planting or bump growth, and the input and output ends of the packaging structure are flexibly distributed through the ball planting/bump growth. The structure of the double-sided wiring layer 3 can be adjusted according to the requirements of different products, for example, N layers of wiring layers can be manufactured inside the double-sided wiring layer 3 to meet extra signal interconnection, and a through hole structure can be manufactured inside the wiring layers to be used for transmitting signals between the upper surface and the lower surface. The bottom of the packaging structure is provided with solder balls/bumps, and the packaging structure can be welded to a motherboard and can be further integrated with a similar structure in a three-dimensional stacking mode.

Specifically, when the interposer chip 1 is processed, the processing technology thereof includes, but is not limited to, a CMOS process, and the interposer chip 1 further includes a high-speed signal patch circuit for connecting the functional chip a21 and the functional chip B22.

Specifically, when the double-sided wiring layer 3 is processed, the processing technology includes, but is not limited to, a photolithography-electroplating process, and the stacked structure of different levels is manufactured as required.

Specifically, the functional chip a21 and the functional chip B22 are flip chip type chips.

Specifically, the functional chips a21 and B22 include, but are not limited to, FPGA, DSP, CPU, DDR, PROM, or DRAM.

Specifically, the functional chips include a functional chip a21 and a functional chip B22, which are respectively disposed around the adapter chip 1.

Specifically, the inside of the double-sided wiring layer 3 is a high-density interconnection line for connecting signals on the upper surface and the lower surface, and the external signal input and output functions of the packaging structure are realized through the salient points B/solder balls 5.

Specifically, when the package structure is used, the bumps B/the solder balls 5 are used for connecting with an external board-level package structure.

By adopting the design and the use of the structure, the utility model adopts the switching chip 1 to realize the high-speed interconnection between the functional chip A21 and the functional chip B22 so as to reduce the complexity of the substrate level of the packaging structure. The double-sided wiring layer 3 is manufactured by a rewiring technology to replace a traditional substrate, an electric signal on the upper surface of the double-sided wiring layer 3 is led to the lower surface by utilizing a through hole/wiring structure, and the external input and output functions of the packaging structure are realized through the salient points B/solder balls 5. The whole packaging structure is completed by a wafer level packaging technology, and can be flexibly adjusted to meet the packaging requirement of high-density interconnection.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A high-speed interconnection packaging structure based on switching chip, its characterized in that:

the packaging structure comprises a switching chip (1), a functional chip and a double-sided wiring layer (3); the double-sided wiring layer (3) is connected with the switching chip (1) and the salient points A (4) of the functional chips through the bonding pads on the upper surface, the switching chip (1) is connected with the functional chips through switching lines, and salient points B/welding balls (5) are uniformly distributed on the lower surface of the double-sided wiring layer (3) through the bonding pads.

2. A high-speed interconnection packaging structure based on a patch chip according to claim 1, wherein the patch chip (1) is processed by a process including but not limited to CMOS process, and the inside of the patch chip (1) further comprises a high-speed signal patch circuit connected to the functional chip.

3. A high-speed interconnection packaging structure based on a patch chip as claimed in claim 1, wherein the double-sided wiring layer (3) is processed by a process including but not limited to photolithography-electroplating process, and different levels of stacked structures are formed as required.

4. The interposer chip-based high-speed interconnect package as claimed in claim 1, wherein the functional chip is a flip-chip type chip.

5. The high-speed interconnection packaging structure based on the switch chip of claim 4, wherein the functional chip comprises but is not limited to FPGA, DSP, CPU, DDR, PROM or DRAM.

6. A high-speed interconnection packaging structure based on a switch chip as claimed in claim 1, wherein the functional chips include a functional chip A (21) and a functional chip B (22) respectively disposed around the switch chip (1).

7. The high-speed interconnection packaging structure based on the interposer chip as claimed in claim 1, wherein the inside of the double-sided wiring layer (3) is a high-density interconnection circuit for connecting signals of upper and lower surfaces, and the external signal input and output functions of the packaging structure are realized through the bumps B/solder balls (5).

8. A high-speed interconnected package structure based on patch chips as claimed in claim 1, wherein the bumps B/solder balls (5) are used for connecting with an external board-level package structure when the package structure is in use.