WO2024066783A1

WO2024066783A1 - Manufacturing method for high-bandwidth die, and high-bandwidth die

Info

Publication number: WO2024066783A1
Application number: PCT/CN2023/113378
Authority: WO
Inventors: 吴恒; 王峰; 王延; 黄达; 李作; 卓铭; 杨存永
Original assignee: 北京比特大陆科技有限公司
Priority date: 2022-09-26
Filing date: 2023-08-16
Publication date: 2024-04-04
Also published as: CN115458479A

Abstract

Provided in the present disclosure are a manufacturing method for a high-bandwidth die, and a high-bandwidth die. The method comprises: bonding a first metal layer of a first wafer with a first metal layer of a second wafer; thinning a silicon substrate layer of the second wafer until a first FEOL dielectric layer of the second wafer is exposed; building a first BEOL dielectric layer on the first FEOL dielectric layer; building, on the first BEOL dielectric layer, a second metal layer of the second wafer; and bonding the second metal layer of the second wafer with a metal layer of a third wafer.

Description

A method for manufacturing a high-bandwidth bare chip and a high-bandwidth bare chip

The present disclosure claims priority to a Chinese patent application with application number 202211176793.3 filed on September 26, 2022, and invention name “A method for manufacturing a high-bandwidth bare chip and a high-bandwidth bare chip”; the entire contents of which are incorporated into the present disclosure by reference.

Technical Field

The present disclosure relates to, but is not limited to, the field of computer technology, and in particular to a method for manufacturing a high-bandwidth die and a high-bandwidth die.

Background technique

As an integrated circuit, a chip is packaged from a die, which includes a large number of transistors. Different chips have different integration scales, ranging from hundreds of millions to tens or hundreds of transistors. The chip production process is to form an integrated circuit on the surface of a wafer, then cut it into individual dies, and finally package these dies separately to form the final chip.

Currently, bare chips that have not yet been packaged are restricted by 2.5D packaging and through silicon vias (TSV) bonding, have limited bandwidth, have high requirements for chip wiring, and are very difficult to design.

Summary of the invention

The present disclosure provides a method for manufacturing a high-bandwidth bare chip and the high-bandwidth bare chip, so as to improve the bandwidth of the chip.

In a first aspect, the present disclosure provides a method for manufacturing a high-bandwidth bare chip, comprising: bonding a first metal layer of a first wafer to a first metal layer of a second wafer; thinning a silicon base layer of the second wafer until a first front end of line (FEOL) dielectric layer of the second wafer is exposed; building a first back end of line (BEOL) dielectric layer above the first FEOL dielectric layer; building a second metal layer of the second wafer above the first BEOL dielectric layer; and bonding the second metal layer of the second wafer to a metal layer of a third wafer.

In a second aspect, the present disclosure provides a high-bandwidth bare chip, comprising: a first wafer, a second wafer and a third wafer; the second wafer comprises a first metal layer and a second metal layer arranged opposite to each other; the first metal layer of the second wafer is bonded to the first metal layer of the first wafer, and the second metal layer of the second wafer is bonded to the metal layer of the third wafer.

Compared with the prior art, the technical solution provided by the present disclosure has the following beneficial effects:

In the present disclosure, the first metal layer of the first wafer is bonded to the first metal layer of the second wafer, the silicon base layer of the second wafer is thinned until the first FEOL dielectric layer of the second wafer is exposed, the first BEOL dielectric layer is built on the first FEOL dielectric layer, the second metal layer of the second wafer is built on the first BEOL dielectric layer, and the second metal layer of the second wafer is bonded to the metal layer of the third wafer, so that the upper and lower surfaces of the second wafer have metal layers, and the interconnection between the wafers can be realized at the same time, which greatly improves the bandwidth of the chip.

It should be understood that the above general description and the following detailed description are exemplary and explanatory only and are not intended to limit the present disclosure. scope of protection.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the embodiments of the present disclosure.

FIG1 is a schematic diagram of a first implementation flow of a method for manufacturing a high-bandwidth die in an embodiment of the present disclosure;

2a-2e are schematic diagrams of a second implementation process of the method for manufacturing a high-bandwidth die in an embodiment of the present disclosure;

FIG3 is a schematic diagram of a third implementation flow of the method for manufacturing a high-bandwidth die in an embodiment of the present disclosure;

FIG4 is a schematic diagram of a first implementation flow of a method for manufacturing a high-bandwidth chip in an embodiment of the present disclosure;

FIG5 is a schematic diagram of a second implementation flow of a method for manufacturing a high-bandwidth chip in an embodiment of the present disclosure;

FIG6 is a schematic diagram of a structure of a high-bandwidth bare chip in an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a structure of a high-bandwidth chip in an embodiment of the present disclosure.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present disclosure.

The terms used in the disclosed embodiments are only for the purpose of describing specific embodiments and are not intended to limit the disclosed embodiments. The singular forms of "a", "said" and "the" used in the disclosed embodiments are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and/or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

The embodiments of the present disclosure are described below in conjunction with the drawings in the embodiments of the present disclosure. In the following description, reference is made to the drawings that form part of the embodiments of the present disclosure and show specific aspects of the embodiments of the present disclosure or specific aspects of the embodiments of the present disclosure in an illustrative manner. It should be understood that the embodiments of the present disclosure can be used in other aspects and may include structural or logical changes not depicted in the drawings. Therefore, the following detailed description should not be understood in a restrictive sense. For example, it should be understood that the disclosure content in conjunction with the described method can also be applied to the corresponding device or system for performing the method, and vice versa. For example, if one or more specific method steps are described, the corresponding device may include one or more units such as functional units to perform the one or more method steps described (for example, one unit performs one or more steps, or multiple units, each of which performs one or more of the multiple steps), even if such one or more units are not explicitly described or illustrated in the drawings. On the other hand, for example, if a specific device is described based on one or more units such as functional units, the corresponding method may include a step to perform the functionality of one or more units (for example, one step performs the functionality of one or more units, or multiple steps, each of which performs the functionality of one or more units in multiple units), even if such one or more steps are not explicitly described or illustrated in the drawings. It should be understood that unless otherwise expressly stated, The features of the exemplary embodiments and/or aspects described above may be combined with each other.

In the process of bare chip manufacturing, three-dimensional system-on-chip technology and hybrid bonding technology can be used to bond two wafers, and then combined with a silicon interposer (Si interposer) to achieve connection with other functional bare chips (die).

At present, multi-chip packaging technology can achieve the bonding of two wafers, but it can only bond two wafers. If you want to achieve vertical packaging of more layers of chips, you need to use a silicon interposer for 2.5D packaging, or use TSV bonding. The chips made by these two methods have limited bandwidth and have high requirements for the wiring of the upper-layer logic computing chips, making the design very difficult.

In order to solve the above problems, an embodiment of the present disclosure provides a method for manufacturing a high-bandwidth bare chip to improve the bandwidth of the chip.

First, before manufacturing the high-bandwidth die, M wafers for integration in the high-bandwidth die are manufactured, where M is a positive integer greater than or equal to 3, and then the prepared M wafers are used to manufacture the high-bandwidth die.

Next, the method for manufacturing the high-bandwidth die is performed.

In one embodiment, the production of a high-bandwidth die using three wafers is used as an example for explanation. For example, it is assumed that M is equal to 3, that is, three wafers are integrated in the high-bandwidth die, namely the first wafer (which can be recorded as wafer A), the second wafer (which can be recorded as wafer B) and the third wafer (which can be recorded as wafer C). Then, the production method of these three wafers may include: first preparing a silicon base layer (which can also be called a substrate, base, etc.); then preparing a FEOL dielectric layer on top of the silicon base layer, wherein the FEOL dielectric layer includes transistors; after the FEOL dielectric layer is prepared, a BEOL dielectric layer is prepared on top of the FEOL dielectric layer, wherein the BEOL dielectric layer is composed of several layers of conductive metal wires, wherein the conductive metal wires of different layers are connected by columnar metals; after the BEOL dielectric layer is prepared, a metal layer is built on top of the BEOL dielectric layer. At this point, the preparation of wafer A, wafer B and wafer C is completed.

FIG. 1 is a schematic diagram of a first implementation flow of a method for manufacturing a high-bandwidth die in an embodiment of the present disclosure. Referring to FIG. 1 , the method for manufacturing a high-bandwidth die may include:

S101, bonding the first metal layer of wafer A to the first metal layer of wafer B.

It should be noted that the metal layer of the wafer may include but is not limited to copper, aluminum, gold, silver and other metals. The embodiment of the present disclosure takes the metal layer of the wafer as copper as an example to illustrate the method for manufacturing a high-bandwidth bare chip.

S102, thinning the silicon base layer of the second wafer until the first FEOL dielectric layer of the second wafer is exposed.

It can be understood that after bonding the first metal layer of wafer A and the first metal layer of wafer B, the silicon base layer of wafer B is thinned until the transistors in the first FEOL dielectric layer of wafer B are exposed.

In a possible implementation, when preparing wafer B, in order to protect the first FEOL dielectric layer of wafer B, a sacrificial layer may be inserted between the silicon base layer of wafer B and the first FEOL dielectric layer.

For example, after preparing the silicon base layer of wafer B and before building the first FEOL dielectric layer of wafer B, a silicon-based compound is grown on the silicon base layer by epitaxial growth to form a sacrificial layer; or the prepared silicon-based compound dielectric layer is bonded to the silicon base layer to form a sacrificial layer. Of course, the method of inserting the sacrificial layer between the silicon base layer of wafer B and the first FEOL dielectric layer can also be other methods, which are not limited in the embodiments of the present disclosure.

It should be noted that the silicon-based compounds used to make the sacrificial layer may include but are not limited to: silicon-germanium alloy (Si-Ge), silicon oxide (SiOx), silicon carbon nitride (SiCN), silicon nitride (SiN), etc.

The technical solution of inserting a sacrificial layer between the silicon substrate layer of wafer B and the first FEOL dielectric layer in the embodiment of the present disclosure can When the silicon base layer of wafer B is subsequently thinned, the first FEOL dielectric layer of wafer B is not damaged.

In a possible implementation, when a sacrificial layer exists between the silicon base layer of wafer B and the first FEOL dielectric layer, the above S102 may include: thinning the silicon base layer of the second wafer until the sacrificial layer is exposed; and thinning the sacrificial layer until the first FEOL dielectric layer is exposed.

It can be understood that after the first metal layer of wafer A is bonded to the first metal layer of wafer B, the side of wafer B that is not bonded to wafer A (i.e., the silicon base layer of wafer B) is thinned. When thinning wafer B, the silicon base layer is thinned first to expose the sacrificial layer between the silicon base layer and the first FEOL dielectric layer of wafer B, and then the sacrificial layer is thinned until the transistors in the first FEOL dielectric layer of wafer B are exposed.

S103 , constructing a first BEOL dielectric layer on the first FEOL dielectric layer.

It can be understood that after thinning the silicon base layer of wafer B to expose the FEOL dielectric layer of wafer B, a BEOL dielectric layer (i.e., the first BEOL dielectric layer) is built on top of the FEOL dielectric layer of wafer B. This is also the second BEOL dielectric layer in wafer B.

It should be noted that after thinning wafer B, the first BEOL dielectric layer built on the first FEOL dielectric layer of wafer B exposing the transistor has the same structure as the BEOL dielectric layer built between the first metal layer and the first FEOL dielectric layer of wafer B when preparing wafer B.

S104 , building a second metal layer of a second wafer above the first BEOL dielectric layer.

It can be understood that after the first BEOL dielectric layer of wafer B is built, the second metal layer of wafer B is built on the first BEOL dielectric layer.

The technical solution described in the embodiment of the present disclosure of building a first BEOL dielectric layer on the first FEOL dielectric layer of wafer B and then building a second metal layer of wafer B above the first BEOL dielectric layer can enable wafer B to have metal layers on both sides. In other words, both sides of wafer B can be powered. This structure of wafer B can be called a double-sided power supply network structure. Based on the double-sided power supply network structure, wafer B can be bonded to the upper wafer (i.e., wafer C). The double-sided power supply network structure can also serve as a logic chip data interface to achieve signal network interconnection between wafer B and wafer C, thereby greatly improving the bandwidth of the final product (i.e., chip).

S105 , bonding the second metal layer of the second wafer to the metal layer of the third wafer.

It can be understood that after the second metal layer of wafer B is built, the second metal layer of wafer B is bonded to the metal layer of wafer C.

2a-2e are schematic diagrams of a second implementation process of the method for manufacturing a high-bandwidth bare chip in an embodiment of the present disclosure. Referring to FIG2a, wafer A, wafer B, and wafer C are first manufactured, and then the first metal layer 2014 of wafer A and the first metal layer 2025 of wafer B are bonded together (see FIG2b); the silicon base layer 2021 of wafer B is thinned until the sacrificial layer 2022 is exposed, and the sacrificial layer 2022 is further thinned until the crystal in the first FEOL dielectric layer 2023 of wafer B is exposed. After wafer B is thinned, a BEOL dielectric layer is built on top of the first FEOL dielectric layer 2023 of wafer B as the first BEOL dielectric layer 2026 of wafer B, and a metal layer is built on top of the first BEOL dielectric layer 2026 as the second metal layer 2027 of wafer B (see FIG. 2d); after the second metal layer 2027 of wafer B is built, the second metal layer 2027 of wafer B is bonded to the metal layer 2034 of wafer C (see FIG. 2e). At this point, the integration of three wafers is completed. The fabrication of high bandwidth die.

In one embodiment, the production of a high-bandwidth die using four wafers is used as an example for explanation. For example, it is assumed that M is equal to 4, that is, four wafers are integrated in the high-bandwidth die, namely the first wafer (which can be recorded as wafer A’), the second wafer (which can be recorded as wafer B’), the third wafer (which can be recorded as wafer C’) and the fourth wafer (which can be recorded as wafer D). Then, the production method of these four wafers may include: first preparing a silicon base layer (which can also be called a substrate, base, etc.); then preparing a FEOL dielectric layer on the silicon base layer, wherein the FEOL dielectric layer includes transistors; after the FEOL dielectric layer is prepared, a BEOL dielectric layer is prepared on the FEOL dielectric layer, wherein the BEOL dielectric layer is composed of several layers of conductive metal wires, wherein the conductive metal wires of different layers are connected by columnar metals; after the BEOL dielectric layer is prepared, a metal layer is built on the BEOL dielectric layer. At this point, the preparation of wafer A’, wafer B’, wafer C’ and wafer D is completed.

FIG3 is a schematic diagram of a third implementation flow of the method for manufacturing a high-bandwidth die in an embodiment of the present disclosure. Referring to FIG3 , the method for manufacturing a high-bandwidth die may include:

S301, thinning the silicon base layer of the first wafer until the second FEOL dielectric layer of the first wafer is exposed.

It can be understood that the silicon base layer of wafer A’ is thinned until the transistors in the second FEOL dielectric layer of wafer A’ are exposed.

In a possible implementation, there may be a sacrificial layer between the silicon base layer of wafer A’ and the second FEOL dielectric layer. In the case where there is a sacrificial layer between the silicon base layer of wafer A’ and the second FEOL dielectric layer, the above S301 may include: thinning the silicon base layer of the first wafer until the sacrificial layer is exposed; thinning the sacrificial layer until the second FEOL dielectric layer is exposed.

S302 , building a third BEOL dielectric layer on the second FEOL dielectric layer of the first wafer.

It can be understood that after executing S301, the third BEOL dielectric layer of wafer A’ is built on top of the second FEOL dielectric layer of wafer A’, which is also the second BEOL dielectric layer in wafer A’.

S303 , building a second metal layer of the first wafer above the third BEOL dielectric layer.

It can be understood that after the third BEOL dielectric layer of wafer A’ is built, the second metal layer of wafer A’ is built on top of the third BEOL dielectric layer of wafer A’.

S304, bonding the first metal layer of the first wafer to the first metal layer of the second wafer.

It should be noted that the execution process of S304 may refer to the above S101.

S305 , thinning the silicon base layer of the second wafer until the first FEOL dielectric layer of the second wafer is exposed.

It should be noted that the execution process of S305 may refer to the above S102.

S306 , building a first BEOL dielectric layer on the first FEOL dielectric layer of the second wafer.

It should be noted that the execution process of S306 may refer to the above S103.

S307 , building a second metal layer of the second wafer above the first BEOL dielectric layer of the second wafer.

It should be noted that the execution process of S307 may refer to the above S104.

S308 , bonding the second metal layer of the second wafer to the metal layer of the third wafer.

It should be noted that the execution process of S308 may refer to the above S105.

For example, when manufacturing a high-bandwidth bare chip integrating four wafers, the silicon base layer of wafer A' is first thinned until the sacrificial layer is exposed, and then the sacrificial layer is thinned until the transistor in the second FEOL dielectric layer of wafer A' is exposed; the wafer A' is thinned. Afterwards, a BEOL dielectric layer is built on the second FEOL dielectric layer of wafer A' as the third BEOL dielectric layer of wafer A'; a metal layer is built on the third BEOL dielectric layer as the second metal layer of wafer A'; after the second metal layer of wafer A' is built, the second metal layer of wafer A' is bonded to the metal layer of wafer D; after the second metal layer of wafer A' is bonded to the metal layer of wafer D, the first metal layer of wafer A' is bonded to the first metal layer of wafer B'; and the The silicon base layer is thinned until the sacrificial layer is exposed, and then the sacrificial layer is thinned until the transistors in the first FEOL dielectric layer of wafer B' are exposed; after wafer B' is thinned, a BEOL dielectric layer is built on the first FEOL dielectric layer of wafer B' as the first BEOL dielectric layer of wafer B'; a metal layer is built on the first BEOL dielectric layer of wafer B' as the second metal layer of wafer B'; after the second metal layer of wafer B' is built, the second metal layer of wafer B' is bonded to the metal layer of wafer C'. At this point, the production of high-bandwidth bare chips integrating more than three wafers is completed.

It can be understood that wafer B in the high-bandwidth bare chip integrating three wafers and wafer A’ and wafer B’ in the high-bandwidth bare chip integrating four wafers all include two BEOL dielectric layers and two metal layers with the same structure, that is, wafer B, wafer A’ and wafer B’ all have a double-sided power supply network structure.

In one embodiment, when preparing a high-bandwidth bare chip integrating M wafers, M-2 wafers among the high-bandwidth bare chips integrating the M wafers have a double-sided power supply network structure.

Exemplarily, when manufacturing a high-bandwidth bare chip integrating M wafers, M wafers are prepared first, and then the metal layers of the wafers are bonded in sequence, wherein the preparation method and bonding method of the i-th wafer having a double-sided power supply network structure and the i+1-th wafer also having a double-sided power supply network structure are the same as the preparation method and bonding method of wafer A’ and wafer B’ in the high-bandwidth bare chip integrating four wafers in the above embodiment, and the preparation method and bonding method of the first wafer and the M-th wafer are the same as the preparation method and bonding method of wafer D and wafer C’ in the high-bandwidth bare chip integrating four wafers in the above embodiment.

Based on the same inventive concept, the embodiment of the present disclosure further provides a method for manufacturing a high-bandwidth chip, which may include the method for manufacturing the high-bandwidth bare die described in one or more of the above embodiments, and may also include a method for packaging the high-bandwidth bare die. The embodiment of the present disclosure takes the method for manufacturing a high-bandwidth chip integrating three wafers as an example for description.

In a possible implementation, after obtaining a high-bandwidth die integrating three wafers, the high-bandwidth die can be packaged based on the TSV of the third wafer in the high-bandwidth die or the TSV of the first wafer in the high-bandwidth die to obtain a high-bandwidth chip.

It can be understood that after wafer A, wafer B and wafer C are bonded together respectively, the high-bandwidth bare die integrating the three wafers has been completed. At this time, the high-bandwidth bare die can be packaged based on TSV to obtain a high-bandwidth chip integrating the three wafers. Among them, when TSV is buried in wafer C, the high-bandwidth bare die is packaged based on the TSV of wafer C, and when TSV is buried in wafer A, the high-bandwidth bare die is packaged based on the TSV of wafer A.

It should be noted that TSV can be filled with conductive materials such as copper, tungsten, polysilicon, etc. to achieve vertical electrical interconnection of TSV.

In one embodiment, when preparing a high-bandwidth die, TSVs may be embedded in the silicon substrate layer of the third wafer, and then a high-bandwidth chip may be manufactured based on the TSVs of the third wafer, wherein the TSVs extend in a direction away from the FEOL dielectric layer of the third wafer.

The TSV technology described in the embodiments of the present disclosure can reduce signal delay and capacitance/inductance through vertical interconnection, achieve low-power and high-speed communication between chips, increase bandwidth, and realize miniaturization of chip integration.

Exemplarily, FIG. 4 is a schematic diagram of a first implementation flow of a method for manufacturing a high-bandwidth chip in an embodiment of the present disclosure. Referring to FIG. 4 , when TSV is embedded in the third wafer, the method for manufacturing the high-bandwidth chip is as follows:

It should be noted that, assuming that the high-bandwidth chip includes three wafers, before manufacturing the high-bandwidth chip, a high-bandwidth bare die integrating the three wafers is first prepared. Referring to FIG. 2a , wafer A, wafer B, and wafer C are first prepared, wherein a sacrificial layer 2022 is inserted between the silicon base layer 20021 of wafer B and the first FEOL dielectric layer 2023, and TSV is embedded in the silicon base layer 2031 of wafer C.

S401, bonding the first metal layer of wafer A and the first metal layer of wafer B,

S402 , thinning the silicon base layer of wafer B until the first FEOL dielectric layer of wafer B is exposed.

S403 , building a first BEOL dielectric layer on the first FEOL dielectric layer of wafer B.

S404 , building a second metal layer on the first BEOL dielectric layer of wafer B.

S405 , bonding the second metal layer of wafer B and the metal layer of wafer C to obtain a high-bandwidth bare chip.

S406 , based on the TSV in the silicon base layer of the wafer C, the high-bandwidth bare die in S405 is packaged to obtain a high-bandwidth chip.

In another embodiment, when preparing a high-bandwidth die, TSVs may be embedded in the silicon substrate layer of the first wafer, and then the high-bandwidth chip may be manufactured based on the TSVs of the first wafer, wherein the TSVs extend in a direction away from the FEOL dielectric layer of the first wafer.

Exemplarily, FIG5 is a schematic diagram of a second implementation flow of the method for manufacturing a high-bandwidth chip in an embodiment of the present disclosure. Referring to FIG5 , when the TSV is embedded in the first wafer, the method for manufacturing the high-bandwidth chip is as follows:

It should be noted that before preparing the high-bandwidth chip, wafer A, wafer B and wafer C are prepared first, wherein a sacrificial layer is inserted between the silicon base layer of wafer B and the first FEOL medium, and TSV is embedded in the silicon base layer of wafer A.

S501, bonding the first metal layer of wafer A to the first metal layer of wafer B,

S502 , thinning the silicon base layer of wafer B until the first FEOL dielectric layer of wafer B is exposed.

S503 , building a first BEOL dielectric layer on the first FEOL dielectric layer of wafer B.

S504 , building a second metal layer on the first BEOL dielectric layer of wafer B.

S505 , bonding the second metal layer of wafer B and the metal layer of wafer C to obtain a high-bandwidth bare chip.

S506 , based on the TSV in the silicon base layer of wafer A, the high-bandwidth bare die in S505 is packaged to obtain a high-bandwidth chip.

At this point, the production of a high-bandwidth chip integrating three wafers has been completed.

In the disclosed embodiment, the first metal layer of the first wafer is bonded to the first metal layer of the second wafer, the silicon base layer of the second wafer is thinned until the first FEOL dielectric layer of the second wafer is exposed, the first BEOL dielectric layer is built on the first FEOL dielectric layer, and the second metal layer of the second wafer is built on the first BEOL dielectric layer; the second metal layer of the second wafer is bonded to the metal layer of the third wafer, so that the upper and lower surfaces of the second wafer have metal layers, and the interconnection between the wafers can be realized at the same time, which greatly improves the bandwidth of the chip.

In the disclosed embodiment, based on the dual power supply network structure of the second wafer, double-sided wiring and power supply can be achieved on the front and back sides of the second wafer, which can be directly bonded to the upper wafer. The double-sided power supply network can also function as a logic chip interface.

Based on the same inventive concept, the embodiment of the present disclosure provides a high-bandwidth die. FIG. 2e in the method for manufacturing the high-bandwidth die provides a structural schematic diagram of the high-bandwidth die in the embodiment of the present disclosure. Referring to FIG. 2e, the high-bandwidth die includes: wafer A, wafer B, and wafer C; wafer B includes a first metal layer 2025 and a second metal layer 42027 that are arranged opposite to each other; a first metal layer 2026 of wafer B; and a second metal layer 2027 of wafer C. The metal layer 2025 is bonded to the first metal layer 4014 of wafer A, and the second metal layer 2027 of wafer B is bonded to the metal layer 4031 of wafer C.

In one embodiment, wafer B may further include a first BEOL dielectric layer 2026, a first FEOL dielectric layer 2023 and a fourth BEOL dielectric layer 2024 which are arranged in sequence; the first BEOL dielectric layer 2026 grows from the first surface of the first FEOL dielectric layer 2023, and the fourth BEOL dielectric layer 2024 grows from the second surface of the first FEOL dielectric layer 2023, and the first surface is opposite to the second surface; the first metal layer 2025 of wafer B is arranged on the third surface of the fourth BEOL dielectric layer 2024, and the second metal layer 2027 of wafer B is arranged on the fourth surface of the first BEOL dielectric layer 2026, the third surface is the surface of the first BEOL dielectric layer 2026 away from the first FEOL dielectric layer 2023, and the fourth surface is the surface of the first BEOL dielectric layer 2026 away from the first FEOL dielectric layer 2023.

The above structure is a high-bandwidth die integrating three wafers. The high-bandwidth die provided in the embodiment of the present disclosure can also integrate more than three wafers. FIG6 is a structural schematic diagram of the high-bandwidth die in the embodiment of the present disclosure. As shown in FIG6 , the high-bandwidth die can also include: wafer D, the metal layer 6014 of wafer D is bonded to the second metal layer 2016 of wafer A’.

In one embodiment, as shown in FIG6 , the high-bandwidth bare chip integrating four wafers may further include wafer D, and wafer A′ may further include a second BEOL dielectric layer 2013, a second FEOL dielectric layer 2012, and a third BEOL dielectric layer 2015 which are sequentially arranged; the second BEOL dielectric layer 2013 grows from the fifth surface of the second FEOL dielectric layer 2012, and the third BEOL dielectric layer 2015 grows from the sixth surface of the second FEOL dielectric layer 2012, and the fifth surface is opposite to the sixth surface; the first metal layer 2014 of wafer A′ is arranged on the seventh surface of the second BEOL dielectric layer 2013, and the second metal layer 2016 of wafer A′ is arranged on the eighth surface of the third BEOL dielectric layer 2015, the seventh surface is the surface of the second BEOL dielectric layer 2013 away from the second FEOL dielectric layer 2012, and the eighth surface is the surface of the third BEOL dielectric layer 2015 away from the second FEOL dielectric layer 2012.

Based on the same inventive concept, the embodiment of the present disclosure also provides a high-bandwidth chip, which may include the high-bandwidth bare die described in one or more of the above embodiments, and may also include a packaging layer. The embodiment of the present disclosure is described by taking a high-bandwidth chip integrating three wafers as an example. FIG. 7 is a schematic diagram of a structure of a high-bandwidth chip in an embodiment of the present disclosure. As shown in FIG. 7 , the high-bandwidth chip may include: wafer A, wafer B, wafer C, and a packaging layer 701.

In a possible implementation, the high-bandwidth chip may include a high-bandwidth bare die and a packaging layer integrated with three wafers, wherein the packaging layer is grown from the ninth surface of the silicon base layer of the third wafer.

In one embodiment, as shown in Figure 7, a TSV is arranged in the silicon base layer 2031 of wafer C, and the TSV extends in a direction away from the FEOL dielectric layer 2032 of wafer C and toward the ninth surface of the silicon base layer 2031 of wafer C, and the packaging layer 701 is located on the ninth surface of the silicon base layer 2031 of wafer C.

In a possible implementation, the high-bandwidth chip may include a high-bandwidth bare die and a packaging layer integrated with three wafers, wherein the packaging layer grows from the tenth surface of the silicon base layer of the first wafer.

In one embodiment, a TSV is disposed in the silicon base layer of the first wafer, the TSV extends in a direction away from the second FEOL dielectric layer of the first wafer and toward the ninth surface of the silicon base layer of the first wafer, and the packaging layer is located on the tenth surface of the silicon base layer of the first wafer.

Those skilled in the art will appreciate that the order of execution of the steps in the above embodiments does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. After considering the specification and practicing the invention disclosed herein, those skilled in the art will easily think of other embodiments of the disclosed embodiments. The present disclosure is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

The above is only an exemplary embodiment of the present disclosure, but the protection scope of the embodiments of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A method for manufacturing a high-bandwidth bare chip, comprising:

bonding the first metal layer of the first wafer to the first metal layer of the second wafer;

Thinning the silicon base layer of the second wafer until a first front-end FEOL dielectric layer of the second wafer is exposed;

Building a first back-end BEOL dielectric layer above the first FEOL dielectric layer;

Building a second metal layer of the second wafer above the first BEOL dielectric layer;

The second metal layer of the second wafer is bonded to the metal layer of the third wafer.
The method according to claim 1, wherein the method further comprises:

inserting a sacrificial layer between the silicon base layer of the second wafer and the first FEOL dielectric layer;

The thinning of the silicon base layer of the second wafer until the first FEOL dielectric layer is exposed includes:

Thinning the silicon base layer of the second wafer until the sacrificial layer is exposed;

The sacrificial layer is thinned until the first FEOL dielectric layer is exposed.
The method according to claim 1, wherein the method further comprises:

A through silicon via (TSV) is embedded in the silicon base layer of the third wafer, and the TSV extends in a direction away from the FEOL dielectric layer of the third wafer.
The method according to claim 1, wherein the method further comprises:

A through silicon via TSV is embedded in the silicon base layer of the first wafer, and the TSV extends in a direction away from the second FEOL dielectric layer of the first wafer.
The method according to claim 1, wherein before bonding the first metal layer of the first wafer to the first metal layer of the second wafer, the method further comprises:

Thinning the silicon base layer of the first wafer until a second front-end FEOL dielectric layer of the first wafer is exposed;

Building a third BEOL dielectric layer above the second FEOL dielectric layer;

Building a second metal layer of the first wafer above the third BEOL dielectric layer;

The second metal layer of the first wafer is bonded to the metal layer of the fourth wafer.
A high-bandwidth bare chip, comprising: a first wafer, a second wafer and a third wafer; the second wafer comprises a first metal layer and a second metal layer arranged opposite to each other;

The first metal layer of the second wafer is bonded to the first metal layer of the first wafer, and the second metal layer of the second wafer is bonded to the metal layer of the third wafer.
The high-bandwidth die according to claim 6, wherein the second wafer further comprises a first back-end BEOL dielectric layer, a first front-end FEOL dielectric layer, and a fourth BEOL dielectric layer arranged in sequence; the first BEOL dielectric layer grows from a first surface of the first FEOL dielectric layer, the fourth BEOL dielectric layer grows from a second surface of the first FEOL dielectric layer, and the first surface is opposite to the second surface;

The first metal layer of the second wafer is disposed on the third surface of the fourth BEOL dielectric layer, the second metal layer of the second wafer is disposed on the fourth surface of the first BEOL dielectric layer, and the third surface is the first BEOL dielectric layer away from the The fourth surface is a surface of the first FEOL dielectric layer, and the fourth surface is a surface of the first BEOL dielectric layer facing away from the first FEOL dielectric layer.
The high bandwidth die according to claim 6, wherein a through silicon via (TSV) is provided in the silicon base layer of the third wafer, and the TSV extends in a direction away from the FEOL dielectric layer of the third wafer.
The high bandwidth die according to claim 6, wherein a TSV is disposed in the silicon base layer of the first wafer, and the TSV extends in a direction away from the second FEOL dielectric layer of the first wafer.
The high bandwidth die of claim 6, wherein the high bandwidth die further comprises a fourth wafer;

The first wafer further includes a second BEOL dielectric layer, a second FEOL dielectric layer and a third BEOL dielectric layer which are arranged in sequence; the second BEOL dielectric layer grows from the fifth surface of the second FEOL dielectric layer, the third BEOL dielectric layer grows from the sixth surface of the second FEOL dielectric layer, and the fifth surface is opposite to the sixth surface;

The first metal layer of the first wafer is arranged on the seventh surface of the second BEOL dielectric layer, and the second metal layer of the first wafer is arranged on the eighth surface of the third BEOL dielectric layer. The seventh surface is the surface of the second BEOL dielectric layer facing away from the second FEOL dielectric layer, and the eighth surface is the surface of the third BEOL dielectric layer facing away from the second FEOL dielectric layer.