WO2023221540A1 - Chip assembly, manufacturing method therefor, chip and electronic device - Google Patents

Abstract

Provided in the present application are a chip assembly, a manufacturing method therefor, a chip and an electronic device. The chip assembly may include a processing chip and a first chip. The processing chip comprises a power supply connecting line and a grounding connecting line. The first chip comprises: at least one decoupling capacitor; the decoupling capacitor comprises: a first pole and a second pole; the first pole of the decoupling capacitor is directly connected to the power supply connecting line of the processing chip; and the second pole thereof is directly connected to the grounding connecting line of the processing chip. In the embodiments of the present application, the capacitive resources in the first chip can provide decoupling capacitor resources for the processing chip, so that the area of the processing chip can be saved, the processing chip can achieve more data processing functions, and the function of the chip assembly is richer. Moreover, the function of the first chip in the chip assembly is relatively single, so that the decoupling capacitor is arranged in the first chip, and the function of the chip assembly is not influenced.

Description

A chip component, its manufacturing method, chip and electronic equipment

Cross-references to related applications

This application requires the priority of a Chinese patent application submitted to the China Patent Office on May 19, 2022, with the application number 202210553243.2 and the application title "A chip component, its production method, chips and electronic equipment", and its entire content has been approved This reference is incorporated into this application.

Technical field

The present application relates to the field of power electronics technology, and in particular to a chip component, its manufacturing method, chip and electronic equipment.

Background technique

With the continuous development of semiconductor manufacturing technology, chip size shrinkage has gradually encountered a bottleneck. Restricted by factors such as the "storage wall" of the von Neumann architecture, traditional single-chip planar packaging integration can no longer meet people's needs for System on Chip. SoC) function, area, and energy consumption requirements. Three-dimensional integrated circuits (3D Integrated Circuit, 3D IC) have better inter-chip interconnection bandwidth and energy efficiency, and have gradually attracted widespread attention in the industry.

Three-dimensional integrated circuits can be divided into two categories: homogeneous three-dimensional integrated circuits and heterogeneous three-dimensional integrated circuits. Among them, homogeneous three-dimensional integrated circuits integrate multi-layer active devices in the vertical direction. They have the advantages of low cost and high precision, but they also face problems such as imperfect processes and tools. Heterogeneous three-dimensional integrated circuits combine chips with different process architectures, different instruction sets, and different functions into a system that can integrate different semiconductor materials, processes, structures, and devices, and can apply advanced technologies, such as IP (which has independent functions in the chip) Circuit module), chiplet, etc.

In related technologies, heterogeneous integrated circuits can 3D stack processing chips with other chips. The processing chip can be any chip with processing functions. This heterogeneous integrated circuit has a larger memory access bandwidth ( Memory bandwidth), which is more suitable for application scenarios that require large bandwidth such as artificial intelligence and data processing. However, in processing chips, due to power integrity (PI) requirements, decoupling capacitors (decoupling capacitors, decaps) need to be added to the chip power distribution network (Power PDN). These decoupling capacitors consume a large amount of energy. Due to the limited area of the processing chip, the decoupling capacitor occupies a larger area, resulting in the processing chip being unable to implement more data processing functions.

Contents of the invention

Embodiments of the present application provide a chip component, a manufacturing method thereof, a chip, and an electronic device to solve the problem that the decoupling capacitor in the processing chip occupies a large area, resulting in the processing chip being unable to implement more data processing functions.

In a first aspect, an embodiment of the present application provides a chip component. The chip component provided by an embodiment of the present application may include: a processing chip and a first chip. The processing chip may include: power connection lines and ground connection lines. The first chip may include: at least one decoupling capacitor. The decoupling capacitor may include: a first pole and a second pole. The first pole of the decoupling capacitor is directly connected to the power connection line of the processing chip, and the second pole is connected to the power connection line of the processing chip. The ground connection wire is connected directly.

It should be noted that the direct connection in the embodiment of this application refers to the connection between two components through wires, solder balls, through silicon vias and other connectors that only serve as a conductive connection. There is no connection between the two components. Other functional circuits or functions Devices, where a functional circuit or functional device can be understood as: one or more components set up to achieve certain functions. In other words, there are no other components between these two parts except for wire connection.

In the embodiment of the present application, the processing chip has a processing function. For example, the processing chip can be a logic chip (Logic die) or a system on chip (SoC) chip. Of course, the processing chip can also be any other chip with data processing functions. The chip is not limited here. The first chip can be a memory chip (Memory die) or an analog chip. Of course, the first chip can also be other chips that have enough space to install decoupling capacitors. There is no limitation here. In some embodiments of the present application, chips such as the processing chip and the first chip may be bare chips (die) or packaged chips. The chip may be a bare chip (die) or a wafer (wafer), and the wafer may be a cut wafer or an uncut wafer, which is not limited here.

In the chip assembly provided by the embodiment of the present application, a decoupling capacitor is provided in the first chip, and the first pole of the decoupling capacitor is directly connected to the power connection line of the processing chip, and the second pole is directly connected to the ground connection line of the processing chip. connection, so the decoupling capacitor in the first chip can be used as a decoupling capacitor for the power distribution network in the processing chip, and the capacitance resources in the first chip can be used to provide decoupling capacitance resources for the processing chip to improve the power integrity of the processing chip. , thus, the area of the processing chip can be saved, so that the processing chip can implement more data processing functions, thereby making the chip component more functional. Moreover, the function of the first chip in a general chip assembly is relatively single. For example, the memory chip is used to store data. Therefore, setting the decoupling capacitor in the first chip will not affect the function of the first chip, nor will it affect the performance of the first chip. Functionality of chip components.

In this embodiment of the present application, in addition to the decoupling capacitor, the first chip may also include other capacitor structures. For example, when the first chip is a memory chip, the first chip may also be provided with a storage capacitor. In specific implementation, the power connection line and the ground connection line can also be provided in the first chip, and other capacitor structures in the first chip are connected to the power connection line or the ground connection line of the first chip, and the decoupling in the first chip The capacitor is directly connected to the power connection line and the ground connection line of the processing chip. Moreover, generally the power supply connection lines in the first chip and the power supply connection lines in the processing chip have different levels. The first chip is also provided with pins. The power connection line in the first chip is connected to the external power supply through the pins. The decoupling capacitor in the first chip is connected to the power connection line in the processing chip through the pins. Therefore, the first The decoupling capacitors and other capacitive structures in the chip are connected to different pins. During specific implementation, the decoupling capacitor can be distinguished from other capacitor structures based on the connection relationship between the decoupling capacitor and other capacitor structures in the first chip. In the actual evidence collection process, a cross-sectional analysis of the first chip can be performed to determine the pins connected to each capacitor structure in the first chip (i.e., the second connection part in the remainder of this article). The functions of different pins can be determined through the pin descriptions. and connection relationship, so that the decoupling capacitor in the first chip can be distinguished from other capacitor structures.

In this embodiment of the present application, when the first chip is a memory chip, the first chip may also be provided with a storage capacitor. One pole of the storage capacitor may be connected to the power connection line of the first chip, and the other pole may be suspended. The processing chip and the first chip may also include signal connection lines, and the storage capacitor may be connected to the signal connection line of the processing chip through the signal connection line in the first chip, thereby transmitting the data stored in the storage capacitor to the processing chip.

During specific implementation, both the first chip and the processing chip may include: a substrate, and a subsequent metal interconnection layer located on the substrate. In order to facilitate distinction, in the embodiment of the present application, the substrate in the first chip is is called the first substrate, the substrate in the processing chip is called the second substrate, the back-end metal interconnection layer in the first chip is called the first back-end metal interconnection layer, and the back-end metal interconnection layer in the processing chip is called The metal interconnection layer is called the second subsequent metal interconnection layer.

In a possible implementation, the first chip may include: a first substrate, and a first back-end metal interconnection layer located on the first substrate. The side of the first back-end metal interconnection layer facing away from the first substrate may be called the active surface of the first chip, and the side of the first substrate facing away from the first back-end metal interconnection layer may be called the first chip. passive surface. in actual production During the process, the front end of line (FEOL) process can be used to fabricate devices on the surface of the first substrate (for example, the device can be an active device or a passive device), and then the back end process (FEOL) can be used. Back End of Line (BEOL) continues to form each film layer in the first back-end metal interconnection layer on the side of the first substrate with the device.

Similarly, the processing chip may include: a second substrate, and a second back-end metal interconnect layer located on the second substrate. The side of the second back-end metal interconnection layer facing away from the second substrate can be called the active surface of the processing chip, and the side of the second substrate facing away from the second back-end metal interconnection layer can be called the inactive surface of the processing chip. Source surface. In the actual manufacturing process, a front-end process can be used to fabricate a device on the surface of the second substrate (for example, the device can be an active device or a passive device), and then a back-end process can be used to fabricate a device on the second substrate. One side of the device continues to form the layers in the second back metal interconnect layer.

In some embodiments of the present application, the processing chip and the first chip may be stacked. In practical applications, the chip components in the embodiments of the present application can be packaged and processed to form a three-dimensional integrated circuit. In the chip assembly provided by the embodiment of the present application, the processing chip and the first chip can be three-dimensionally stacked and integrated in a face-to-face manner, that is, the active surface of the processing chip is opposite to the active surface of the first chip. , the surface of the second subsequent metal interconnection layer of the processing chip is bonded to the surface of the first subsequent metal interconnection layer of the first chip.

In a possible implementation, the side of the processing chip facing the first chip is provided with a first connection portion (which may also be called a pin in some scenarios), and the side of the first chip facing the processing chip is provided with a second connection portion. The connection part (which may also be called a pin in some scenarios), the processing chip and the first chip are electrically connected through the first connection part and the second connection part.

In a possible implementation, the processing chip and the first chip can be electrically connected through micro bumps. That is to say, the first connection part and the second connection part can be micro bumps. Micro bumps It can be made of copper, gold, silver, tin-silver alloy and other materials, and the shape of the micro-bumps can be spherical or columnar. During the manufacturing process, the micro-bumps on the surface of the processing chip can be aligned with the micro-bumps on the surface of the first chip, and the processing chip and the first chip are three-dimensionally integrated through thermal compression bonding.

In another possible implementation, the processing chip and the first chip can be electrically connected through hybrid bonding. The first connection part and the second connection part may be metal pads, and the metal pads may be made of copper, gold or other metal materials. During the manufacturing process, after metal pads are formed on the surfaces of the processing chip and the first chip, a dielectric layer is formed on the surfaces of the processing chip and the first chip respectively, and the metal pads are recessed into the surface of the dielectric layer. The layer can use materials such as SiO ₂ and SiNx. The surfaces of the processing chip and the first chip are planarized and then the surfaces are activated. Then, after the surfaces of the processing chip and the first chip are aligned, dielectric bonding and metallic bonding are performed respectively, wherein, Dielectric bonding can make the dielectric layer on the surface of the processing chip and the dielectric layer on the surface of the first chip chemically bonded to increase the mechanical firmness between the processing chip and the first chip. Metal bonding can make the metal on the surface of the processing chip The bonding pad is electrically connected to the metal bonding pad on the surface of the first chip, thereby achieving mechanical and electrical bonding between the processing chip and the first chip.

In the embodiment of the present application, the bonding method between the processing chip and the first chip is not limited to face-to-face bonding. In specific implementation, face-to-back bonding can also be used between the processing chip and the first chip. Bonding, back-to-back bonding or various combination bonding methods.

In a possible implementation, the processing chip and the first chip are bonded in a face-to-back manner, the passive surface of the processing chip is opposite to the active surface of the first chip, and the second substrate of the processing chip is The surface of the first chip is bonded to the surface of the first subsequent metal interconnection layer. The processing chip is provided with a first through silicon via, and the second back-end metal interconnection layer in the processing chip can be connected to the first connection part through the first through silicon via, the first connection part and the third connection part. The second connection part can realize mechanical connection and electrical connection between the processing chip and the first chip.

In another possible implementation, the processing chip and the first chip are bonded in a back-to-back manner. The passive surface of the chip is arranged opposite to the active surface of the first chip, and the surface of the second substrate of the processing chip is bonded to the surface of the first substrate of the first chip. A first through-silicon via is provided in the processing chip, and the second back-end metal interconnection layer in the processing chip can be connected to the first connection portion through the first through-silicon via. A second through-silicon via is provided in the first chip, and the first back-end metal interconnection layer in the first chip can be connected to the second connection portion through the second through-silicon via. Through the first through silicon via, the second through silicon via, the first connection part and the second connection part, the mechanical connection and the electrical connection between the processing chip and the first chip can be realized.

In the embodiment of the present application, the chip component may include a processing chip and a first chip. During specific implementation, the chip component may also include other chips. For example, the chip component may include other processing chips, other memory chips or other analog chips. etc., can be set according to factors such as the functions that the chip component needs to implement and the amount of storage required. The number and type of chips in the chip component are not limited here. When the chip assembly includes multiple chips, the relative positions of the multiple chips can be set according to actual needs, which are not limited here.

During specific implementation, if the space in other processing chips is limited, other processing chips can also be connected to decoupling capacitors in other chips. For specific implementation methods, refer to the decoupling between the processing chip and the first chip in the embodiments of the present application. The implementation of capacitor connection will not be repeated here. If there is more space in other memory chips (or analog chips), you can also set decoupling capacitors connected to the processing chip in other memory chips (or analog chips). You can set them according to the actual situation. In other memory chips (or analog chips), The specific implementation method of arranging the decoupling capacitor in the first chip can be referred to the implementation method of arranging the decoupling chip in the first chip in the embodiment of the present application, and the repeated parts will not be described again.

For example, the chip component may further include: a second chip. The second chip is located on a side of the first chip away from the processing chip. The second chip may be a memory chip or an analog chip. The processing chip and the first chip are bonded face to face, and the first chip and the second chip are bonded face to back. The processing chip and the first chip are electrically connected through the first connection part and the second connection part. A third connection part and a fourth connection part are provided between the first chip and the second chip, and the first chip and the second chip can be electrically connected through the third connection part and the fourth connection part. In a possible implementation, the decoupling capacitor may be provided in both the first chip and the second chip, or the decoupling capacitor may be provided only in the first chip, and may be set according to actual needs.

In a possible implementation, the first chip may include: a power through silicon via and a ground through silicon via, that is, the second through silicon via in the first chip may be divided into a power through silicon via and a ground through silicon via. Among them, the power through silicon via is connected to the power connection line in the processing chip, the ground through silicon via is connected to the ground connection line in the processing chip, and the first pole of the decoupling capacitor is connected to the power connection line of the processing chip through the power through silicon via. , the second pole is connected to the ground connection line of the processing chip through the ground through silicon via, so that the decoupling capacitor can be connected to the power connection line and the ground connection line in the processing chip through the internal structure of the first chip to provide the The processing chip provides decoupling capacitors to improve the power integrity of the processing chip. In this embodiment of the present application, other capacitive structures in the first chip except the decoupling capacitor can be connected to the power pins and ground pins of the first chip through other second through silicon vias.

In some embodiments of the present application, the chip assembly may further include: a rewiring layer (Backside Redistribution Layer, RDL), the rewiring layer is located on the side of the first chip facing away from the processing chip; or, the rewiring layer is located on the side of the processing chip facing away from the third processing chip. On one side of a chip, during specific implementation, the rewiring layer can be provided at the bottom or top layer of the chip component, so that the chip component can be connected to other components through the rewiring layer. In a possible implementation, taking the first chip located between the processing chip and the rewiring layer as an example, the processing chip and the first chip both include: power connection lines, ground connection lines and signal connection lines. In the first chip The power connection lines, ground connection lines and signal connection lines are respectively connected to the rewiring layer through through silicon holes, so that the power supply, ground and signal of the first chip itself can be connected to the rewiring layer. The power connection lines, ground connection lines and signal connection lines in the processing chip are connected to the rewiring layer through the through silicon vias in the processing chip and the through silicon vias in the first chip respectively, so that the power supply and signal connection lines of the processing chip can be connected. Ground and signals are connected to the rerouting layer. Moreover, the power transmission paths of the processing chip and the first chip are different, that is, the power connection lines and ground connection lines of the processing chip have no connection relationship with the power connection lines and ground connection lines of the first chip.

In specific implementation, the rewiring layer can also be provided with a fifth connection portion on the side away from the first chip. In a possible implementation, the fifth connection portion can be solder bumps (C4 bumps). The rewiring layer It can be connected to the packaging substrate through solder bumps. In another possible implementation, the fifth connection portion can be a micro-bump, and the rewiring layer can be connected to the interposer through micro-bumps.

The above embodiments introduce how the processing chip and the first chip are stacked. In other embodiments of the present application, the processing chip and the first chip can also be arranged on the same layer, that is, the processing chip and the first chip can also be placed side by side. set up. In specific implementation, the chip assembly may also include: a connecting component. The connecting component may be located on the same side of the processing chip and the first chip. In specific implementation, the connecting component may be located on one side of the active surface of the processing chip and the first chip. Alternatively, the connection component may be located on the passive surface side of the processing chip and the first chip. The first pole and the second pole of the decoupling capacitor are respectively connected to the power connection line and the ground connection line through the connecting component.

In a possible implementation, the connection component may include: a rewiring layer, the processing chip and the first chip are arranged on the same layer, and the rewiring layer is located on the same side of the processing chip and the first chip. The rewiring layer may include: a first connection line and a second connection line. The first pole of the decoupling capacitor may be connected to the power connection line through the first connection line, and the second pole may be electrically connected to the ground connection line through the second connection line. . In a possible implementation, a packaging substrate may be used instead of the rewiring layer, that is, the packaging substrate may be provided on the same side of the processing chip and the first chip, and the first connection line and the second connection line may be provided in the packaging substrate, The first pole of the decoupling capacitor is connected to the power connection line through the first connection line, and the second pole of the decoupling capacitor is connected to the ground connection line through the second connection line.

In another possible implementation, the connection component may include: an interconnection bridge, the processing chip and the first chip are arranged on the same layer, and the interconnection bridge is located on the same side of the processing chip and the first chip. The interconnection bridge may include: a first interconnection line and a second interconnection line. The first pole of the decoupling capacitor may be connected to the power connection line through the first interconnection line, and the second pole may be electrically connected to the ground connection line through the second interconnection line.

In another possible implementation, the connection component may include: a first lead and a second lead, the processing chip and the first chip are arranged on the same layer, and the first lead and the second lead are located on the same side of the processing chip and the first chip. . The first pole of the decoupling capacitor can be electrically connected to the power connection line through the first lead, and the second pole can be electrically connected to the ground connection line through the second lead.

Of course, the decoupling capacitor can also be directly connected to the power connection line and the ground connection line in the processing chip through other methods, and no examples are given here.

In the embodiment of the present application, the decoupling capacitor in the first chip has multiple implementation methods. The specific implementation method of the decoupling capacitor will be described in detail below.

In a possible implementation, the decoupling capacitor may include: a sub-capacitor. The sub-capacitor may be an interdigital capacitor located in the same metal film layer in the first subsequent metal interconnection layer. One of the interdigital capacitors The inserted finger electrode is used as the first pole of the decoupling capacitor, and the other inserted finger electrode is used as the second pole of the decoupling capacitor. In order to ensure that the first pole and the second pole are insulated from each other, between the first pole and the second pole An insulating oxide can also be provided so that the sub-capacitor forms a metal-oxide-metal (MOM) capacitor structure. The MOM capacitor structure has high linearity, does not require additional process steps, and has low manufacturing costs. .

Alternatively, the decoupling capacitor may include: at least two sub-capacitors arranged in parallel. The sub-capacitor may be an interdigital capacitor located in the same metal film layer in the first back-end metal interconnection layer. One end of the total capacitance obtained after each sub-capacitor is connected in parallel serves as the first pole of the decoupling capacitor, and the other end serves as the second pole of the decoupling capacitor. For each sub-capacitor, between the two interdigital electrodes Insulated from each other, an insulating oxide can also be placed between the two interdigitated electrodes, so that the sub-capacitor forms a metal-oxide-metal (MOM) capacitor structure. The linearity of the MOM capacitor structure is high. And no additional process steps are required, and the production cost is low.

In another possible implementation, the first back-end metal interconnection layer may include: a first metal layer and a second metal layer arranged in a stack, the first pole of the decoupling capacitor is located in the first metal layer, and the second The pole is located in the second metal layer, that is, the first pole and the second pole in the decoupling capacitor are located in different metal film layers. In order to insulate the first pole and the second pole from each other, the first pole and the second pole can be insulated from each other. An insulating dielectric layer is set between the two poles so that the decoupling capacitor forms a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure has a higher capacitance density and higher precision. In addition, the first back-end metal interconnection layer may also include other metal film layers. For example, the first back-end metal interconnection layer may also include a third metal layer.

In a possible implementation, the decoupling capacitor may include: a field effect transistor. For example, the field effect transistor may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, abbreviated as MOS), the field effect transistor may include: a first terminal, a second terminal and a control terminal, wherein the first terminal may be a source and the second terminal may be a drain; or the first terminal may be a drain and the second The terminal can be the source, there is no limitation here. The first terminal can be used as the first terminal of the decoupling capacitor, and the control terminal can be used as the second terminal of the decoupling capacitor. In this way, the field effect transistor can be multiplexed by utilizing the capacitance between the control terminal and the first terminal of the field effect transistor. It is a decoupling capacitor. The decoupling capacitor has a high capacitance density, does not require additional process steps, and has a low manufacturing cost.

In some embodiments of the present application, the connection relationship between the storage capacitor in the first chip can be improved so that the storage capacitor in the first chip serves as the above-mentioned decoupling capacitor. Specifically, the storage capacitor in the first chip can be connected to the storage capacitor in the first chip. The power connection line and the ground connection line are connected to the power connection line and the ground connection line in the processing chip. In this way, the first chip's own storage capacitor resource can be used to provide the decoupling capacitor, without adding a new capacitor structure, and the manufacturing cost is low. For example, the decoupling capacitor can be a stacked capacitor or a trench capacitor. Of course, decoupling capacitors can also be improved for other storage capacitors. For example, decoupling capacitors can also be improved for ferroelectric capacitors in ferroelectric memory (Fe RAM). In addition, other redundant capacitors in the first chip can also be set as decoupling capacitors, which will not be explained one by one here.

In a second aspect, embodiments of the present application further provide an electronic device. The electronic device in the embodiment of the present application may include: any of the above chip components and a shell, and the shell covers the chip component. In the above chip assembly, the capacitance resources in the first chip can be used to provide decoupling capacitance resources for the processing chip to improve the power integrity of the processing chip, thereby saving the area of the processing chip and enabling the processing chip to achieve more Data processing functions, thereby making the chip components more functional. Therefore, the functions of electronic devices including any of the above chip components are also richer, making the user experience of the electronic devices better.

Since the problem-solving principle of this electronic device is similar to that of the foregoing chip component, the implementation of this electronic device can refer to the implementation of the foregoing chip component, and repeated details will not be repeated.

In a third aspect, embodiments of the present application also provide a chip (ie, the first chip in the above embodiment). The chip may include: at least one decoupling capacitor. The decoupling capacitor includes: a first pole and a second pole, The first pole of the decoupling capacitor is used to be directly connected to the power connection line of the processing chip, and the second pole is used to be directly connected to the ground connection line of the processing chip.

In a possible implementation, the above-mentioned chip may include: a substrate, and a back-end metal interconnection layer located on the substrate. The decoupling capacitor may include: one sub-capacitor; alternatively, the decoupling capacitor may include: at least two sub-capacitors arranged in parallel, and the sub-capacitors are interdigital capacitors located in the same metal film layer in the subsequent metal interconnection layer.

In another possible implementation, the above-mentioned chip may include: a substrate, and a subsequent metal layer located on the substrate. Belongs to the interconnection layer. The subsequent metal interconnection layer may include: a first metal layer and a second metal layer that are stacked, the first pole of the decoupling capacitor is located in the first metal layer, and the second pole is located in the second metal layer.

In another possible implementation, the decoupling capacitor may include: a field effect transistor. The field effect transistor includes: a first terminal, a second terminal and a control terminal. The first terminal serves as the first pole of the decoupling capacitor, and the control terminal As the second pole of the decoupling capacitor.

In another possible implementation, the decoupling capacitor may be a stack capacitor or a trench capacitor.

In the embodiment of the present application, the above-mentioned chip can be a memory chip (Memory die) or an analog chip. Of course, the above-mentioned chip can also be other chips with sufficient space to install decoupling capacitors, which is not limited here.

For the specific implementation of the chip in the embodiment of the present application, reference can be made to the specific implementation of the first chip in the above embodiment, and repeated details will not be described again.

In a fourth aspect, embodiments of the present application further provide a method of manufacturing a chip component. The method of manufacturing a chip component provided by the embodiment of the present application may include:

A processing chip is provided. The processing chip includes: a power connection line and a ground connection line;

A first chip is provided. The first chip includes: at least one decoupling capacitor; the decoupling capacitor includes: a first pole and a second pole;

The first pole of the decoupling capacitor is directly connected to the power connection line of the processing chip, and the second pole is directly connected to the ground connection line of the processing chip.

For the specific implementation of the chip component manufacturing method in the embodiment of the present application, reference can be made to the specific implementation of the chip component in the above embodiment, and repeated details will not be described again.

Description of the drawings

Figure 1 is a schematic structural diagram of a chip component provided by an embodiment of the present application;

Figure 2 is another structural schematic diagram of a chip component provided by an embodiment of the present application;

Figure 3 is another schematic structural diagram of a chip component provided by an embodiment of the present application;

Figure 4 is another schematic structural diagram of a chip component provided by an embodiment of the present application;

Figure 5 is another structural schematic diagram of a chip component provided by an embodiment of the present application;

Figure 6 is another structural schematic diagram of a chip component provided by an embodiment of the present application;

Figure 7 is another structural schematic diagram of a chip component provided by an embodiment of the present application;

Figure 8 is a schematic structural diagram of a decoupling capacitor in an embodiment of the present application;

Figure 9 is another structural schematic diagram of a decoupling capacitor in an embodiment of the present application;

Figure 10 is another structural schematic diagram of a decoupling capacitor in an embodiment of the present application;

Figure 11 is a schematic structural diagram of the field effect transistor of the present application;

FIG. 12 is a schematic flowchart of a method for manufacturing a chip component provided by an embodiment of the present application.

Reference signs:

11-processing chip; 111-second substrate; 112-second back-end metal interconnection layer; 113-first through silicon via; 12-first chip; 121-first substrate; 122-first back-end road Metal interconnection layer; 122a-first metal layer; 122b-second metal layer; 122c-insulating dielectric layer; 122d-third metal layer; 123a-power through silicon via; 123b-ground through silicon via; 123c-signal silicon Through hole; 12′-second chip; 121′-third substrate; 122′-third back-end metal interconnection layer; 13-rewiring layer; 14-first connection part; 15-second connection part; 16-The third connection part; 17-The fourth connection part; 18-The fifth connection part; C-decoupling capacitor; c1-first pole; c2-second pole; C′-subcapacitor; NMOS-N-type field Effect transistor; PMOS-P type field effect transistor; G-control terminal; S-first terminal; D-second terminal; W-interconnection bridge; L1-first lead; L2-second lead.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail below in conjunction with the accompanying drawings.

It should be noted that the same reference numerals in the drawings of the present application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing position and direction described in this application are all explained by taking the accompanying drawings as examples, but they can be changed as needed, and all changes are included in the protection scope of this application. The drawings in this application are only used to illustrate relative positional relationships and do not represent true proportions.

In order to solve the problem that the decoupling capacitor in the processing chip occupies a large area, causing the processing chip to be unable to implement more data processing functions, embodiments of the present application provide a chip component, a manufacturing method thereof, a chip, and an electronic device. The chip components in the embodiments of the present application can be applied to various types of electronic devices. For example, the electronic devices can be smart phones, computers, smart TVs, etc.

FIG. 1 is a schematic structural diagram of a chip component provided by an embodiment of the present application. As shown in FIG. 1 , the chip component provided by an embodiment of the present application may include: a processing chip 11 and a first chip 12 . The processing chip 11 may include: power connection lines (not shown in the figure) and ground connection lines (not shown in the figure). The first chip 12 may include: at least one decoupling capacitor C. The decoupling capacitor C may include: a first pole c1 and a second pole c2. The first pole c1 of the decoupling capacitor C is directly connected to the power connection line of the processing chip 11 , the second pole c2 is directly connected to the ground connection line of the processing chip 11 .

It should be noted that the direct connection in the embodiment of this application refers to the connection between two components through wires, solder balls, through silicon vias and other connectors that only serve as a conductive connection. There is no connection between the two components. Other functional circuits or functional devices, wherein functional circuits or functional devices can be understood as: one or more components provided to achieve certain functions. In other words, there are no other components between these two parts except for wire connection.

In the embodiment of the present application, the processing chip 11 has a processing function. For example, the processing chip 11 can be a logic chip (Logic die) or a system on chip (SoC) chip. Of course, the processing chip 11 can also be any other chip with Chips with data processing functions are not limited here. The first chip 12 can be a memory die or an analog chip. Of course, the first chip 12 can also be other chips with enough space to install decoupling capacitors, which is not limited here. In some embodiments of the present application, the processing chip 11, the first chip 12 and other chips may be bare chips (die) or packaged chips. The chip may be a bare chip (die) or a wafer (wafer), and the wafer may be a cut wafer or an uncut wafer, which is not limited here.

In the chip assembly provided by the embodiment of the present application, a decoupling capacitor is provided in the first chip, and the first pole of the decoupling capacitor is directly connected to the power connection line of the processing chip, and the second pole is connected to the ground connection line in the processing chip. Direct connection, so the decoupling capacitor in the first chip can be used as a decoupling capacitor for the power distribution network in the processing chip. The capacitance resources in the first chip can be used to provide decoupling capacitance resources for the processing chip to improve the power integrity of the processing chip. Therefore, the area of the processing chip can be saved, so that the processing chip can implement more data processing functions, thereby making the chip components more functional. Moreover, the function of the first chip in a general chip assembly is relatively single. For example, the memory chip is used to store data. Therefore, setting the decoupling capacitor in the first chip will not affect the function of the first chip, nor will it affect the performance of the first chip. Functionality of chip components.

In this embodiment of the present application, in addition to the decoupling capacitor, the first chip may also include other capacitor structures. For example, when the first chip is a memory chip, the first chip may also be provided with a storage capacitor. In specific implementation, the power connection line and the ground connection line can also be provided in the first chip, and other capacitor structures in the first chip are connected to the power connection line or the ground connection line of the first chip, and the decoupling in the first chip The capacitor is directly connected to the power connection line and the ground connection line of the processing chip. Moreover, generally the levels of the power connection lines in the first chip and the power connection lines in the processing chip are different. The first chip is also provided with pins. The power connection line in the first chip is connected to the external power supply through the pins. The decoupling capacitor in the first chip is connected to the power connection line in the processing chip through the pins. Therefore, the first The decoupling capacitors and other capacitive structures in the chip are connected to different pins. During specific implementation, the decoupling capacitor can be distinguished from other capacitor structures based on the connection relationship between the decoupling capacitor and other capacitor structures in the first chip. In the actual evidence collection process, a cross-sectional analysis of the first chip can be performed to determine the pins connected to each capacitor structure in the first chip (i.e., the second connection part in the remainder of this article). The functions of different pins can be determined through the pin descriptions. and connection relationship, so that the decoupling capacitor in the first chip can be distinguished from other capacitor structures.

In this embodiment of the present application, when the first chip is a memory chip, the first chip may also be provided with a storage capacitor. One pole of the storage capacitor may be connected to the power connection line of the first chip, and the other pole may be suspended. The processing chip and the first chip may also include signal connection lines, and the storage capacitor may be connected to the signal connection line of the processing chip through the signal connection line in the first chip, thereby transmitting the data stored in the storage capacitor to the processing chip.

During specific implementation, both the first chip and the processing chip may include: a substrate, and a subsequent metal interconnection layer located on the substrate. In order to facilitate distinction, in the embodiment of the present application, the substrate in the first chip is is called the first substrate, the substrate in the processing chip is called the second substrate, the back-end metal interconnection layer in the first chip is called the first back-end metal interconnection layer, and the back-end metal interconnection layer in the processing chip is called The metal interconnection layer is called the second subsequent metal interconnection layer.

Continuing to refer to FIG. 1 , the first chip 12 may include: a first substrate 121 , and a first backend metal interconnect layer 122 located on the first substrate 121 . The side of the first back-end metal interconnection layer 122 facing away from the first substrate 121 can be called the active surface of the first chip 12 , and the side of the first substrate 121 facing away from the first back-end metal interconnection layer 122 It is called the passive surface of the first chip 12 . In the actual manufacturing process, the front end of line (FEOL) process can be used to manufacture devices on the surface of the first substrate 121 (for example, the device can be an active device or a passive device), and then, using The back end of line (BEOL) process continues to form each film layer in the first back end of line metal interconnection layer 122 on the side of the first substrate 121 with the device.

Similarly, the processing chip 11 may include: a second substrate 111, and a second backend metal interconnect layer 112 located on the second substrate 111. The side of the second back-end metal interconnection layer 112 facing away from the second substrate 111 can be called the active surface of the processing chip 11 , and the side of the second substrate 111 facing away from the second back-end metal interconnection layer 112 can be called the active surface of the processing chip 11 . It is the passive surface of the processing chip 11 . In the actual manufacturing process, a front-end process can be used to fabricate a device on the surface of the second substrate 111 (for example, the device can be an active device or a passive device), and then a back-end process can be used to fabricate a device on the surface of the second substrate 111 . The side of 111 with the device continues to form the layers in the second back-end metal interconnect layer 112 .

In some embodiments of the present application, the processing chip and the first chip may be stacked. In practical applications, the chip components in the embodiments of the present application can be packaged and processed to form a three-dimensional integrated circuit. In the chip assembly shown in FIG. 1 , the processing chip 11 and the first chip 12 can be three-dimensionally stacked and integrated in a face-to-face manner, that is, the active surface of the processing chip 11 and the active surface of the first chip 12 Arranged oppositely, the surface of the second back-end metal interconnection layer 112 of the processing chip 11 is bonded to the surface of the first back-end metal interconnection layer 122 of the first chip 12 .

As shown in FIG. 1 , the processing chip 11 is provided with a first connection portion 14 (which may also be called a pin in some scenarios) on the side facing the first chip 12 , and the first chip 12 is provided on a side facing the processing chip 11 . The processing chip 11 and the first chip 12 are electrically connected through the second connection part 15 (which may also be called a pin in some scenarios) through the first connection part 14 and the second connection part 15 .

In a possible implementation, the processing chip 11 and the first chip 12 can be electrically connected through micro bumps. That is to say, the first connection portion 14 and the second connection portion 15 can be micro bumps. , micro-bumps can be made of copper, gold, silver, tin-silver alloy and other materials, and the shape of the micro-bumps can be spherical or columnar. in production During the process, the micro bumps on the surface of the processing chip 11 can be aligned with the micro bumps on the surface of the first chip 12, and the processing chip 11 and the first chip 12 can be three-dimensionally integrated through thermal compression bonding. .

In another possible implementation, the processing chip 11 and the first chip 12 can be electrically connected through hybrid bonding. The first connection part 14 and the second connection part 15 may be metal pads, and the metal pads may be made of copper, gold or other metal materials. During the manufacturing process, after metal pads are formed on the surfaces of the processing chip 11 and the first chip 12 , a dielectric layer is formed on the surfaces of the processing chip 11 and the first chip 12 respectively, and the metal pads are recessed into the dielectric layer. On the surface, the dielectric layer can use materials such as SiO ₂ and SiNx. The surfaces of the processing chip 11 and the first chip 12 are planarized and the surfaces are activated. Then, after the surfaces of the processing chip 11 and the first chip 12 are aligned, dielectric bonding and metallic bonding are performed respectively. ), wherein dielectric bonding can realize chemical bonding between the dielectric layer on the surface of the processing chip 11 and the dielectric layer on the surface of the first chip 12, thereby increasing the mechanical firmness between the processing chip 11 and the first chip 12. Metal bonding The bonding can electrically connect the metal pads on the surface of the processing chip 11 and the metal pads on the surface of the first chip 12, thereby achieving mechanical and electrical bonding between the processing chip 11 and the first chip 12.

In the embodiment of the present application, the bonding method between the processing chip and the first chip is not limited to face-to-face bonding. In specific implementation, face-to-back bonding can also be used between the processing chip and the first chip. Bonding, back-to-back bonding or various combination bonding methods. Figure 2 is another structural schematic diagram of a chip assembly provided by an embodiment of the present application. In the chip assembly shown in Figure 2, the processing chip 11 and the first chip 12 are bonded in a face-to-back manner. The passive surface is arranged opposite to the active surface of the first chip 12 , and the surface of the second substrate 111 of the processing chip 11 is bonded to the surface of the first back-end metal interconnection layer 122 of the first chip 12 . The processing chip 11 is provided with a first through silicon via 113 . The second back-end metal interconnect layer 112 in the processing chip 11 can be connected to the first connection portion 14 through the first through silicon via 113 . , the first connection part 14 and the second connection part 15 can realize the mechanical connection and electrical connection between the processing chip 11 and the first chip 12 .

Figure 3 is another schematic structural diagram of a chip assembly provided by an embodiment of the present application. In the chip assembly shown in Figure 3, the processing chip 11 and the first chip 12 are bonded in a back-to-back manner. The passive components of the processing chip 11 The surface of the second substrate 111 of the processing chip 11 is bonded to the surface of the first substrate 121 of the first chip 12 . The processing chip 11 is provided with a first through silicon via 113 , and the second back-end metal interconnect layer 112 in the processing chip 11 can be connected to the first connection portion 14 through the first through silicon via 113 . The first chip 12 is provided with second through silicon vias (such as 123a, 123b and 123c in the figure), and the first back-end metal interconnect layer 122 in the first chip 12 can be connected to the second through silicon via. Part 15 is connected. Through the first through silicon via 113 , the second through silicon via, the first connection part 14 and the second connection part 15 , the mechanical connection and the electrical connection between the processing chip 11 and the first chip 12 can be realized.

The chip assembly shown in Figures 1 to 3 includes a processing chip 11 and a first chip 12. During specific implementation, the chip assembly may also include other chips. For example, the chip assembly may include other processing chips, other memory chips or other Analog chips, etc., can be set according to factors such as the functions that the chip component needs to implement and the amount of storage required. The number and type of chips in the chip component are not limited here. When the chip assembly includes multiple chips, the relative positions of the multiple chips can be set according to actual needs, which are not limited here.

During specific implementation, if the space in other processing chips is limited, other processing chips can also be connected to decoupling capacitors in other chips. For specific implementation methods, refer to the decoupling between the processing chip and the first chip in the embodiments of the present application. The implementation of capacitor connection will not be repeated here. If there is more space in other memory chips (or analog chips), you can also set decoupling capacitors connected to the processing chip in other memory chips (or analog chips). You can set them according to the actual situation. In other memory chips (or analog chips), For specific implementation methods of setting decoupling capacitors in analog chips, please refer to According to the implementation method of arranging the decoupling chip in the first chip in the embodiment of the present application, the repeated details will not be repeated.

FIG. 4 is another schematic structural diagram of a chip assembly provided by an embodiment of the present application. As shown in FIG. 4 , for example, the chip assembly may further include: a second chip 12 ′. The second chip 12 ′ is located away from the first chip 12 . On one side of the processing chip 11, the second chip 12' may be a memory chip or an analog chip, or the like. The second chip 12' may include: a third substrate 121' and a third backend metal interconnect layer 122' located on the third substrate 121'. In FIG. 4 , the processing chip 11 and the first chip 12 are bonded face to face, and the first chip 12 and the second chip 12 ′ are bonded face to back. The processing chip 11 and the first chip 12 are electrically connected through the first connection part 14 and the second connection part 15 . A third connection part 16 and a fourth connection part 17 are provided between the first chip 12 and the second chip 12 ′. The first chip 12 and the second chip 12 ′ can pass through the third connection part 16 and the fourth connection part 17 Make electrical connections. In a possible implementation, the decoupling capacitor C can be provided in both the first chip 12 and the second chip 12'. In specific implementation, the decoupling capacitor C can also be provided only in the first chip 12. It can be set according to actual needs.

In a possible implementation, as shown in FIG. 1 , the first chip 12 may include: a power TSV 123 a and a ground TSV 123 b. That is, the second TSV in the first chip 12 may be divided into power TSVs 123 a and ground TSVs 123 b. TSV 123a and ground TSV 123b. Among them, the power through silicon via 123a is connected to the power connection line in the processing chip 11, the ground through silicon via 123b is connected to the ground connection line in the processing chip 11, and the first pole c1 of the decoupling capacitor C is connected to the power through silicon via 123a. The power connection line of the processing chip 11 is connected, and the second pole c2 is connected to the ground connection line of the processing chip 11 through the ground through silicon via 123b. Therefore, the decoupling capacitor C and the processing chip 11 can be realized through the internal structure of the first chip 12 The power connection line and the ground connection line are connected to provide a decoupling capacitor C to the processing chip 11 to improve the power integrity of the processing chip 11 . In this embodiment of the present application, other capacitive structures in the first chip 12 except the decoupling capacitor C can be connected to the power pins and ground pins of the first chip 12 through other second through silicon vias.

As shown in Figure 1, in some embodiments of the present application, the chip assembly may also include: a rewiring layer 13 (Backside Redistribution Layer, RDL), the rewiring layer 13 is located on the side of the first chip 12 away from the processing chip 11; Alternatively, the rewiring layer 13 is located on the side of the processing chip 11 away from the first chip 12. In specific implementation, the rewiring layer 13 can be provided at the bottom or top layer of the chip component, so that the chip component can be connected to the chip through the rewiring layer 13. Other components realize the connection. In a possible implementation, taking the structure shown in Figure 1 as an example, the first chip 12 is located between the processing chip 11 and the rewiring layer 13. Both the processing chip 11 and the first chip 12 include: power connection lines, The ground connection lines and signal connection lines, the power connection lines, the ground connection lines and the signal connection lines in the first chip 12 are respectively connected to the rewiring layer 13 through the through silicon vias, so that the power supply and ground of the first chip 12 itself can be connected. , the signal is connected to the rewiring layer 13. The power connection lines, ground connection lines and signal connection lines in the processing chip 11 are connected to the rewiring layer 13 through the through silicon vias in the processing chip 11 and the through silicon vias in the first chip 12 respectively, so that the processing can be The power, ground, and signals of the chip 11 are connected to the rewiring layer 13 . Moreover, the power transmission paths of the processing chip 11 and the first chip 12 are different, that is, the power connection lines and ground connection lines of the processing chip 11 have no connection relationship with the power connection lines and ground connection lines of the first chip 12 .

In specific implementation, the rewiring layer 13 can also be provided with a fifth connection portion 18 on the side away from the first chip 12. In a possible implementation, the fifth connection portion 18 can be solder bumps (C4 bumps). , the rewiring layer 13 can be connected to the package substrate through solder bumps. In another possible implementation, the fifth connection portion 18 can be a micro-bump, and the rewiring layer 13 can be connected to the interposer through micro-bumps ( interposer) on.

Figures 1 to 4 take the stacked arrangement of the processing chip and the first chip as an example. In other embodiments of the present application, the processing chip and the first chip can also be arranged on the same layer, that is, the processing chip and the first chip can also be arranged on the same layer. Can be set up side by side. In specific implementation, the chip assembly may also include: a connecting component, which may be located between the processing chip and the first chip. On the same side, during specific implementation, the connecting component may be located on the active surface side of the processing chip and the first chip, or the connecting component may also be located on the passive surface side of the processing chip and the first chip. The first pole and the second pole of the decoupling capacitor are respectively connected to the power connection line and the ground connection line through the connecting component.

Figure 5 is another schematic structural diagram of a chip assembly provided by an embodiment of the present application. As shown in Figure 5, the connection component may include: a rewiring layer 13. The processing chip 11 and the first chip 12 are arranged on the same layer. The rewiring layer 13 is located on The same side of the processing chip 11 and the first chip 12 is processed. The rewiring layer 13 may include: a first connection line and a second connection line (not shown in the figure), the first pole c1 of the decoupling capacitor C may be connected to the power connection line through the first connection line, and the second pole c2 may be It is electrically connected to the ground connection line through the second connection line. In a possible implementation, a packaging substrate can be used instead of the rewiring layer, that is, a packaging substrate can also be provided on the same side of the processing chip 11 and the first chip 12, and the first connection line and the second connection can be provided in the packaging substrate. The first connection line connects the first pole c1 of the decoupling capacitor C and the power connection line, and the second connection line connects the second pole c2 of the decoupling capacitor C and the ground connection line.

Figure 6 is another structural schematic diagram of a chip assembly provided by an embodiment of the present application. As shown in Figure 6, the connection component may include: an interconnection bridge W. The processing chip 11 and the first chip 12 are arranged on the same layer. The interconnection bridge W is located on the processing chip. 11 and the same side of the first chip 12. The interconnection bridge W may include: a first interconnection line and a second interconnection line (not shown in the figure). The first pole c1 of the decoupling capacitor C may be connected to the power connection line through the first interconnection line, and the second pole c2 may be connected through the first interconnection line. The second interconnection line is electrically connected to the ground connection line.

Figure 7 is another structural schematic diagram of a chip assembly provided by an embodiment of the present application. As shown in Figure 7, the connection component may include: a first lead L1 and a second lead L2. The processing chip 11 and the first chip 12 are arranged on the same layer. The first lead L1 and the second lead L2 are located on the same side of the processing chip 11 and the first chip 12 . The first pole c1 of the decoupling capacitor C can be connected to the power connection line through the first lead L1, and the second pole c2 can be electrically connected to the ground connection line through the second lead L2.

Of course, the decoupling capacitor C can also be directly connected to the power connection line and the ground connection line in the processing chip 11 in other ways, and no examples are given here.

In the embodiment of the present application, the decoupling capacitor in the first chip has multiple implementation methods, which will be described in detail below with reference to the accompanying drawings.

Figure 8 is a schematic structural diagram of a decoupling capacitor in an embodiment of the present application. Figure 9 is another schematic structural diagram of a decoupling capacitor in an embodiment of the present application. As shown in Figure 8, the decoupling capacitor C may include: a sub-capacitor C' , the sub-capacitor C′ can be an interdigital capacitor located in the same metal film layer in the first back-end metal interconnection layer. One of the interdigital electrodes in the interdigital capacitor serves as the first pole c1 of the decoupling capacitor C, and the other The inserted finger electrode serves as the second pole c2 of the decoupling capacitor C. In order to ensure that the first pole c1 and the second pole c2 are insulated from each other, an insulating oxide can also be provided between the first pole c1 and the second pole c2, so that The sub-capacitor C′ forms a metal-oxide-metal (MOM) capacitor structure. The MOM capacitor structure has high linearity, does not require additional process steps, and has low manufacturing cost.

Alternatively, as shown in FIG. 9 , the decoupling capacitor C may include: at least two sub-capacitors C′ arranged in parallel. The sub-capacitor C′ may be an interdigital capacitor located in the same metal film layer in the first subsequent metal interconnection layer. One end of the total capacitance obtained by connecting each sub-capacitor C′ in parallel serves as the first pole of the decoupling capacitor C, and the other end serves as the second pole of the decoupling capacitor C. In order to insulate the two interdigitated electrodes of each sub-capacitor C' from each other, an insulating oxide can also be provided between the two interdigitated electrodes, so that the sub-capacitor C' forms a metal-oxide-metal (Metal-Oxide) -Metal, MOM) capacitor structure. The MOM capacitor structure has high linearity, does not require additional process steps, and has low production costs.

Figure 10 is another schematic structural diagram of a decoupling capacitor in an embodiment of the present application. As shown in Figure 10, the first back-end metal interconnection layer may include: a first metal layer 122a and a second metal layer 122b arranged in a stack. The first pole c1 of the decoupling capacitor C is located in the first metal layer 122a, and the second pole c2 is located in the second metal layer 122b, that is, the first pole of the decoupling capacitor C c1 and the second electrode c2 are respectively located on different metal film layers. In order to insulate the first electrode c1 and the second electrode c2 from each other, an insulating dielectric layer 122c can be provided between the first electrode c1 and the second electrode c2, so that The decoupling capacitor C forms a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure has a high capacitance density and high precision. In addition, the first subsequent metal interconnection layer may also include other metal film layers. For example, the first subsequent metal interconnection layer may further include a third metal layer 122d.

In a possible implementation, the decoupling capacitor may include: a field effect transistor. For example, the field effect transistor may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, abbreviated as MOS), Figure 11 is a schematic structural diagram of the field effect transistor of the present application, (1) in Figure 11 is a schematic structural diagram of the N-type field effect transistor NMOS, and (2) in Figure 11 is a structural schematic diagram of the P-type field effect transistor PMOS Schematic diagram, as shown in (1) and (2) in Figure 11, the field effect transistor may include: a first terminal S, a second terminal D, and a control terminal G, where the first terminal S may be the source, and the second terminal D It can be a drain; alternatively, the first terminal S can be a drain, and the second terminal D can be a source, which is not limited here. The first terminal S can be used as the first terminal c1 of the decoupling capacitor, and the control terminal G can be used as the second terminal c2 of the decoupling capacitor. In this way, the capacitance between the control terminal G and the first terminal S of the field effect transistor can be used. The field effect transistor is reused as a decoupling capacitor. The decoupling capacitor has a high capacitance density, does not require additional process steps, and has a low manufacturing cost.

In some embodiments of the present application, the connection relationship between the storage capacitor in the first chip can be improved so that the storage capacitor in the first chip serves as the above-mentioned decoupling capacitor. Specifically, the storage capacitor in the first chip can be connected to the storage capacitor in the first chip. The power connection line and the ground connection line are connected to the power connection line and the ground connection line in the processing chip. In this way, the first chip's own storage capacitor resource can be used to provide the decoupling capacitor, without adding a new capacitor structure, and the manufacturing cost is low. For example, the decoupling capacitor can be a stacked capacitor or a trench capacitor. Of course, decoupling capacitors can also be improved for other storage capacitors. For example, decoupling capacitors can also be improved for ferroelectric capacitors in ferroelectric memory (Fe RAM). In addition, other redundant capacitors in the first chip can also be set as decoupling capacitors, which will not be explained one by one here.

Based on the same technical concept, embodiments of the present application also provide an electronic device. The electronic device in the embodiment of the present application may include: any of the above chip components and a shell, and the shell covers the chip component. In the above chip assembly, the capacitance resources in the first chip can be used to provide decoupling capacitance resources for the processing chip to improve the power integrity of the processing chip, thereby saving the area of the processing chip and enabling the processing chip to achieve more Data processing functions, thereby making the chip components more functional. Therefore, the functions of electronic devices including any of the above chip components are also richer, making the user experience of the electronic devices better.

Since the problem-solving principle of this electronic device is similar to that of the foregoing chip component, the implementation of this electronic device can refer to the implementation of the foregoing chip component, and repeated details will not be repeated.

Based on the same technical concept, embodiments of the present application also provide a chip (ie, the first chip in the above embodiment). The chip may include: at least one decoupling capacitor. The decoupling capacitor includes: a first pole and a second pole. , the first pole of the decoupling capacitor is used to directly connect to the power connection line of the processing chip, and the second pole is used to directly connect to the ground connection line of the processing chip.

In a possible implementation, the above-mentioned chip may include: a substrate, and a back-end metal interconnection layer located on the substrate. The decoupling capacitor may include: one sub-capacitor; alternatively, the decoupling capacitor may include: at least two sub-capacitors arranged in parallel, and the sub-capacitors are interdigital capacitors located in the same metal film layer in the subsequent metal interconnection layer.

In another possible implementation, the above-mentioned chip may include: a substrate, and a back-end metal interconnection layer located on the substrate. The subsequent metal interconnection layer may include: a first metal layer and a second metal layer that are stacked, the first pole of the decoupling capacitor is located in the first metal layer, and the second pole is located in the second metal layer.

In another possible implementation, the decoupling capacitor may include: a field effect transistor. The field effect transistor includes: a first terminal, a second terminal and a control terminal. The first terminal serves as the first pole of the decoupling capacitor, and the control terminal As the second pole of the decoupling capacitor.

In another possible implementation, the decoupling capacitor may be a stack capacitor or a trench capacitor.

In the embodiment of the present application, the above-mentioned chip can be a memory chip (Memory die) or an analog chip. Of course, the above-mentioned chip can also be other chips with sufficient space to install decoupling capacitors, which is not limited here.

For the specific implementation of the chip in the embodiment of the present application, reference can be made to the specific implementation of the first chip in the above embodiment, and repeated details will not be described again.

Based on the same technical concept, embodiments of the present application also provide a method for manufacturing a chip component. Figure 12 is a schematic flow chart of a method of manufacturing a chip component provided by an embodiment of the application. As shown in Figure 12, an embodiment of the application provides a method for manufacturing a chip component. Manufacturing methods for chip components may include:

S201. Provide a processing chip. The processing chip includes: a power connection line and a ground connection line;

S202. Provide a first chip. The first chip includes: at least one decoupling capacitor; the decoupling capacitor includes: a first pole and a second pole;

S203. Directly connect the first pole of the decoupling capacitor to the power connection line of the processing chip, and directly connect the second pole to the ground connection line of the processing chip.

For the specific implementation of the chip component manufacturing method in the embodiment of the present application, reference can be made to the specific implementation of the chip component in the above embodiment, and repeated details will not be described again.

Although the preferred embodiments of the present application have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of this application.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of this application and equivalent technologies, then this application is also intended to include these modifications and variations.

Claims (22)

1. A chip component, characterized by including: a processing chip and a first chip;

   The processing chip includes: a power connection line and a ground connection line;

   The first chip includes: at least one decoupling capacitor; the decoupling capacitor includes: a first pole and a second pole; the first pole of the decoupling capacitor is connected to the power connection line of the processing chip Directly connected, the second pole is directly connected to the ground connection line of the processing chip.
2. The chip assembly of claim 1, wherein the first chip includes: a substrate, and a back-end metal interconnect layer located on the substrate;

   The decoupling capacitor includes: one sub-capacitor; or, the decoupling capacitor includes: at least two sub-capacitors arranged in parallel;

   The sub-capacitor is an interdigital capacitor located in the same metal film layer in the subsequent metal interconnection layer.
3. The chip assembly of claim 1, wherein the first chip includes: a substrate, and a back-end metal interconnect layer located on the substrate;

   The back-end metal interconnection layer includes: a first metal layer and a second metal layer arranged in a stack;

   The first pole of the decoupling capacitor is located in the first metal layer, and the second pole is located in the second metal layer.
4. The chip assembly of claim 1, wherein the decoupling capacitor includes: a field effect transistor;

   The field effect transistor includes: a first terminal, a second terminal and a control terminal, the first terminal serves as the first pole of the decoupling capacitor, and the control terminal serves as the third pole of the decoupling capacitor. Two poles.
5. The chip assembly of claim 1, wherein the decoupling capacitor is a stacked capacitor or a trench capacitor.
6. The chip assembly according to any one of claims 1 to 5, wherein the processing chip and the first chip are stacked;

   The first chip includes: a power through silicon via and a ground through silicon via; the power through silicon via is connected to the power connection line in the processing chip, and the ground through silicon via is connected to the power connection line in the processing chip. The ground connection wire is connected;

   The first pole of the decoupling capacitor is connected to the power connection line through the power through silicon via, and the second pole is connected to the ground connection line through the ground through silicon via.
7. The chip assembly of claim 6, further comprising: a rewiring layer;

   The rewiring layer is located on a side of the first chip facing away from the processing chip; or, the rewiring layer is located on a side of the processing chip facing away from the first chip.
8. The chip assembly according to claim 6 or 7, wherein the processing chip and the first chip are electrically connected through micro bumps; or, the processing chip and the first chip are electrically connected through hybrid bonding. way to achieve electrical connection.
9. The chip assembly according to any one of claims 6 to 8, further comprising: a second chip;

   The second chip is located on a side of the first chip away from the processing chip.
10. The chip assembly according to any one of claims 1 to 5, further comprising: a connecting component;

    The processing chip and the first chip are arranged on the same layer, and the connecting component is located on the same side of the processing chip and the first chip;

    The first pole and the second pole of the decoupling capacitor are respectively connected to the power connection line and the ground connection line through the connection component.
11. The chip assembly of claim 10, wherein the connection component includes: a rewiring layer;

    The rewiring layer includes: a first connection line and a second connection line;

    The first pole of the decoupling capacitor is connected to the power connection line through the first connection line, and the second pole is connected to the ground connection line through the second connection line.
12. The chip assembly of claim 10, wherein the connection component includes: an interconnection bridge;

    The interconnection bridge includes: a first interconnection line and a second interconnection line;

    The first pole of the decoupling capacitor is connected to the power connection line through the first interconnection line, and the second pole is connected to the ground connection line through the second interconnection line.
13. The chip assembly of claim 10, wherein the connection component includes: a first lead and a second lead;

    The first pole of the decoupling capacitor is connected to the power connection line through the first lead, and the second pole is connected to the ground connection line through the second lead.
14. The chip component according to any one of claims 1 to 10, wherein the first chip is a memory chip or an analog chip.
15. An electronic device, characterized by comprising: the chip component according to any one of claims 1 to 14 and a housing, the housing covering the chip component.
16. A chip, characterized in that it includes: at least one decoupling capacitor;

    The decoupling capacitor includes: a first pole and a second pole. The first pole of the decoupling capacitor is used to directly connect to the power connection line of the processing chip. The second pole is used to connect to the processing chip. The ground connection wire is connected directly.
17. The chip of claim 16, wherein the chip includes: a substrate, and a back-end metal interconnection layer located on the substrate;

    The decoupling capacitor includes: one sub-capacitor; or, the decoupling capacitor includes: at least two sub-capacitors arranged in parallel;

    The sub-capacitor is an interdigital capacitor located in the same metal film layer in the subsequent metal interconnection layer.
18. The chip of claim 16, wherein the chip includes: a substrate, and a back-end metal interconnection layer located on the substrate;

    The back-end metal interconnection layer includes: a first metal layer and a second metal layer arranged in a stack;

    The first pole of the decoupling capacitor is located in the first metal layer, and the second pole is located in the second metal layer.
19. The chip of claim 16, wherein the decoupling capacitor includes: a field effect transistor;

    The field effect transistor includes: a first terminal, a second terminal and a control terminal, the first terminal serves as the first pole of the decoupling capacitor, and the control terminal serves as the third pole of the decoupling capacitor. Two poles.
20. The chip of claim 16, wherein the decoupling capacitor is a stacked capacitor or a trench capacitor.
21. The chip according to any one of claims 16 to 20, characterized in that the chip is a memory chip or an analog chip.
22. A method for manufacturing a chip component, which is characterized by including:

    A processing chip is provided, and the processing chip includes: a power connection line and a ground connection line;

    A first chip is provided, the first chip includes: at least one decoupling capacitor; the decoupling capacitor includes: a first pole and a second pole;

    The first pole of the decoupling capacitor is directly connected to the power connection line of the processing chip, and the second pole is connected to the The ground connection wire of the processing chip is connected directly.