WO2022261806A1

WO2022261806A1 - Chip stacking structure and manufacturing method, wafer stacking structure, and electronic device

Info

Publication number: WO2022261806A1
Application number: PCT/CN2021/099953
Authority: WO
Inventors: 夏禹; 朱靖华; 朱继锋; 雷电; 王前文
Original assignee: 华为技术有限公司
Priority date: 2021-06-15
Filing date: 2021-06-15
Publication date: 2022-12-22
Also published as: CN117501443A

Abstract

Embodiments of the present application provide a chip stacking structure and a manufacturing method, a wafer stacking structure, and an electronic device, and relate to the technical field of semiconductors. In a 3D-IC stacking process, manufacturing costs are reduced while meeting requirements for bonding strength between chips. The present chip stacking structure comprises a first chip, a second chip, and a third chip that are stacked in sequence. The back surface of the second chip faces an active surface of the first chip, and the back surface of the third chip faces the active surface of the first chip. In the present chip stacking structure, the first chip and the second chip are bonded by using a fusion bonding process, and the third chip and the second chip are bonded by using a hybrid bonding process.

Description

Chip stack structure and manufacturing method, wafer stack structure, electronic device

technical field

The present application relates to the technical field of semiconductors, and in particular to a chip stacking structure and a manufacturing method, a wafer stacking structure, and electronic equipment.

Background technique

With the development of semiconductor technology, in order to meet the needs of users, the size of electronic equipment tends to be smaller and smaller, but the functions of the electronic equipment are more and more diversified. In this way, within the limited two-dimensional layout space of the electronic device, it is necessary to arrange components with higher integration and performance. At present, a plurality of chips can be stacked vertically one by one by using a three-dimensional (3 dimensions, 3D) integrated circuit chip (IC) stacking technology to form the above components. In order to improve the reliability of components, a bonding process with complex process and high bonding strength is usually used to bond two adjacent layers of chips. However, as the number of chip stacking layers increases, multiple bonding processes with complex processes and high bonding strength will lead to an increase in manufacturing costs.

Contents of the invention

Embodiments of the present application provide a chip stacking structure and manufacturing method, a wafer stacking structure, and electronic equipment, which are used to reduce manufacturing costs while ensuring that the bonding strength between chips meets requirements during the 3D-IC stacking process.

In order to achieve the above object, the application adopts the following technical solutions:

According to a first aspect of the embodiments of the present application, a chip stacking structure is provided. The chip stack structure includes a first chip, a second chip and a third chip. Wherein, the second chip is arranged on the side where the active surface of the first chip is located, and the passive surface of the second chip faces the active surface of the first chip. The first chip and the second chip are bonded through a fusion bonding process. The third chip is arranged on the side where the active surface of the second chip is located. The passive surface of the third chip faces the active surface of the second chip. The third chip is bonded to the second chip through a hybrid bonding process.

To sum up, on the one hand, the above-mentioned chip stacking structure may include a plurality of stacked chips, so that it can have a high degree of integration in the vertical direction, reduce the size of the chip stacking structure in a two-dimensional plane, and then can be used in electronic devices In the limited two-dimensional layout space, components with high integration and performance are provided. On the other hand, it can be known from the above that the chips in the stacked chip structure adopt two bonding methods: fusion bonding and hybrid bonding. That is, when the number of chip stacking layers is low, for example, when the first chip and the second chip are stacked, fusion bonding with lower cost can be used between the first chip and the second chip. Since the number of layers of chips in the component formed by bonding the first chip and the second chip is relatively low, the fusion bonding can ensure the reliability of the component formed after the bonding of the first chip and the second chip. When the third chip is bonded to the bonded assembly of the first chip and the second chip, the number of layers of the chip stack increases. When the third chip is bonded to the second chip using a hybrid bonding process, the third chip and the second chip can be bonded not only through insulating materials, but also through metal materials, which improves the performance of the second chip. The bonding strength between the three chips and the second core. Therefore, the reliability of the chip stack structure formed after the bonding of the third chip, the second chip and the first chip can be improved. Therefore, during the 3D-IC stacking process, the bonding strength between chips can be guaranteed to meet the requirements, and the production cost can be reduced.

Optionally, the chip stack structure further includes a first dielectric layer, a second dielectric layer, a third dielectric layer, a plurality of first dummy pads arranged at intervals, and a plurality of second dummy pads arranged at intervals. The first dielectric layer is disposed between the first chip and the second chip. In order to bond the first chip and the second chip through a fusion bonding process, the first chip and the second chip are bonded through the first dielectric layer. The second dielectric layer is disposed on the active surface side of the second chip, and the plurality of first dummy pads are disposed in the second dielectric layer. The third dielectric layer is disposed on the passive surface of the third chip, and a plurality of second dummy pads are disposed in the third dielectric layer. In order to bond the third chip and the second chip through a hybrid bonding process, the third dielectric layer of insulating material between the third chip and the second chip is bonded to the second dielectric layer, and in addition, the third chip One second dummy pad among the plurality of second dummy pads is bonded to one first dummy pad among the plurality of first dummy pads with the metal material between the second chip.

Optionally, the chip stack structure further includes a first interconnection component. The first interconnection component includes a first redistribution layer, a second redistribution layer and a first via hole. The first redistribution layer is disposed in the first dielectric layer and coupled with the first chip. The second redistribution layer is disposed in the second dielectric layer and coupled with the second chip. The first via hole runs through the second chip. The first end of the first via hole is coupled to the first redistribution layer, and the second end of the first via hole is coupled to the second redistribution layer. In this way, the first chip can realize signal transmission between the first chip and the second chip through the above-mentioned first interconnection component. Since the first via hole in the first interconnection component runs through the second chip, and the base thickness of the second chip is very thin, about 50 μm, the first chip and the second chip can be vertically connected through the first interconnection component. The two chips are coupled so that the signal transmission path between the first chip and the second chip is shorter. In this case, compared with the scheme of coupling two side-by-side chips through wires in a two-dimensional plane, the signal transmitted by the chip stack structure provided by this application can have a higher bandwidth, which is beneficial to The performance of the chip stack structure is improved.

Optionally, the first interconnection component further includes a first conducting pad, disposed on a surface of the second redistribution layer away from the first redistribution layer, and coupled to the second redistribution layer. The chip stack structure also includes a second interconnection component. The second interconnection component includes a second via pad and a second via hole. The second conducting pad is disposed in the third dielectric layer and bonded with the first conducting pad. The second via hole runs through the third chip. The first end of the second via hole is coupled to the second via pad, and the second end of the second via hole is coupled to the third chip. In this way, the second redistribution layer can be coupled to the second conductive pad in the second interconnection assembly through the above-mentioned first conductive pad, so that the second chip can pass through the above-mentioned first conductive pad. Signal transmission is realized between the through pad and the second interconnection component and the third chip. As mentioned above, the second via hole in the second interconnection component runs through the third chip, so the second chip and the third chip can be coupled vertically through the second interconnection component, so that the second chip and the third chip The signal transmission path of the chip is shorter, which is conducive to improving the performance of the chip stack structure.

Optionally, the chip stack structure further includes a fourth chip and a fourth dielectric layer. The fourth chip is disposed on a side of the third chip away from the second chip, and the passive surface of the fourth chip faces the active surface of the third chip. The fourth dielectric layer is disposed between the third chip and the fourth chip. The third chip and the fourth chip are bonded through the fourth dielectric layer. In this way, when the number of chips in the chip stack structure increases, the first chip and the second chip can be bonded through the first dielectric layer by adopting a low-cost fusion bonding process as described above. Moreover, the third chip and the fourth chip are bonded through the fourth dielectric layer by adopting a fusion bonding process. Then, the component formed by bonding the first chip and the second chip is bonded with the component formed by bonding the third chip and the fourth chip by using a hybrid bonding process with higher bonding strength. In this case, when the number of stacked chips is small, the bonding process between the chips can adopt a fusion bonding process with a lower cost. When the number of stacked chips is large, hybrid bonding with high bonding strength is used between the chips, so that the reliability of the chip stacking structure can be improved while reducing the manufacturing cost. In addition, when the number of stacked chips in the chip stacking structure increases, a part of the chips can be grouped and bonded to form a stacked component under the premise that the fusion bonding process can ensure reliability. Then, a hybrid bonding process with higher bonding strength is used to bond multiple stacked components in pairs. In this case, compared to the solution of stacking chips layer by layer, in the embodiment of the present application, when a chip in one of the stacking components has a stacking error or a deviation in alignment accuracy during the stacking process, it can be separately The stack assembly can be replaced without causing failure of the entire chip stack structure.

Optionally, the chip stack structure further includes a fifth dielectric layer. The fifth dielectric layer is disposed on the active surface of the fourth chip. The chip stack structure also includes a third interconnection component. The third interconnection component includes a third redistribution layer, a fourth redistribution layer and a third via hole. Wherein, the third redistribution layer is disposed in the fourth dielectric layer and coupled with the third chip and the first interconnection component. The fourth redistribution layer is disposed in the fifth dielectric layer and coupled with the fourth chip. The third via hole runs through the fourth chip. The first end of the third via hole is coupled to the third redistribution layer, and the second end of the third via hole is coupled to the fourth redistribution layer. In this way, the fourth chip can realize signal transmission between the third chip and the third chip through the third interconnection component.

Optionally, the chip stack structure further includes a plurality of third conductive pads arranged at intervals and a plurality of fourth conductive pads arranged at intervals. A plurality of third conducting pads are disposed in the second dielectric layer and coupled with the second chip. While making the first dummy pad, the preparation of the third conductive pad can be completed. A plurality of fourth conducting pads are disposed in the third dielectric layer and coupled with the third chip. While fabricating the second dummy pad, fabrication of the fourth conductive pad can be completed. In this case, one third conductive pad among the plurality of third conductive pads is bonded to one fourth conductive pad among the plurality of fourth conductive pads. In this way, when hybrid bonding is used between the second chip and the third chip, signal transmission can be realized not only through the first interconnection component and the second interconnection component, but also through the third conductive pads coupled to each other. and the fourth conduction pad to realize signal transmission, so that the signal bandwidth of the chip stack structure can be increased.

Optionally, the chip farthest from the first chip in the chip stack structure is the bottom chip. The chip stack structure also includes a plurality of interface pads arranged at intervals. The plurality of interface pads are arranged in the dielectric layer on the side of the active surface of the bottom chip. A plurality of interface pads are used to couple the bottom chip with external components. In this way, since other chips in the above-mentioned chip stacking structure can perform signal transmission between the above-mentioned interconnection component structure and the bottom chip, when the bottom chip couples the above-mentioned interface pads to the external components, it can make the whole The chip stack structure performs signal transmission through the above-mentioned external components, such as an adapter board and a PCB.

Optionally, the bottom chip is a logic chip, and at least one chip other than the bottom chip in the chip stack structure is a memory chip. In this way, the chip stack structure can form a high-bandwidth memory.

In a second aspect of the embodiments of the present application, a wafer stacking structure is provided. The wafer stack structure includes a first wafer, a second wafer and a third wafer. The second wafer is arranged on the side where the active surface of the first wafer is located, and the passive surface of the second wafer faces the active surface of the first wafer. The first wafer is bonded to the second wafer through a fusion bonding process. The third wafer is arranged on the side of the second wafer away from the first wafer; the passive surface of the third wafer faces the active surface of the second wafer. The third wafer is bonded to the second wafer by a hybrid bonding process. The above-mentioned wafer stacking structure has the same technical effect as that of the chip stacking structure provided in the foregoing embodiments, which will not be repeated here.

Optionally, the wafer stack structure further includes a first dielectric layer, a second dielectric layer, a third dielectric layer, a plurality of first dummy pads arranged at intervals, and a plurality of second dummy pads arranged at intervals. In order to bond the first wafer and the second wafer through a fusion bonding process, the first dielectric layer is arranged between the first wafer and the second wafer, and the first wafer and the second wafer pass through The first dielectric layer is bonded. The second dielectric layer is disposed on one side of the active surface of the second wafer. A plurality of first dummy pads are disposed in the second dielectric layer. The third dielectric layer is disposed on the passive surface of the third wafer. A plurality of second dummy pads are disposed in the third dielectric layer. In order to bond the third wafer to the second wafer through a hybrid bonding process, the third dielectric layer of insulating material between the third wafer and the second wafer is bonded to the second dielectric layer, and in addition , the metal material between the third wafer and the second wafer. One of the plurality of second dummy pads is bonded to one of the plurality of first dummy pads. combine.

Optionally, the wafer stack structure further includes a first interconnection component. The first interconnection component includes a first redistribution layer, a second redistribution layer and a first via hole. The first redistribution layer is disposed in the first dielectric layer and coupled with the first wafer. The second redistribution layer is disposed in the second dielectric layer and coupled with the second wafer. The first via hole runs through the second wafer. The first end of the first via hole is coupled to the first redistribution layer, and the second end of the first via hole is coupled to the second redistribution layer. The technical effect of the above-mentioned first interconnection component is the same as that described above, and will not be repeated here.

Optionally, the first interconnection component further includes a first conducting pad disposed on a surface of the second redistribution layer away from the first redistribution layer. The chip stack structure also includes a second interconnection component. The second interconnection component includes a second via pad and a second via hole. The second conducting pad is disposed in the third dielectric layer and bonded to the first conducting pad. The second via hole runs through the third wafer. The first end of the second via hole is coupled to the second via pad, and the second end of the second via hole is coupled to the third wafer. The technical effect of the above-mentioned second interconnection component is the same as that described above, and will not be repeated here.

Optionally, the wafer stack structure further includes a fourth wafer and a fourth dielectric layer. The fourth wafer is disposed on a side of the third wafer away from the second wafer, and the passive surface of the fourth wafer faces the active surface of the third wafer. The fourth dielectric layer is disposed between the third wafer and the fourth wafer. The third wafer and the fourth wafer are bonded through the fourth dielectric layer. The fourth chip in the chip stack structure is obtained by dicing the fourth wafer. The fourth wafer has the same technical effect as that of the fourth chip provided by the foregoing embodiments, which will be described in detail here.

Optionally, the wafer stack structure further includes a fifth dielectric layer. The fifth dielectric layer is disposed on the active surface of the fourth wafer. The chip stack structure also includes a third interconnection component. The third interconnection assembly includes a third redistribution layer and a fourth redistribution layer. The third redistribution layer is disposed in the fourth dielectric layer and coupled with the third wafer and the first interconnection component. The fourth redistribution layer is disposed in the fifth dielectric layer and coupled with the fourth wafer. The third via hole runs through the fourth wafer. The first end of the third via hole is coupled to the third redistribution layer, and the second end of the third via hole is coupled to the fourth redistribution layer. The technical effect of the above-mentioned third interconnection component is the same as that described above, and will not be repeated here.

Optionally, the wafer stack structure further includes a plurality of third conduction pads arranged at intervals and a plurality of fourth conduction pads arranged at intervals. A plurality of third conducting pads are disposed in the second dielectric layer and coupled with the second wafer. While making the first dummy pad, the preparation of the third conductive pad can be completed. A plurality of fourth conducting pads are disposed in the third dielectric layer and coupled with the third wafer. While fabricating the second dummy pad, fabrication of the fourth conductive pad can be completed. In this case, one third conductive pad among the plurality of third conductive pads is bonded to one fourth conductive pad among the plurality of fourth conductive pads. In this way, when hybrid bonding is used between the second wafer and the third wafer, signal transmission can be realized not only through the first interconnection component and the second interconnection component, but also through the third interconnection coupled to each other. The welding pad and the fourth conductive pad implement signal transmission, thereby increasing the signal bandwidth of the wafer stack structure.

A third aspect of the embodiments of the present application provides an electronic device, including an external component and at least one chip stack structure as described above coupled with the external component. The electronic device has the same technical effect as that of the chip stacking structure provided by the foregoing embodiments, which will not be repeated here.

Optionally, the external component includes a packaging substrate, an interposer, or at least one fan-out redistribution layer. In this case, the bottom chip in the chip stack structure can realize signal transmission between the above-mentioned external components and the PCB.

According to the fourth aspect of the embodiment of the present application, there is provided a method for manufacturing a stacked chip structure, the method comprising: firstly, setting a second wafer on the side where the active surface of the first wafer is located, and the second wafer without The source surface faces the active surface of the first wafer, and the first wafer and the second wafer are bonded by a fusion bonding process. Next, set a third wafer on the side where the active surface of the second wafer is located, with the passive surface of the third wafer facing the active surface of the second wafer, and pass a fusion bonding process, or, mixed The bonding process bonds the third wafer to the second wafer.

In this way, on the one hand, in the process of manufacturing the chip stack structure provided by the embodiment of the present application, the first wafer (to obtain the first chip after cutting) and the second wafer (to obtain the second chip after cutting) Wafer to wafer bonding (wafer to wafer bonding, W2W bonding) method is used to stack in sequence. Next, the stack assembly composed of the first wafer and the second wafer is bonded to the third wafer (the third chip is obtained after dicing) by W2W bonding to form a wafer stack structure. In this case, the wafer stack structure may be cut along the cutting line on the outermost wafer of the wafer stack structure to form a plurality of chip stack structures. Therefore, in the process of manufacturing the stacked chip structure, it is only necessary to align wafers to wafers, instead of aligning individual chips, thereby reducing alignment accuracy and improving production efficiency. In addition, compared with the scheme of bonding chips (or called grains) and chips (die to die, D2D) and the scheme of bonding chips and wafers (die to wafer, D2W), this application In the W2W bonding solution provided in the embodiment, the chip stack structure 20 is obtained by directly bonding the wafers and cutting them, so there is no need to use known good dies (KGD) to test the cut dies one by one , so that the manufacturing process can be simplified and the production cost can be reduced. On the other hand, there is no need to add an organic adhesive layer during the bonding process of any two wafers, so the probability of organic impurity contamination caused by the introduction of organic materials can be reduced during the fabrication of chip stack structures. On the other hand, in the process of thinning the passive surface of the second wafer and bonding the passive surface of the second wafer with the active surface of the first wafer, the wafer carrier Both can support the second wafer, thereby reducing the probability of warping of the second wafer during thinning and stacking with other wafers. Furthermore, the wafer stack structure and the yield rate of the chip stack structure formed by cutting the wafer stack structure can be improved.

Optionally, the second wafer is arranged on the side where the active surface of the first wafer is located, and the method of bonding the first wafer and the second wafer through a fusion bonding process includes: The round active face forms the first dielectric layer. Next, a second dielectric layer is formed on the active surface of the second wafer, the wafer carrier is bonded to the surface of the second dielectric layer away from the second wafer, and the passive surface of the second wafer is thinning. Next, the passive surface of the second wafer is bonded to the active surface of the first wafer through the first dielectric layer, and the wafer carrier is removed. In addition, a third wafer is arranged on the side where the active surface of the second wafer is located, and the method of bonding the third wafer to the second wafer through a fusion bonding process or a hybrid bonding process includes : forming a third dielectric layer on the passive surface of the third wafer. The method for bonding the third wafer to the second wafer includes: bonding the third wafer to the second wafer through at least the third dielectric layer and the second dielectric layer. Specifically, when the third wafer and the second wafer are bonded by a fusion bonding process, the third wafer and the second wafer can be bonded through the third dielectric layer and the second dielectric layer. combine. Or, when the third wafer and the second wafer are bonded using a hybrid bonding process, the third wafer and the second wafer can be bonded not only through the third dielectric layer and the second dielectric layer It can also be bonded by metal materials.

Optionally, after the third wafer is bonded to the second wafer, the stacking method of the above-mentioned chip wafers further includes cutting the first wafer, the second wafer and the third wafer along the cutting line, which can Multiple chip stack structures are obtained.

Optionally, after the second dielectric layer is formed on the active surface of the second wafer, the method for manufacturing the chip stack structure further includes: manufacturing a plurality of first dummy pads arranged at intervals in the second dielectric layer. After forming the third dielectric layer on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: manufacturing a plurality of second dummy pads arranged at intervals in the third dielectric layer. Bonding the third wafer to the second wafer through at least the third dielectric layer and the second dielectric layer includes: bonding the third dielectric layer to the second dielectric layer, and bonding a plurality of One of the first dummy pads is bonded to one of the plurality of second dummy pads. In this case, two bonding methods, fusion bonding and hybrid bonding, are used in the process of fabricating the chip stack structure. That is, when the number of stacked wafers is relatively low, for example, when the first wafer and the second wafer are stacked, fusion bonding with a lower cost can be used between the first wafer and the second wafer. Since the number of wafer layers in the component formed by bonding the first wafer and the second wafer is relatively low, the fusion bonding can fully ensure the reliability of the component formed after the bonding of the first wafer and the second wafer. When the third wafer is bonded to the bonded assembly of the first and second wafers, the number of layers in the wafer stack increases. When the hybrid bonding process is used to bond the third wafer to the second wafer, the third wafer and the second wafer can be bonded not only through insulating materials, but also through metal materials , improving the bonding strength between the third wafer and the second chip. Therefore, the reliability of the wafer stack structure formed after the bonding of the third wafer, the second wafer and the first wafer can be improved.

Optionally, after the second dielectric layer is formed on the active surface of the second wafer, the method for manufacturing the chip stack structure further includes: manufacturing a plurality of third conductive pads arranged at intervals in the second dielectric layer. A plurality of third conducting pads are coupled to the second wafer. After the third dielectric layer is formed on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: manufacturing a plurality of fourth conductive pads arranged at intervals in the third dielectric layer. A plurality of fourth conducting pads are coupled to the third wafer. Bonding the third wafer to the second wafer through at least the third dielectric layer and the second dielectric layer further includes: bonding one of the plurality of third conductive pads to the plurality of third conductive pads One of the fourth conductive pads is bonded to each other. The technical effects of the above-mentioned third conductive pad and the fourth conductive pad are the same as those described above, and will not be repeated here.

Optionally, bonding the third wafer to the second wafer through at least the third dielectric layer and the second dielectric layer includes: bonding the third dielectric layer to the second dielectric layer. In this way, each wafer in the stack assembly and the bonding manner between different stack assemblies can all adopt fusion bonding, thereby reducing the manufacturing cost.

Optionally, after the first dielectric layer is formed on the active surface of the first wafer, before the passive surface of the second wafer is bonded to the active surface of the first wafer through the first dielectric layer, the The chip stacking method further includes: forming a first redistribution layer coupled with the first wafer in the first dielectric layer. After the passive surface of the second wafer is bonded to the active surface of the first wafer through the first dielectric layer, the third wafer is bonded to the second wafer through at least the third dielectric layer and the second dielectric layer. Before wafer bonding, the method for manufacturing the chip stack structure further includes: forming a first via hole penetrating through the second wafer, and a second via hole disposed in the second dielectric layer and coupled to the second wafer. Rewiring layers. The first end of the first via hole is coupled to the first redistribution layer, and the second end is coupled to the second redistribution layer. The first redistribution layer, the first via hole and the second redistribution layer may constitute a first interconnection component. The technical effect of the first interconnection component is the same as that described above, and will not be repeated here.

Optionally, before forming the third dielectric layer on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: firstly, forming a fourth dielectric layer on the active surface of the third wafer. Next, a second via hole is formed in the third wafer, and a third redistribution layer is formed in the fourth dielectric layer. The third redistribution layer is coupled to the second end of the second via hole and the third wafer. Next, a fifth dielectric layer is formed on the active surface of the fourth wafer, the wafer carrier is bonded to the surface of the fifth dielectric layer away from the fourth wafer, and the passive surface of the fourth wafer is thinning. Next, the passive surface of the fourth wafer is bonded to the active surface of the third wafer through the fourth dielectric layer, and the wafer carrier is removed. Next, forming a third via hole penetrating through the fourth wafer, and a fourth redistribution layer disposed in the fifth dielectric layer and coupled with the fourth wafer. The first end of the third via hole is coupled to the third redistribution layer, and the second end is coupled to the fourth redistribution layer. The wafer carrier is bonded to the surface of the fifth dielectric layer away from the fourth wafer, and the passive surface of the third wafer is thinned to expose the first end of the second via hole. After the third dielectric layer is formed on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: manufacturing a second conductive pad in the third dielectric layer. The second via pad is coupled to the first end of the second via hole and the second redistribution layer. In this way, the above-mentioned fourth wafer can be added in the chip stacking structure, so that the integration degree of the wafer stacking structure can be improved. In addition, the above-mentioned second via hole penetrating through the third wafer is formed before the bonding of the third wafer and the fourth wafer by adopting a mid-section drilling process. Therefore, compared with the scheme of forming the second via hole by using the post-drilling process, the mid-section drilling process does not need to form an etch stop layer covering the surface of the third redistribution layer when making the second via hole, and it is not necessary for the second via hole to be formed. The three wafers and the etching barrier layer are sequentially etched step by step, so that the third redistribution layer is coupled with the second via hole. Therefore, steps such as step-by-step etching and formation of an etching barrier layer need not be considered in the process of manufacturing the second via hole by adopting the mid-section drilling process, which is beneficial to reduce the difficulty of the process.

Optionally, before forming the third dielectric layer on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: first, forming a fourth dielectric layer on the active surface of the third wafer, and A third rewiring layer is formed in the fourth dielectric layer. Next, a fifth dielectric layer is formed on the active surface of the fourth wafer, and the wafer carrier is bonded to the surface of the fifth dielectric layer away from the fourth wafer; thinning. Next, the passive surface of the fourth wafer is bonded to the active surface of the third wafer through the fourth dielectric layer, and the wafer carrier is removed. Next, forming a third via hole penetrating through the fourth wafer, and a fourth redistribution layer disposed in the fifth dielectric layer and coupled to the fourth wafer. The first end of the third via hole is coupled to the third redistribution layer, and the second end is coupled to the fourth redistribution layer. Next, the wafer carrier is bonded to the surface of the fifth dielectric layer away from the fourth wafer; and the passive surface of the third wafer is thinned. After the third dielectric layer is formed on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: forming a second via hole penetrating through the third wafer, and forming a second via hole in the third dielectric layer. The conducting pad; the second conducting pad is coupled with the first end of the second via hole and the second redistribution layer. In this way, the above-mentioned fourth wafer can be added in the chip stacking structure, so that the integration degree of the wafer stacking structure can be improved. In addition, the second via hole penetrating through the third wafer is formed after the bonding of the third wafer and the fourth wafer by adopting a post-drilling process.

Description of drawings

FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

FIG. 2a is a schematic diagram of a chip stack structure provided by an embodiment of the present application;

Fig. 2b is a schematic structural diagram of the first chip in Fig. 2a;

FIG. 3 is a schematic diagram of another chip stack structure provided by the embodiment of the present application;

FIG. 4 is a flow chart of a method for manufacturing a chip stack structure provided in an embodiment of the present application;

Fig. 5a, Fig. 5b, Fig. 5c, Fig. 5d, Fig. 5e and Fig. 5f are sequential structural schematic diagrams corresponding to the steps of making the first stacked assembly;

Figure 6a, Figure 6b, and Figure 6c are sequentially a structural schematic diagram corresponding to the steps of making the second stacked assembly;

Fig. 7 is a structural schematic diagram obtained by bonding the first stack assembly shown in Fig. 5f and the second stack assembly shown in Fig. 6c;

FIG. 8 is a schematic top view of a wafer stack structure provided in an embodiment of the present application;

Fig. 9a is a schematic diagram of another first stacking assembly provided by the embodiment of the present application;

Fig. 9b is a schematic diagram of another second stacking assembly provided by the embodiment of the present application;

Fig. 9c is a structural schematic diagram obtained by bonding the first stack assembly shown in Fig. 9a and the second stack assembly shown in Fig. 9b;

FIG. 10 is a schematic structural diagram of another wafer stack structure provided in the embodiment of the present application;

FIG. 11 is a schematic diagram of a chip stack structure obtained by cutting the wafer stack structure shown in FIG. 10;

Fig. 12a, Fig. 12b, Fig. 12c and Fig. 12d are sequentially another structural schematic diagram corresponding to the steps of making the second stacked assembly;

Fig. 13 is a schematic structural diagram obtained by bonding the first stack assembly shown in Fig. 5f and the second stack assembly shown in Fig. 12d;

FIG. 14 is a schematic diagram of a chip stack structure obtained by cutting the wafer stack structure shown in FIG. 13;

FIG. 15 is a schematic top view of another chip stack structure provided by the embodiment of the present application;

Fig. 16a, Fig. 16b, Fig. 16c and Fig. 16d are sequentially another structural schematic diagram corresponding to the step of manufacturing the second stack assembly.

Reference signs:

01-electronic equipment; 10-external components; 20-chip stacking structure; 21-first stacking assembly; 211-first chip; 301-first dielectric layer; 212-second chip; 302-second dielectric layer 22-the second stacking component; 213-the third chip; 303-the third dielectric layer; 401-the first dummy pad; 402-the second dummy pad; 50-the first interconnection component; 501-the first Redistribution layer; 502-second redistribution layer; 511-first via hole; 100-substrate; 101-circuit structure; 304-fourth dielectric layer; 521-first conduction pad; 02-wafer Stack structure; 51-second interconnection component; 522-second via pad; 512-second via hole; 503-third rewiring layer; 131-first wafer; 200-groove; 132- The second wafer; 31-wafer carrier; 133-the third wafer; 523-the third conducting pad; 524-the fourth conducting pad; 134-the fourth wafer; 305-the fifth dielectric layer; 52-third interconnection component; 513-third via hole; 504-fourth rewiring layer; 214-fourth chip; 600-interface pad; 215-fifth chip; 306-sixth dielectric Floor.

detailed description

The following will describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.

Hereinafter, the terms "first", "second", etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature.

In addition, in this application, directional terms such as "upper" and "lower" are defined relative to the schematic placement of components in the drawings. It should be understood that these directional terms are relative concepts, and they are used for relative For descriptions and clarifications, it may vary accordingly according to changes in the orientation of parts placed in the drawings.

In this application, unless otherwise specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary. In addition, the term "coupled" may be an electrical connection for signal transmission. "Coupling" can be a direct electrical connection, or an indirect electrical connection through an intermediary.

An embodiment of the present application provides an electronic device. The electronic device includes a mobile phone (mobile phone), a tablet computer (pad), a computer, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (virtual reality, VR) terminal device, an augmented reality (augmented reality, AR ) Terminal equipment and other electronic products. The embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.

As shown in FIG. 1 , the electronic device 01 includes an external component 10 and at least one chip stack structure 20 coupled to the external component 10 . Wherein, the external component 10 may include at least one of a packaging substrate, a silicon-based interposer, and at least one redistribution layer (RDL) of fan-out (integrated fan-out, InFO).

The above-mentioned chip stack structure 20 may include a plurality of stacked chips. The chips in the chip stack structure 20 may be logic chips or memory chips. The chip stack structure 20 may be coupled with a ball grid array (BGA) as shown in FIG. 1 , or a plurality of copper pillar bumps arranged in an array. In addition, the electronic device 01 also includes printed circuit boards (printed circuit boards, PCB). The above-mentioned external component 10 can also be coupled with the PCB through the above-mentioned electrical connector. In this case, the chip stack structure 20 can realize signal transmission with other chips or chip stack structures on the PCB through the external component 10 .

The above chip stack structure 20 will be described below.

In some embodiments of the present application, as shown in FIG. 2 a (which is a partial structure of the chip stack structure 20 ), the chip stack structure 20 may include a first chip 211 , a second chip 212 and a third chip 213 . Hereinafter, for convenience of description, the chip stack structure 20 is divided into a first stack component 21 and a second stack component 22 . Wherein, the first stack assembly 21 includes the above-mentioned first chip 211 and the second chip 212 . The second stack assembly 22 includes the aforementioned third chip 213 .

It should be noted that any one of the above chips, such as the first chip 211 as shown in FIG. 2b, may include a substrate 100, such as a glass substrate, an amorphous silicon (a-Si) substrate, or a silicon carbide (SiC) substrate. In addition, the first chip 211 may further include a circuit structure 101 disposed on the substrate 100 . In the embodiment of the present application, the surface of the circuit structure 101 in the first chip 211 away from the substrate 100 is called the active surface F of the chip, and the surface of the substrate 100 away from the circuit structure 101 is called the passive surface B .

The second chip 212 is disposed on the side where the active surface F of the first chip 211 is located, and the passive surface B of the second chip 212 faces the active surface F of the first chip 211 . The first stack assembly 21 further includes a first dielectric layer 301 and a second dielectric layer 302 . The first dielectric layer 301 is disposed between the first chip 211 and the second chip 212 . The first chip 211 and the second chip 212 may be bonded using a fusion bonding process. In this case, the first chip 211 and the second chip 212 may be bonded through the first dielectric layer 301 . The second dielectric layer 302 is disposed on the side of the active surface F of the second chip 212 .

It should be noted that the bonding between chips is a process in which the atoms at the chip interface are combined into one body through van der Waals force, molecular force or even atomic force under the action of external energy.

In addition, the above-mentioned first stack assembly 21 further includes a plurality of first dummy pads (pads) 401 arranged at intervals. A plurality of first dummy pads 401 are disposed in the second dielectric layer 302 . In the present application, the material constituting the second dummy pad 402 is a conductive material, such as at least one of gold, silver, copper, and aluminum. In the embodiment of the present application, the material constituting the second dummy pad 402 may be pure copper. There is no coupling between the plurality of first dummy pads 401 and the second chip 212 .

On this basis, in order to enable signal transmission between the first chip 211 and the second chip 212 in the first stacking assembly 21, the above-mentioned first stacking assembly 21 may also include a first interconnection assembly as shown in FIG. 2a 50. The first interconnection component 50 may include a first re-distribution layer (re-distribution layer, RDL) 501, a second re-distribution layer 502, and a first through hole (through Si via, TSV) 511.

The first redistribution layer 501 is disposed in the first dielectric layer 301 and coupled to the first chip 211 . The first redistribution layer 501 includes multiple dielectric layers and metal wires disposed between two adjacent dielectric layers. Adjacent metal wires can be electrically connected through via holes formed on the dielectric layer. In this case, the coupling between the first redistribution layer 501 and the first chip 211 means that the metal traces in the first redistribution layer 501 and the circuit structure 101 in the first chip 211 (as shown in FIG. 2b ) phase coupling.

Similarly, the second redistribution layer 502 is disposed in the second dielectric layer 302 and coupled to the second chip 212 . At this time, the metal traces in the second redistribution layer 502 can be coupled with the circuit structure 101 in the second chip 212 . In addition, as shown in FIG. 2 a , the above-mentioned first via hole 511 may penetrate through the second chip 212 . Moreover, the first end of the first via hole 511 is coupled to the first redistribution layer 501 , and the second end of the first via hole 511 is coupled to the second redistribution layer 502 . In this way, the circuit structure 101 in the first chip 211 can be coupled to the circuit structure 101 in the second chip 212 through the first redistribution layer 501 , the first via hole 511 and the second redistribution layer 502 in sequence. Thus, signal transmission between the first chip 211 and the second chip 212 is realized.

In addition, as shown in FIG. 2 a , the above-mentioned second stack assembly 22 may further include a third dielectric layer 303 as shown in FIG. 2 a. The third chip 213 is disposed on the side where the active surface F of the second chip 212 is located, and the passive surface B of the third chip 213 faces the active surface F of the second chip 212 . The third dielectric layer 303 is disposed on the passive surface B of the third chip 213 .

The above-mentioned second stack assembly 22 may include a plurality of second dummy pads 402 arranged at intervals. A plurality of second dummy pads 402 are disposed in the third dielectric layer 303 . The material constituting the second dummy pad 402 may be the above-mentioned conductive material, such as pure copper material. The third chip 213 is bonded to the second chip 212 through a hybrid bonding process. In this case, the insulating material between the third chip 213 and the second chip 212 is bonded, that is, the third dielectric layer 303 is bonded to the second dielectric layer 302 . In addition, the metal material between the third chip 213 and the second chip 212 is bonded, that is, one of the multiple second dummy pads 402 and one of the multiple first dummy pads 401 The first dummy pads 401 are bonded to each other. There is no coupling between the plurality of second dummy pads 402 and the third chip 213 .

In addition, as shown in FIG. 3 , the above-mentioned first interconnection component 50 may further include a first conducting pad 521 . The first conducting pad 521 is disposed on a surface of the second redistribution layer 502 away from the first redistribution layer 501 , and is coupled to the second redistribution layer 502 .

The second stack assembly 22 also includes a second interconnection assembly 51 . The second interconnection component 51 may include a second via pad 522 and a second via hole 512 . Wherein, the second conducting pad 522 is disposed in the third dielectric layer 303 and bonded to the first conducting pad 521 . The second via hole 512 runs through the third chip 213 . A first end of the second via hole 512 is coupled to the second via pad 522 , and a second end of the second via hole 512 is coupled to the third chip 213 . The materials constituting the first conducting pad 521 and the second conducting pad 522 may be the same, such as pure copper.

In this case, in order to enable the second end of the second via hole 512 to be coupled with the third chip 213, the second stack assembly 22 further includes a fourth dielectric layer 304 as shown in FIG. The third redistribution layer 503 within the fourth dielectric layer 304 . The fourth dielectric layer 304 is disposed on the side of the active surface F of the third chip 213, a part of the third redistribution layer 503 is coupled with the circuit structure 101 in the third chip 213, and the other part can be connected with the above-mentioned first Second ends of the two via holes 512 are coupled.

In this way, the third chip 213 can perform signal transmission with the second chip 212 through the third redistribution layer 503 and the second via hole 512 . In addition, the third chip 213 can also pass through the third redistribution layer 503, the second via hole 512, the second conduction pad 522, the first conduction pad 521, the second redistribution layer 502, the first conduction The hole 511 and the first redistribution layer 501 perform signal transmission with the first chip 211 .

It can be seen from the above that the first chip 211 in the chip stack structure 20 can realize signal transmission between the first interconnection component 50 and the second chip 212 . Since the first via hole 511 in the first interconnection component 50 runs through the second chip 212, and the thickness of the substrate 100 of the second chip 212 is very thin, which can be about 50 μm, the first interconnection component 50 can vertically The first chip 211 and the second chip 212 are coupled so that the signal transmission paths of the first chip 211 and the second chip 212 are shorter. In this case, compared with the solution of coupling two side-by-side chips through wires in a two-dimensional plane, the signal transmitted by the chip stack structure 20 provided by the present application can have a higher bandwidth, thereby effectively It is beneficial to improve the performance of the chip stacking structure. Similarly, the second chip 212 can realize signal transmission between the second chip 212 and the third chip 213 through the above-mentioned first conductive pad 521 and the second interconnection component 51 . As mentioned above, the second via hole 512 in the second interconnection component 51 runs through the third chip 213, so the second chip 212 and the third chip 213 can be coupled vertically through the second interconnection component 51, so that The signal transmission paths of the second chip 212 and the third chip 213 are shorter, which is beneficial to improve the performance of the chip stack structure 20 .

In the embodiment of the present application, the above-mentioned chip stack structure 20 may be manufactured in a W2W bonding manner. The method for fabricating the above-mentioned chip stack structure 20 is illustrated below with an example.

example one

In this example, each via hole used to connect chips in different layers in the chip stack structure 20 is prepared by a post-drilling process. That is, the aforementioned via holes are formed on the wafers after stacking a plurality of wafers.

As shown in FIG. 4 , the manufacturing method of the chip stack structure 20 includes S101 - S104 .

S101 , a method for manufacturing a first stack component 21 . Wherein, the above S101 includes disposing the second wafer 132 on the side where the active surface F of the first wafer 131 is located. The passive surface B of the second wafer 132 faces the active surface F of the first wafer 131 , and the first wafer 131 and the second wafer 132 are bonded by a fusion bonding process.

Specifically, the above S101 includes: first, as shown in FIG. 5 a , cleaning the first wafer 131 , and forming a first dielectric layer 301 on the active surface F of the first wafer 131 . Then, a groove 200 is formed on the first dielectric layer 301 by photolithography. The specific photolithography process includes: forming a photoresist layer (not shown in the figure) on the surface of the first dielectric layer 301 away from the first wafer 131, and then patterning the photoresist layer by using a mask. and then forming a groove 200 on the first dielectric layer 301 by an etching process.

Next, as shown in FIG. 5 b , a first redistribution layer 501 coupled with the first wafer 131 is formed in the groove 200 . The first redistribution layer 501 is coupled to the circuit structure 101 in the first wafer 131 (as shown in FIG. 2 b ).

It should be noted that the above-mentioned first wafer 131 includes the substrate 100 and the circuit structure 101 as shown in FIG. 2 b . In addition, a plurality of cutting lines (not shown in the figure) intersecting horizontally and vertically are arranged on the first wafer 131 , and the area surrounded by adjacent cutting lines intersecting horizontally and vertically is the area where the first chip 211 is located. Therefore, a plurality of the above-mentioned first chips 211 can be obtained after cutting the first wafer 131 along the cutting line.

Next, the second wafer 132 as shown in FIG. 5 c is cleaned, and a second dielectric layer 302 is formed on the active surface F of the second wafer 132 . Then, as shown in FIG. 5d, the wafer carrier 31 is bonded to the surface of the second dielectric layer 302 away from the second wafer 132, and to the passive surface B of the second wafer 132 (ie, the second wafer 132). In the circle, the surface of the substrate 100 away from the circuit structure 101 is thinned. For example, the thickness of the substrate 100 of the second wafer 132 can be reduced to about 50 μm. As mentioned above, a plurality of second chips 212 can be obtained after cutting the second wafer 132 along the cutting line on the second wafer 132 .

It should be noted that, in the embodiment of the present application, the material of the wafer carrier 31 may be the same as that of the substrate constituting the above-mentioned wafer.

Next, as shown in FIG. 5 e , a fusion bonding process may be used to bond the passive surface B of the second wafer 132 to the active surface F of the first wafer 131 through the first dielectric layer 301 . Then, a grinding process, a chemical mechanical polishing process or an etching process (dry etching or wet etching) may be used to remove the wafer carrier 31 shown in FIG. 5d.

In the embodiment of the present application, any dielectric layer, for example, the material of the first dielectric layer 301 is an inorganic material. Therefore, in this application, there is no need to add an organic adhesive layer during the bonding process of any two wafers. Therefore, the probability of organic impurity contamination due to the introduction of organic materials can be reduced during the manufacturing process of the chip stack structure 20 .

In addition, it can be known from the above that in the process of thinning the passive surface of the second wafer 132 and bonding the passive surface B of the second wafer 132 with the active surface F of the first wafer 131 During the process, the wafer carrier 31 can support the second wafer 132, thereby reducing the probability of warping of the second wafer 132 during the process of thinning and stacking with other wafers. Furthermore, the yield of the wafer stack structure 02 and the chip stack structure 20 formed by dicing the wafer stack structure 02 can be improved.

Next, as shown in FIG. 5 f , an etching process, such as a dry etching process, may be used to form a first via hole 511 penetrating through the second wafer 132 . For example, a part of the second wafer 132 is firstly etched to stop on the etch barrier layer on the surface of the first redistribution layer 501, and then the etch barrier layer is etched to expose the first redistribution layer 501. The metal traces in the wafer 132 form holes penetrating through the second wafer 132 . Then an isolation layer is deposited in the via hole to isolate the first via hole 511 from the second wafer 132 . Finally, the isolation layer on the surface of the first redistribution layer 501 is opened, and a metal conductive material is formed in the hole penetrating the second wafer 132 to form a first via hole 511 coupled with the first redistribution layer 501 . Then, a second redistribution layer 502 coupled to the second wafer 132 is formed in the second dielectric layer 302, so that the first end of the first via hole 511 is coupled to the first redistribution layer 501, The second end is coupled to the second redistribution layer 502 . Since the first via hole 511 is formed after the first wafer 131 and the second wafer 132 are bonded, the above-mentioned first via hole 511 adopts the aforementioned post-drilling process.

In addition, a plurality of first dummy pads 401 arranged at intervals may also be fabricated in the second dielectric layer 302 . For example, a plurality of grooves arranged at intervals may be formed on the second dielectric layer 302 by using the photolithography process described above. Then, a conductive material, such as a pure copper material, is formed in the above-mentioned groove by using an electroplating process to form the above-mentioned first dummy pad 401 . At the same time, the first conducting pad 521 connected to the surface of the second redistribution layer 502 away from the second wafer 132 may also be used. In this case, the material constituting the first via pad 521 may be the same as that of the first dummy pad 401 . At this time, the formed first stack assembly 21 is shown in FIG. 5f.

It can be seen from the above that the first redistribution layer 501, the first via hole 511, the second redistribution layer 502 and the first conduction pad 521 can constitute the first interconnection assembly 50, so that through the first wafer 131 Signal transmission can be realized between the first chip 211 obtained by dicing and the second chip 212 obtained by dicing the second wafer 132 through the first interconnection component 50 .

It should be noted that, the process for forming the above-mentioned conductive material in the groove on the second dielectric layer 302 may include chemical vapor deposition (chemical vapor deposition, CVD) process, sputtering deposition process, ion beam deposition process, physical vapor deposition (physical vapor deposition, PVD) process, atomic layer deposition process, molecular beam epitaxy (MBE) evaporation and electrolytic metal plating (electro-plating).

S102 , a method for manufacturing the second stack component 22 . Wherein, the above S102 includes: as shown in FIG. 6 a , forming a fourth dielectric layer 304 on the active surface F of the third wafer 133 , and forming a third redistribution layer 503 in the fourth dielectric layer 304 . Then, as shown in FIG. 6 b , the wafer carrier 31 is bonded to the surface of the fourth dielectric layer 304 away from the third wafer 133 , and the passive surface B of the third wafer 133 is thinned.

As mentioned above, when the third wafer 133 is diced along the dicing line on the third wafer 133 , a plurality of third chips 213 can be obtained.

Next, as shown in FIG. 6 c , a third dielectric layer 303 is formed on the passive surface B of the third wafer 133 . Then a second via hole 512 penetrating through the third wafer 133 is formed by a dry etching process. Furthermore, a second conducting pad 522 coupled to the second via hole 512 is formed in the third dielectric layer 303 . It can be seen from the above that the second via pad 522 and the second via hole 512 constitute the above-mentioned second interconnection component 51 . In addition, a plurality of second dummy pads 402 arranged at intervals are formed in the third dielectric layer 303 . The manufacturing method of the second dummy pad 402 is similar to that of the first dummy pad 401 , and will not be repeated here.

S103 , bonding the first stack component 21 and the second stack component 22 . This S103 may include: setting the third wafer 133 on the side where the active surface F of the second wafer 132 is located, the passive surface B of the third wafer 133 faces the active surface F of the second wafer 132, and The third wafer 133 is bonded to the second wafer 132 by a fusion bonding process, or a hybrid bonding process.

Wherein, bonding the third wafer 133 to the second wafer 132 through a fusion bonding process or a hybrid bonding process refers to at least passing through the third dielectric layer 303 as shown in FIG. 6c and as shown in FIG. 5f The second dielectric layer 302 shown, the third wafer 133 and the second wafer 132 are bonded to achieve the purpose of bonding the first stack assembly 21 and the second stack assembly 22, thereby forming The wafer stack structure 02 shown.

In some embodiments of the present application, when the third wafer 133 is bonded to the second wafer 132 using a fusion bonding process, only the third wafer 133 and the second wafer 132 may be connected by a third The dielectric layer 303 is bonded to the second dielectric layer 302 .

Alternatively, in other embodiments of the present application, multiple first dummy pads 401 are disposed in the second dielectric layer 302 , and multiple second dummy pads 402 are disposed in the third dielectric layer 303 . A position of a first dummy pad 401 may correspond to a position of a second dummy pad 402 . In this way, in the process of bonding the third wafer 133 to the second wafer 132, a hybrid bonding process can be used to not only bond the third dielectric layer 303 to the second dielectric layer 302, but also A first dummy pad 401 may also be bonded to a second dummy pad 402 corresponding to the position of the first dummy pad 401 .

S104 , cutting the wafer stack structure 02 along the cutting line L shown in FIG. 8 , to obtain multiple chip stack structures 20 . A longitudinal cross-sectional view of the wafer stack structure 02 is shown in FIG. 3 .

It should be noted that the dicing line of the wafer stack structure 02 may be the uppermost wafer in the wafer stacking structure 02 , such as the dicing line of the third wafer 133 in FIG. 7 . Also, the positions of the dicing lines of different wafers at the same position can be aligned. Therefore, when cutting the wafer stack structure 02 along the cutting line of the wafer stack structure 02, while cutting the first wafer 131 to obtain a plurality of first chips 211, the second wafer 132 can be cut to obtain a plurality of The second chip 212 can obtain a plurality of third chips 213 after cutting the third wafer 133 .

To sum up, in order to obtain the chip stack structure 20, the manufacturing method of the chip stack structure 20 provided by the embodiment of the present application is to first stack and bond a plurality of wafers, such as the first wafer 131 and the second wafer 132 to form the second wafer 131. A stacking assembly 21, and then the second stacking assembly 22 including the third wafer 133 is bonded to the first stacking assembly 21 to form the above-mentioned wafer stacking structure 02. Next, the wafer stack structure 02 is cut to form a plurality of chip stack structures 20 .

In this way, on the one hand, by cutting the formed wafer stack structure 02 , a chip stack structure 20 in which multiple chips are stacked can be obtained. The chip stack structure 20 can have a higher degree of integration along the longitudinal direction (a direction perpendicular to any one of the chip substrates 100 ). Reducing the size of the chip stack structure 20 in the two-dimensional plane can provide components with higher integration and performance in the limited two-dimensional layout space of the electronic device 01 .

On the other hand, in the process of manufacturing the stacked chip structure provided by the embodiment of the present application, the first wafer 131 and the second wafer 132 can be stacked successively by means of wafer-to-wafer bonding. Next, the first stack assembly 21 composed of the first wafer 131 and the second wafer 132 is bonded together with the third wafer 133 by W2W bonding to form the wafer stack structure 02 . In this case, the wafer stack structure 02 may be cut along the cutting line on the outermost wafer of the wafer stack structure 02 to form a plurality of chip stack structures 20 . Therefore, in the process of manufacturing the chip stack structure 20 , it is only necessary to align wafers to wafers, instead of aligning individual chips, thereby reducing alignment accuracy and improving production efficiency. In addition, compared to the D2D bonding solution and the D2W bonding solution, in the W2W bonding solution provided in the embodiment of the present application, the chip stack structure 20 is obtained by directly bonding the wafers and cutting them, so there is no need for Using KGD, the cut crystal grains are tested one by one, so that the manufacturing process can be simplified and the production cost can be reduced.

On the other hand, during the fabrication process of the chip stack structure 20, two bonding methods, fusion bonding and hybrid bonding, may be used. That is, when the number of stacked layers of wafers is low, for example, when the first wafer 131 and the second wafer 132 are stacked, a low-cost fusion bond can be used between the first wafer 131 and the second wafer 132 combine. Since the number of layers of wafers in the assembly formed by bonding the first wafer 131 and the second wafer 132 is low, fusion bonding can fully ensure that the first wafer 131 and the second wafer 132 are bonded to form the first wafer 131. The reliability of a stacked assembly 21. When the third river source 133 is bonded to the first stack assembly 21, the number of layers of the wafer stack increases. When the third wafer 133 is bonded to the second wafer 132 using a hybrid bonding process, not only an insulating material (ie, the above-mentioned third dielectric layer) can be passed between the third wafer 133 and the second wafer 132 303 and the second dielectric layer 302), and can also be bonded through metal materials (a first dummy pad 401 and a second dummy pad 402), which improves the connection between the third wafer 133 and the second wafer 133. Bond strength between circles 132 . Therefore, the reliability of the wafer stack structure 02 formed after bonding the third wafer 133, the second wafer 132, and the first wafer 132 and the chip stack structure 20 obtained after cutting the wafer stack structure 02 can be improved. . Therefore, during the 3D-IC stacking process, the bonding strength between chips can be guaranteed to meet the requirements, and the production cost can be reduced.

On the other hand, in some embodiments of the present application, as shown in FIG. 9a, after the second dielectric layer 302 is formed on the active surface F of the second wafer 132, the method for manufacturing the above-mentioned first stack assembly 21 can also be It includes a plurality of third conducting pads 523 arranged at intervals in the second dielectric layer 302 . The plurality of third conducting pads 523 are coupled to the second wafer 132 , that is, each third conducting pad 523 in the plurality of third conducting pads 523 is connected to the circuit in the second wafer 132 Structure 101 (shown in FIG. 2b ) is coupled. The material constituting the third conductive pad 523 may be the same as the material constituting the first dummy pad 401 . Based on this, in order to simplify the fabrication process, the fabrication of the third conductive pad 523 can be completed while fabricating the first dummy pad 401 . After the wafer stack structure 02 is cut to form the chip stack structure 20 , the above-mentioned third conducting pad 523 in the chip stack structure 20 is coupled to the circuit structure 101 in the second chip 212 .

In addition, as shown in FIG. 9b, after the third dielectric layer 303 is formed on the passive surface B of the third wafer 133, the method for manufacturing the second stack assembly 22 may further include making intervals in the third dielectric layer 303 a plurality of fourth conductive pads 524 . The plurality of fourth conductive pads 524 are coupled to the third wafer 133 , that is, each fourth conductive pad 524 of the plurality of fourth conductive pads 524 is connected to the third wafer 133 . The circuit structure 101 (as shown in FIG. 2b ) is coupled. After the wafer stack structure 02 is cut to form the chip stack structure 20 , the fourth conducting pad 524 in the chip stack structure 20 is coupled to the circuit structure 101 in the third chip 213 .

It can be seen from the above that the third wafer 133 further includes the substrate 100 for carrying the above-mentioned circuit structure 101 . The surface of the substrate 100 near the third dielectric layer 303 is the passive surface of the third wafer 133 . Since the third dielectric layer 303 is fabricated on the passive surface of the third wafer 133, in order to make the fourth conducting pad 524 in the third dielectric layer 303 compatible with the circuit structure 101 in the third wafer 133 For coupling, a hole may be drilled on the base 100 of the third wafer 133 , so that the fourth conductive pad 524 passes through the hole on the base 100 to couple with the circuit structure 101 in the third wafer 133 . As mentioned above, the fabrication of the fourth conductive pad 524 can be completed while the second dummy pad 402 is being fabricated. In this case, the material of the fourth conductive pad 524 may be the same as that of the second dummy pad 402 .

Based on this, the above-mentioned bonding of the first stack component 21 and the second stack component 22 also includes, as shown in FIG. Therefore, while bonding a first dummy pad 401 to a second dummy pad 402, a third conductive pad 523 and a fourth conductive pad 524 may also be bonded. In this way, the signal transmission between the second wafer 132 and the third wafer 133 can be realized not only through the first interconnection component 50 and the second interconnection component 51, but also through the third conductive pads coupled to each other. 523 and the fourth conducting pad 524 realize signal transmission, so that the signal bandwidth of the chip stack structure 20 formed by dicing the wafer stack structure 02 can be increased.

It should be noted that, in the embodiment of the present application, the bonded conductive pad groups in the chip stack structure 20 formed by dicing the wafer stack structure 02 shown in FIG. The position of the conductive pad group formed by the conductive pads 524 is not limited. Exemplarily, the aforementioned conductive pad group may be located between two adjacent dummy pads (for example, between the first dummy pad 401 in FIG. 9 c ). Or, in other embodiments of the present application, for a single chip stack structure 20, relative to the dummy pads (such as the first dummy pad 401), the above-mentioned group of bonded conductive pads (such as the phase bond Combined third conductive pad 523 and fourth conductive pad 524) may be disposed on the periphery of the chip stack structure 20.

Of course, the above is to form stacked components, such as the above-mentioned first stacked component 21 and second stacked component 22 , by adopting a fusion bonding process of a plurality of wafers. Then, a hybrid bonding process is used to bond a plurality of stacked components, for example, the first stacked component 21 and the second stacked component 22 are described as an example. In some other embodiments of the present application, a plurality of wafers may also be formed into a stack assembly, such as the above-mentioned first stack assembly 21 and second stack assembly 22 , using a fusion bonding process. Then continue to use the fusion bonding process to bond multiple stack components, for example, the first stack component 21 and the second stack component 22 . In this case, as shown in FIG. 10 , only the second dielectric layer 302 and the third The dielectric layer 303 is bonded. Therefore, the manufacturing process of the wafer stack structure 02 can be simplified.

In addition, it can be known from the above that during the fabrication process of the above-mentioned wafer stack structure 02, any two adjacent wafers are in such a way that the passive surface B of one wafer is close to the front surface F of the other wafer, that is, passive Face to face (back to face, B2F) stacked together. For example, in FIG. 9 c , the passive surface B of the second wafer 132 is close to the front surface F of the first wafer 131 . The passive surface B of the third wafer 133 is close to the front surface F of the second wafer 132 . In this way, the orientations of each wafer are the same, so the via holes (for example, the first via hole 511 and the second via hole 511 and the second via hole in FIG. The location of the hole 512) can be the same. Therefore, it is possible to use the same set of masks to make multiple via holes for phase coupling at the same position on different wafers, avoiding the problem of face-to-face (F2F) The mirror effect (mirror effect), which leads to the problem of increasing the number of masks.

The above description is based on the wafer stacking structure 02, the first stacking assembly 21 includes two wafers, such as the first wafer 131 and the second wafer 132, and the second stacking assembly 22 includes the third wafer 133 as an example. . In other embodiments of the present application, as shown in FIG. 11 , the second stack assembly 22 may further include a fourth wafer 134 . In this case, the manufacturing method of the first stacking component 21 in the manufacturing method of the above-mentioned wafer stack structure 02 is the same as that described above. The difference is that the manufacturing method (ie S102) of the second stacking assembly 22 includes:

Firstly, the fourth wafer 134 as shown in FIG. 12 a is cleaned, and the fifth dielectric layer 305 is formed on the side of the active surface F of the fourth wafer 134 . Then, the wafer carrier 31 is bonded to the surface of the fifth dielectric layer 305 away from the fourth wafer 134 .

Next, the passive surface B of the fourth wafer 134 is thinned, and the thinning process is the same as that described above, and will not be repeated here. In addition, as shown in FIG. 12b, a fusion bonding process may be used to bond the passive surface B of the fourth wafer 134 to the active surface F of the third wafer 133 through the fourth dielectric layer 304, and remove Wafer carrier 31 .

It should be noted that, before bonding the third wafer 133 and the fourth wafer 134 , a third redistribution layer 503 coupled with the third wafer 133 may be formed in the fourth dielectric layer 304 . The manufacturing method of the third redistribution layer 503 is the same as that described above, and will not be repeated here.

Next, as shown in FIG. 12b, a third via hole 513 is formed through the fourth wafer 134, and is disposed in the fifth dielectric layer 305, and is connected with the circuit structure 101 in the fourth wafer 134 (as shown in FIG. 2b) coupled with the fourth redistribution layer 504. A first end of the third via hole 513 is coupled to the third redistribution layer 503 , and a second end is coupled to the fourth redistribution layer 504 . In this way, the third redistribution layer 503, the third via hole 513, and the fourth redistribution layer 504 can constitute the third interconnection component 52, so that the connection between the third wafer 133 and the fourth wafer 134 can be realized. Signal transmission.

Next, as shown in FIG. 12 c , the wafer carrier 31 is bonded to the surface of the fifth dielectric layer 305 away from the fourth wafer 134 , and the passive surface B of the third wafer 133 is thinned.

Next, as shown in FIG. 12 d , a third dielectric layer 303 is formed on the passive surface B of the third wafer 133 . Then a second via hole 512 is formed through the third wafer 133 , and a second via pad 522 and a second dummy pad 402 are formed in the third dielectric layer 303 . The second via pad 522 is coupled to the first end of the second via hole 512 and the second redistribution layer 502 . It can be seen from the above that the second via hole 512 and the second via pad 522 constitute the above-mentioned second interconnection component 51 . In this case, the fabrication of the second stack assembly 22 can be completed.

Based on this, the above S103 is performed again, the first stacking assembly 21 and the second stacking assembly 22 are bonded, and the above-mentioned wafer carrier 31 is removed, and the structure of the formed wafer stacking structure 02 is shown in FIG. 11 . Next, after cutting the wafer stack structure 02 as shown in FIG. 11 , a plurality of chip stack assemblies 20 as shown in FIG. 13 can be obtained.

The fourth chip 214 in the chip stack assembly 20 is obtained by cutting the fourth wafer 134 in the wafer stack structure 02 shown in FIG. 11 . Therefore, the fourth chip 214 is disposed on a side of the third chip 213 away from the second chip 212 , and the passive surface B of the fourth chip 214 faces the third chip 213 . The third chip 213 and the fourth chip are bonded through the fourth dielectric layer 304 . In addition, a fifth dielectric layer 305 is disposed on the side of the active surface F of the fourth chip 214 .

In this way, when the number of wafers increases during the process of manufacturing the chip stack structure 20, the first wafer 131 and the second wafer 132 can be bonded together by using a fusion bonding process with a lower cost as described above. Bonded through the first dielectric layer 301 . Moreover, the third wafer 133 and the fourth wafer 134 are bonded through the fourth dielectric layer 304 by using a fusion bonding process. Then, the first stack assembly 21 formed by bonding the first wafer 131 and the second wafer 132, and the second stack assembly 22 formed by bonding the third wafer 133 and the fourth wafer 134 adopt the bonding strength Higher hybrid bonding process phase bonding. In this case, when the number of stacked wafers is small, the bonding process between the wafers can use a less costly fusion bonding process. When the number of stacked wafers is large, hybrid bonding with higher bonding strength is used between the wafers, so that the reliability of the wafer stacking structure can be improved while reducing manufacturing costs. In addition, when the number of stacked wafers in the wafer stacking structure increases, a part of the wafers can be grouped and bonded by the fusion bonding process to form a stacked assembly under the premise that the reliability of the fusion bonding process can be guaranteed. Then, a hybrid bonding process with higher bonding strength is used to perform two-by-two bonding on multiple stacked components (for example, the above-mentioned first stacked component 21 and the second stacked component 22 are bonded together). In this case, compared to the scheme of stacking wafers layer by layer, in the embodiment of the present application, when the wafers in one of the stacking components have a stacking error or a deviation in alignment accuracy during the stacking process, it can be Replacing the stacked assembly alone will not lead to failure of the entire wafer stacked structure 02 and the chip stacked structure 20 formed after cutting the wafer stacked structure 02 .

In the embodiment of the present application, for any chip stacking structure 20 described above, in the chip stacking structure 20, the chip in the second stacking component 22 that is farthest from the first stacking component 21 can be called the bottom chip, as shown in FIG. The fourth chip 214 in 13 may be referred to as a bottom chip. The underlying chip can be coupled with the external component 10 (as shown in FIG. 1 ), so that the chip stack structure 20 can realize signal transmission with other chips or chip stack structures on the PCB through the external component 10 .

In this case, in order to enable the bottom chip (for example, the fourth chip 214) to be coupled with the above-mentioned external component 10, as shown in FIG. . The interface pad 600 may be disposed in a dielectric layer (eg, the fifth dielectric layer 305 ) on the active side of the bottom chip (eg, the fourth chip 214 ). In this way, each chip in the chip stack structure 20 can be coupled to the external component 10 through the interface pad 600 and the fourth redistribution layer 504 .

In some embodiments of the present application, the above-mentioned bottom chip may be a logic chip, and at least one chip (for example, the first chip 211, the second chip 212 and the third chip 213) may be memory chips. For example, dynamic random access memory (DRAM). In this case, the chip stack structure 20 may be a high bandwidth memory (HBM).

Alternatively, in some other embodiments of the present application, the above-mentioned bottom chip may be a memory chip, and at least one chip other than the bottom chip (for example, the fourth chip 214 ) in the chip stack structure 20 is a logic chip.

To sum up, in the process of manufacturing the chip stack structure 20 shown in FIG. 14 , the first wafer 131 and the second wafer 132 in the first stack assembly 21 are bonded together by fusion. The third wafer 133 and the fourth wafer 134 in the second stacking assembly 22 are fusion bonded together, and then the first stacking assembly 21 and the second stacking assembly 22 are hybrid bonded to form the wafer stacking structure 02 . Finally, the wafer stack structure 02 is cut to form the chip stack structure 20 . In this case, the first stack assembly 21 in the chip stack structure 20 includes two chips, namely a first chip 211 and a second chip 212 . The second stack assembly 22 includes two chips, namely a third chip 213 and a fourth chip 214 .

In other embodiments of the present application, in the process of manufacturing the chip stack structure 20 , four wafers may be firstly bonded together by fusion to form the first stack assembly 21 . And the other four wafers are bonded together by fusion to form the second stack assembly 22 . Then, the first stack assembly 21 and the second stack assembly 22 are bonded by a hybrid bonding process to form a round stack structure 02 with eight wafers. Finally, the wafer stack structure 02 is cut to form the chip stack structure 20 . In this case, the first stack assembly 21 in the chip stack structure 20 includes four chips. The second stack assembly 22 includes four chips.

Alternatively, in other embodiments of the present application, in the process of manufacturing the chip stack structure 20 , eight wafers may be firstly bonded together by fusion to form the first stack assembly 21 . And the other eight wafers are bonded together by fusion to form the second stack assembly 22 . Then, the first stack assembly 21 and the second stack assembly 22 are bonded by a hybrid bonding process to form a round stack structure 02 having sixteen wafers. Finally, the wafer stack structure 02 is cut to form the chip stack structure 20 . In this case, the first stack assembly 21 in the chip stack structure 20 includes eight chips. The second stack assembly 22 includes eight chips.

It should be noted that the above description is based on an example in which the number of wafers or chips in the first stacking assembly 21 and the second stacking assembly 22 are the same. In other embodiments of the present application, as shown in FIG. 15 , the first stack assembly 21 includes a first chip 211 and a second chip 212, and the second stack assembly 22 may include a third chip 213, a fourth chip 214, and a second chip 214. Five chips 215 (the active surface side of the fifth chip 215 is provided with a sixth dielectric layer 306 ). In this case, the number of chips in the first stack assembly 21 and the second stack assembly 22 may be different. The present application does not limit the number of chips in the above-mentioned stacked assembly.

In addition, the above descriptions are based on the example that the wafer stack structure 02 includes two stacking components, such as the first stacking component 21 and the second stacking component 22 . In this application, the number of stacked components in the wafer stacked structure 02 is not limited, as long as the wafer stacked structure 02 only needs to have two stacked components. The bonding method between wafers in any one stacked assembly and the bonding method of any two stacked assemblies are the same as those described above and will not be repeated here.

Example two

In the chip stack structure 20 in this example, as mentioned above, the first stack component 21 may include a first chip 211 and a second chip 212 as mentioned above. The second stack assembly 22 may include a third chip 213 and a fourth chip 214 . The difference from Example 1 is that, in this example, the via holes penetrating through the third chip 213 are made on the third wafer 133 (obtaining the third chip 213 after dicing) using a mid-section drilling process, that is, the via holes The via holes are made before the bonding of the third wafer 133 and the fourth wafer (the fourth chip 214 is obtained after dicing).

In this case, the manufacturing method of the first stacking component 21 in the manufacturing method of the above-mentioned wafer stack structure 02 is the same as that described above. The difference is that the manufacturing method (ie S102) of the second stacking assembly 22 includes:

First, as shown in FIG. 16 a , a fourth dielectric layer 304 is formed on the active surface F of the third wafer 133 . A second via hole 512 is formed in the third wafer 133 , and a third redistribution layer 503 is formed in the fourth dielectric layer 304 . The third redistribution layer 503 is coupled to the second end of the second via hole 512 (an end of the second via hole 512 close to the third redistribution layer 503 ), and the third wafer 133 .

Next, as shown in FIG. 12 a , a fifth dielectric layer 305 is formed on the active surface F of the fourth wafer 134 . Then, the wafer carrier 31 is bonded to the surface of the fifth dielectric layer 305 away from the fourth wafer 134 .

Next, the passive surface B of the fourth wafer 134 is thinned, and as shown in FIG. The source face F is bonded. Then the wafer carrier 31 is removed.

Next, as shown in FIG. 16c, a third via hole 513 penetrating through the fourth wafer 134, and a fourth redistribution disposed in the fifth dielectric layer 305 and coupled to the fourth wafer 134 are formed. Layer 504. A first end of the third via hole 513 is coupled to the third redistribution layer 503 , and a second end is coupled to the fourth redistribution layer 504 . The third redistribution layer 503 , the third via hole 513 and the fourth redistribution layer 504 constitute the third interconnection component 52 . In this case, the fourth wafer 134 can realize signal transmission with the third wafer 133 through the third interconnection component 52 .

Next, as shown in FIG. 16d, the wafer carrier 31 is bonded to the surface of the fifth dielectric layer 305 away from the fourth wafer 134, and the passive surface B of the third wafer 133 is thinned to The first end of the second via hole 512 (the end of the second via hole 512 away from the third redistribution layer 503 ) is exposed.

Next, as shown in FIG. 12d, a third dielectric layer 303 is formed on the passive surface B of the third wafer 133, and a second conductive pad 522 and a second dummy solder pad are formed in the third dielectric layer 303. MAT 402. The second via pad 522 is coupled to the first end of the second via hole 512 and the second redistribution layer 502 . In this case, the fabrication of the second stack assembly 22 can be completed.

Based on this, after performing the above S103, the first stacking assembly 21 and the second stacking assembly 22 are bonded, and the above-mentioned wafer carrier 31 is removed, and the structure of the formed wafer stacking structure 02 is shown in FIG. 11 . Next, after cutting the wafer stack structure 02 as shown in FIG. 11 , a plurality of chip stack assemblies 20 as shown in FIG. 13 can be obtained.

In summary, the second via hole 512 penetrating the third wafer 133 in FIG. 16d, as shown in FIG. 16a and FIG. 16b, is formed before the third wafer 133 and the fourth wafer 134 are stacked and bonded. , the second via hole 512 is prepared by a mid-section drilling process. As for the solution shown in FIG. 12d in Example 1, the second via hole 512 is formed after the third wafer 133 and the fourth wafer 134 are stacked (post-drilling process), the post-drilling process needs to be A part of the third wafer 133 is etched to stop on the etch barrier layer of the third rewiring layer 503, and then the etch barrier layer is etched to expose the metal traces in the third rewiring layer 503. lines, thereby forming holes penetrating the third wafer 133 . Then an isolation layer is deposited in the via hole to isolate the second via hole 512 from the third wafer 133 . Finally, the isolation layer on the surface of the third redistribution layer 503 is opened, and metal conductive material is formed in the hole penetrating the third wafer 133 to form the second via hole 512 coupled with the third redistribution layer 503 . Therefore, the preparation of the second via hole 512 by using the mid-section drilling process does not need to consider steps such as forming an etch barrier layer and sequentially etching the third wafer and the etch barrier layer step by step, which is beneficial to reduce the difficulty of the process.

However, in Example 2, when the second via hole 512 adopts the mid-section drilling process, the second via hole 512 is formed before the bonding of the third wafer 133 and the fourth wafer 134 as shown in FIG. 16 a , and as shown in FIG. As shown in 16d, the second via hole 512 can be exposed during the process of grinding the back of the third wafer 133 . Next, when making the third dielectric layer 303 on the passive surface of the third wafer 133, and the second conducting pad 522 (as shown in FIG. 11 ) located in the second dielectric layer 302, the The second via pad 522 may be coupled to the exposed first end of the second via hole 512 . Therefore, the mid-section drilling process has lower requirements on the manufacturing process precision of the second via hole 512 , which is beneficial to simplify the manufacturing process.

In this example, the number of stacked components in the wafer stack structure 02, the bonding method of two adjacent stacked components, the number of wafers in each stacked component, and the bonding method of two adjacent wafers are the same as above, I won't repeat them here.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A chip stack structure, characterized in that it comprises:

first chip;

The second chip is arranged on the side where the active surface of the first chip is located, and the passive surface of the second chip faces the active surface of the first chip; the first chip and the first chip The two chips are bonded by fusion bonding process;

The third chip is arranged on the side where the active surface of the second chip is located; the passive surface of the third chip faces the active surface of the second chip; the third chip and the second chip Chips are bonded using a hybrid bonding process.
The chip stack structure according to claim 1, wherein the chip stack structure further comprises:

a first dielectric layer disposed between the first chip and the second chip; the first chip and the second chip are bonded through the first dielectric layer;

a second dielectric layer disposed on the active surface side of the second chip;

a plurality of first dummy pads arranged at intervals; the plurality of first dummy pads are arranged in the second dielectric layer;

a third dielectric layer disposed on the passive surface of the third chip and bonded to the second dielectric layer;

A plurality of second dummy pads arranged at intervals; the plurality of second dummy pads are disposed in the third dielectric layer; one second dummy pad in the plurality of second dummy pads is connected to the second dummy pad one of the first dummy pads among the plurality of first dummy pads.
The chip stack structure according to claim 2, wherein the chip stack structure further comprises a first interconnection component; the first interconnection component comprises:

a first redistribution layer disposed in the first dielectric layer and coupled to the first chip;

a second redistribution layer disposed in the second dielectric layer and coupled to the second chip;

The first via hole runs through the second chip; the first end of the first via hole is coupled to the first redistribution layer, and the second end of the first via hole is coupled to the first via hole. The second redistribution layer is coupled.
The chip stack structure according to claim 3, characterized in that,

The first interconnection component further includes a first conductive pad, disposed on a surface of the second redistribution layer away from the first redistribution layer, and coupled to the second redistribution layer ;

The chip stack structure also includes a second interconnection assembly; the second interconnection assembly includes:

a second conducting pad, disposed in the third dielectric layer, and bonded to the first conducting pad;

The second via hole runs through the third chip; the first end of the second via hole is coupled to the second via pad, and the second end of the second via hole is coupled to the second via hole. The third chip is coupled.
The chip stack structure according to claim 3 or 4, wherein the chip stack structure further comprises:

A fourth chip; the fourth chip is disposed on a side of the third chip away from the second chip, and the passive surface of the fourth chip faces the active surface of the third chip;

A fourth dielectric layer; disposed between the third chip and the fourth chip; the third chip and the fourth chip are bonded through the fourth dielectric layer.
The chip stack structure according to claim 5, characterized in that, the chip stack structure further comprises a fifth dielectric layer and a third interconnection component; the fifth dielectric layer is disposed on the active part of the fourth chip source surface;

The third interconnection assembly includes:

The third redistribution layer is arranged in the fourth dielectric layer and coupled with the third chip and the first interconnection component;

a fourth rewiring layer disposed in the fifth dielectric layer and coupled to the fourth chip;

The third via hole runs through the fourth chip; the first end of the third via hole is coupled to the third redistribution layer, and the second end of the third via hole is coupled to the third via hole. The fourth redistribution layer is coupled.
The chip stack structure according to any one of claims 2-6, wherein the chip stack structure further comprises:

A plurality of third conducting pads arranged at intervals; the plurality of third conducting pads are disposed in the second dielectric layer and coupled with the second chip;

A plurality of fourth conducting pads arranged at intervals; the plurality of fourth conducting pads are disposed in the third dielectric layer and coupled to the third chip;

Wherein, one third conductive pad of the plurality of third conductive pads is bonded to one fourth conductive pad of the plurality of fourth conductive pads.
The chip stack structure according to any one of claims 1-7, characterized in that the chip in the chip stack structure that is farthest from the first chip is the bottom chip;

The chip stack structure also includes:

A plurality of interface welding pads arranged at intervals; the plurality of interface welding pads are arranged in the dielectric layer on one side of the active surface of the bottom chip; the plurality of interface welding pads are used to connect the bottom chip to the external components are coupled.
The chip stack structure according to claim 8, wherein the bottom chip is a logic chip, and at least one chip other than the bottom chip in the chip stack structure is a memory chip.
A wafer stack structure, characterized in that, comprising:

first wafer;

The second wafer; the second wafer is arranged on the side where the active surface of the first wafer is located, and the passive surface of the second wafer faces the active surface of the first wafer ; The first wafer is bonded to the second wafer by a fusion bonding process;

The third wafer is arranged on the side of the second wafer away from the first wafer; the passive surface of the third wafer faces the active surface of the second wafer; the third wafer The wafer is bonded to the second wafer by a hybrid bonding process.
An electronic device, characterized by comprising an external component and at least one chip stack structure according to any one of claims 1-9 coupled to the external component.
The electronic device according to claim 11, wherein the external component comprises a package substrate, an interposer, or at least one fan-out redistribution layer.
A method for manufacturing a chip stack structure, characterized in that the method comprises:

A second wafer is arranged on the side where the active surface of the first wafer is located, the passive surface of the second wafer faces the active surface of the first wafer, and the bonding the first wafer to the second wafer;

A third wafer is arranged on the side where the active surface of the second wafer is located, the passive surface of the third wafer faces the active surface of the second wafer, and through a fusion bonding process, Alternatively, a hybrid bonding process bonds the third wafer to the second wafer.
The method for manufacturing a chip stack structure according to claim 13, wherein the second wafer is arranged on the side where the active surface of the first wafer is located, and the The method for bonding the first wafer to the second wafer includes:

forming a first dielectric layer on the active surface of the first wafer;

Forming a second dielectric layer on the active surface of the second wafer, bonding the wafer carrier to the surface of the second dielectric layer away from the second wafer; for the second wafer Thinning of the passive surface;

bonding the passive surface of the second wafer to the active surface of the first wafer through the first dielectric layer, and removing the wafer carrier;

The third wafer is arranged on the side where the active surface of the second wafer is located, and the third wafer is bonded to the second wafer through a fusion bonding process or a hybrid bonding process Methods of bonding include:

forming a third dielectric layer on the passive surface of the third wafer;

The third wafer is bonded to the second wafer through at least the third dielectric layer and the second dielectric layer.
The method for manufacturing a stacked chip structure according to claim 14, characterized in that, after bonding the third wafer to the second wafer, the method further comprises: aligning the first wafer along the dicing line Wafer, the second wafer and the third wafer are diced.
The method for manufacturing a chip stack structure according to claim 14 or 15, characterized in that,

After the second dielectric layer is formed on the active surface of the second wafer, the method for manufacturing the chip stack structure further includes: forming a plurality of first dummy layers arranged at intervals in the second dielectric layer welding pad;

After the third dielectric layer is formed on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: forming a plurality of second dummy layers arranged at intervals in the third dielectric layer welding pad;

Bonding the third wafer to the second wafer through at least the third dielectric layer and the second dielectric layer includes: bonding the third dielectric layer to the second dielectric layer The electrical layers are bonded, and a first dummy pad among the plurality of first dummy pads is bonded to a second dummy pad among the plurality of second dummy pads.
The method for manufacturing a chip stack structure according to claim 16, characterized in that,

After the second dielectric layer is formed on the active surface of the second wafer, the method for manufacturing the chip stack structure further includes: forming a plurality of third conductors arranged at intervals in the second dielectric layer through welding pads; the plurality of third conducting welding pads are coupled to the second wafer;

After the third dielectric layer is formed on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: forming a plurality of fourth conductors arranged at intervals in the third dielectric layer through pads; the plurality of fourth through pads are coupled to the third wafer;

Bonding the third wafer to the second wafer through at least the third dielectric layer and the second dielectric layer further includes: connecting the plurality of third conductive pads to a first The three conducting pads are bonded to one fourth conducting pad of the plurality of fourth conducting pads.
The method for manufacturing a chip stack structure according to any one of claims 14-17, characterized in that, after the first dielectric layer is formed on the active surface of the first wafer, through the first dielectric layer Before bonding the passive surface of the second wafer to the active surface of the first wafer, the method for manufacturing the chip stack structure further includes: forming a a first redistribution layer coupled to the wafer;

After the passive surface of the second wafer is bonded to the active surface of the first wafer through the first dielectric layer, at least through the third dielectric layer and the second dielectric layer, Before bonding the third wafer and the second wafer, the method for manufacturing the chip stack structure further includes:

forming a first via hole penetrating through the second wafer, and a second redistribution layer disposed in the second dielectric layer and coupled to the second wafer; the first via A first end of the via hole is coupled to the first redistribution layer, and a second end is coupled to the second redistribution layer.
The method for manufacturing a chip stack structure according to claim 18, characterized in that,

Before forming the third dielectric layer on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes:

forming a fourth dielectric layer on the active surface of the third wafer; forming a second via hole in the third wafer, and forming a third redistribution layer in the fourth dielectric layer; The third redistribution layer is coupled to the second end of the second via hole and the third wafer;

A fifth dielectric layer is formed on the active surface of the fourth wafer, and the wafer carrier is bonded to the surface of the fifth dielectric layer away from the fourth wafer; for the passive surface of the fourth wafer carry out thinning;

bonding the passive surface of the fourth wafer to the active surface of the third wafer through the fourth dielectric layer, and removing the wafer carrier;

forming a third via hole penetrating through the fourth wafer, and a fourth redistribution layer disposed in the fifth dielectric layer and coupled to the fourth wafer; the third via The first end of the via hole is coupled to the third redistribution layer, and the second end is coupled to the fourth redistribution layer;

Bonding the wafer carrier to the surface of the fifth dielectric layer away from the fourth wafer; thinning the passive surface of the third wafer to expose the first of the second via hole end;

After forming the third dielectric layer on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: manufacturing a second conductive pad in the third dielectric layer; The second via pad is coupled to the first end of the second via hole and the second redistribution layer.
The method for manufacturing a chip stack structure according to claim 18, characterized in that,

Before forming the third dielectric layer on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes:

forming a fourth dielectric layer on the active surface of the third wafer, and forming a third redistribution layer in the fourth dielectric layer;

A fifth dielectric layer is formed on the active surface of the fourth wafer, and the wafer carrier is bonded to the surface of the fifth dielectric layer away from the fourth wafer; for the passive surface of the fourth wafer carry out thinning;

bonding the passive surface of the fourth wafer to the active surface of the third wafer through the fourth dielectric layer, and removing the wafer carrier;

forming a third via hole penetrating through the fourth wafer, and a fourth redistribution layer disposed in the fifth dielectric layer and coupled to the fourth wafer; the third via The first end of the via hole is coupled to the third redistribution layer, and the second end is coupled to the fourth redistribution layer;

Bonding the wafer carrier to the surface of the fifth dielectric layer away from the fourth wafer; thinning the passive surface of the third wafer;

After the third dielectric layer is formed on the passive surface of the third wafer, the method for manufacturing the chip stack structure further includes: forming a second via hole penetrating through the third wafer, and forming a second via hole on the third wafer. forming a second conducting pad in the third dielectric layer; the second conducting pad is coupled to the first end of the second via hole and the second redistribution layer.