CN117459062A - Device and method for performing Beidou ultra-stable low-phase-noise crystal oscillator taming on rubidium atomic clock - Google Patents

Abstract

The invention discloses a device and a method for the frequency-dependent training of a rubidium atomic clock by Beidou ultra-stable low-phase noise crystal oscillator. The invention uses the fixed frequency signal provided by the satellite time service receiver to compare with the oscillation signal generated by the local rubidium clock module to obtain the frequency difference, and then the oscillation frequency is basically consistent with the oscillation frequency of the satellite through the adjustment of the local rubidium clock module, and the phase of the rubidium clock module is compensated in the process of frequency adjustment, so that the Beidou disciplinary rubidium atomic clock reaches or approaches to the level of the primary frequency standard.

Description

Device and method for performing Beidou ultra-stable low-phase-noise crystal oscillator taming on rubidium atomic clock

Technical Field

The invention relates to the technical field of time frequency taming, in particular to a device and a method for taming a rubidium atomic clock by Beidou ultra-stable low-phase noise crystal oscillator.

Background

The frequency standard commonly used at present is a primary frequency standard (including a hydrogen atom frequency standard, a cesium atom frequency standard and the like) and a secondary frequency standard (rubidium atom frequency standard). In various high-precision frequency standards, the primary frequency standard such as a hydrogen clock, a Cesium clock and the like has good long-term stability and short-term stability, but has large volume, high price and very limited application range, and has very high requirements on the use environment; rubidium clock is widely used in various fields of communication, metering, application of electronic technology, electronic instruments, aerospace, radar, national defense and military industry and the like due to low price and small volume, but the frequency stability of the rubidium clock needs to be improved.

Disclosure of Invention

The technical purpose is that: aiming at the technical problems, the invention provides a device and a method for the ultra-stable low-phase-noise crystal oscillator to tame a rubidium atomic clock, which adopt 1pps signals of a Beidou system and the stable low-phase-noise crystal oscillator to tame rubidium atomic frequency standards, can improve the short stability and the phase noise of the rubidium atomic frequency standards, enable output signals to have excellent short stability and relative frequency deviation, overcome the drift of rubidium atoms and reach or approach to the level of a first-level frequency standard.

The technical scheme is as follows: in order to achieve the technical purpose, the invention adopts the following technical scheme:

the utility model provides a device of super steady low phase noise crystal oscillator tame rubidium atomic clock of big dipper which characterized in that includes: the system comprises a Beidou receiver, a Kalman filter, a phase discriminator, a digital loop filter, an A/D (analog to digital) sampler, a central processing unit, a high-precision anti-seismic rubidium clock, a crystal oscillator, a phase-locked loop module, a frequency synthesizer, an isolation distribution amplifier, a frequency divider and a time isolation module;

the output end of the Beidou receiver is connected with a Kalman filter and is used for receiving the Beidou second pulse signals remotely transmitted by the Beidou system and carrying out filtering treatment;

the high-precision anti-vibration rubidium clock is used for generating a rubidium clock oscillation signal, the crystal oscillator is used for generating a clock signal, the phase-locked loop module is used for receiving the rubidium clock oscillation signal and the clock signal, the phase-locked loop module, the frequency synthesizer, the isolation distribution amplifier and the frequency divider are sequentially connected, the frequency divider is used for outputting two paths of rubidium clock frequency division second pulse signals, one path of rubidium clock frequency division second pulse signal is input into the central processing module after passing through the isolation distribution amplifier, and the other path of rubidium clock frequency division second pulse signal is input into the phase discriminator;

the phase discriminator is used for receiving the filtered Beidou second pulse signal and one path of rubidium clock frequency division second pulse signal simultaneously and carrying out phase discrimination processing, and the output end of the phase discriminator is sequentially connected with the digital loop filter and the A/D sampler and is used for carrying out frequency adjustment and phase error control on the output signal to obtain a measurement signal and inputting the measurement signal into the central processing module;

the central processing module is used for calculating an offset correction value according to the measurement signal and the rubidium clock frequency division second pulse signal and inputting the offset correction value into the frequency synthesizer;

the isolation distribution amplifier is used for outputting a plurality of rubidium clock signals.

Preferably, the phase-locked loop module comprises a filter, a digital phase discriminator, a digital filter, a first amplifier, a D/A converter and a second amplifier, wherein an output signal of the rubidium clock module and a clock signal output by the crystal oscillator are input into the digital phase discriminator for phase discrimination, then a high-frequency alternating current component is filtered by the digital filter, and after the output signal of the digital filter is amplified, digital-to-analog converted and amplified in sequence, a feedback control signal is obtained, and the feedback signal is input into the crystal oscillator module for controlling the voltage-controlled constant-temperature crystal oscillator frequency of the crystal oscillator to realize frequency synchronization.

Preferably, the digital phase discriminator adopts a structure of an all-digital purification phase-locked loop, and comprises an exclusive-OR gate phase discriminator, a K-mode reversible counter, a pulse addition and subtraction circuit and a divide-by-N reader which are sequentially connected, wherein the exclusive-OR gate phase discriminator is used for receiving an input signal and a feedback signal, and the divide-by-N reader is used for sending two paths of output signals, and one path of output signal is used as a feedback signal to be sent to the input end of the exclusive-OR gate phase discriminator.

The method for the Beidou ultra-stable low-phase-noise crystal oscillator tame rubidium atomic clock is applied to the device and is characterized by comprising the following steps of:

a rubidium clock oscillation signal is generated through a high-precision anti-vibration rubidium clock, and a clock signal is generated through a crystal oscillator;

the rubidium clock oscillation signal and the clock signal are sequentially sent to a phase-locked loop module, a frequency synthesizer, an isolation distribution amplifier and a frequency divider for processing, the output end of the frequency divider outputs two paths of rubidium clock frequency division second pulse signals, one path of rubidium clock frequency division second pulse signals is input to a central processing module through a time interval measuring module, and the other path of rubidium clock frequency division second pulse signals are input to a phase discriminator; isolation distribution amplifier outputs multiple rubidium clock signals

Receiving a Beidou second pulse signal remotely transmitted by a Beidou system through a Beidou receiver and performing filtering processing;

the phase discriminator receives the filtered Beidou second pulse signal and one path of rubidium clock frequency division second pulse signal simultaneously and carries out phase discrimination processing, and an output signal of the phase discriminator is sequentially filtered and sampled to obtain a measuring signal comprising phase difference information;

and the central processing module calculates a deviation correction value according to the measurement signal, and the deviation correction value is sent to the frequency synthesizer.

Preferably, the method comprises the following process of the Beidou tamarind rubidium clock:

frequency calibration stage: in the stage, the output end of the frequency divider outputs two paths of rubidium clock frequency-dividing second pulse signals to start tracking the filtered Beidou second pulse signals, frequency calibration is carried out, phase differences are gradually eliminated, and the phase differences between the calibrated rubidium clock frequency-dividing second pulse signals and the Beidou second pulse signals are within a preset range;

parameter adjustment stage: after the frequency calibration stage is completed, the control voltage value of the high-precision anti-vibration rubidium clock is kept stable, and the proportional coefficient and the integral coefficient are gradually changed, wherein the proportional coefficient and the integral coefficient are control parameters when PI feedback control is adopted by the device;

frequency locking phase: the central processing module generates an adjusting value according to the frequency control characteristic of the rubidium frequency standard, and the adjusting value is used for adjusting the output signal of the local frequency source.

The beneficial effects are that: due to the adoption of the technical scheme, the invention has the following beneficial effects:

the invention locks the rubidium atomic clock by utilizing the signal remotely transmitted by the Beidou system, can output high-precision frequency signals, can effectively reproduce the relative frequency deviation of the received standard time frequency signals on the rubidium frequency standard, can keep higher relative frequency deviation through the discipline technology in a long time, and meanwhile, the short-term stability and the phase noise of the rubidium frequency standard are improved through the phase-locked high-stability crystal oscillator, so that the Beidou discipline rubidium atomic clock reaches or approaches to the level of the primary frequency standard.

Drawings

FIG. 1 is a block diagram of a device for the Beidou ultra-stable low-phase noise crystal oscillator tame rubidium atomic clock;

FIG. 2 is a schematic diagram of a period difference measurement;

FIG. 3 is a schematic diagram of a measurement of quantization delay;

FIG. 4 is a schematic diagram of a clock taming system;

FIG. 5 is a block diagram of the clock taming system of FIG. 4 simplified to a control system;

FIG. 6 is a schematic diagram of parameter adjustment at each stage in the BDS tamed rubidium clock process of the present invention;

FIG. 7 is a schematic diagram of a phase lock module;

fig. 8 is a schematic diagram of the operation of the clean phase locked loop of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The invention provides a device and a method for the ultra-stable low-phase-noise crystal oscillator taming of a rubidium atomic clock of Beidou, which are a system for realizing timing and correcting a rubidium clock module by receiving navigation satellite signals. The basic principle of clock taming is that a fixed frequency signal provided by a satellite time service receiver is used for comparing with an oscillation signal generated by a local rubidium clock module to obtain a frequency difference; and the oscillation frequency is basically consistent with the oscillation frequency of the satellite through the adjustment of the local rubidium clock module. In the process of frequency regulation, the phase of the rubidium clock module is also required to be compensated, so that the difference value between the frequency division second pulse output by the rubidium clock module and the second pulse output by the receiver is within a certain range.

Example 1

As shown in fig. 1, the apparatus includes: the system comprises a Beidou receiver, a Kalman filter, a phase discriminator, a digital loop filter, an A/D (analog/digital) sampler, a central processing unit, a high-precision anti-seismic rubidium clock, a crystal oscillator, a phase-locked loop module, a frequency synthesizer, an isolation distribution amplifier, a frequency divider and a time isolation module, wherein the output end of the Beidou receiver is connected with the Kalman filter and is used for receiving Beidou second pulse signals remotely transmitted by a Beidou system and carrying out filtering treatment; the high-precision anti-vibration rubidium clock is used for generating a rubidium clock oscillation signal, the crystal oscillator is used for generating a clock signal, the phase-locked loop module is used for receiving the rubidium clock oscillation signal and the clock signal, the phase-locked loop module, the frequency synthesizer, the isolation distribution amplifier and the frequency divider are sequentially connected, the frequency divider is used for outputting two paths of rubidium clock frequency division second pulse signals, one path of rubidium clock frequency division second pulse signal is input into the central processing module after passing through the isolation distribution amplifier, and the other path of rubidium clock frequency division second pulse signal is input into the phase discriminator; the phase discriminator is used for receiving the filtered Beidou second pulse signal and one path of rubidium clock frequency division second pulse signal simultaneously and carrying out phase discrimination processing, and the output end of the phase discriminator is sequentially connected with the digital loop filter and the A/D sampler and is used for carrying out frequency adjustment and phase error control on the output signal to obtain a measurement signal and inputting the measurement signal into the central processing module; the central processing module is used for calculating an offset correction value according to the measurement signal and the rubidium clock frequency division second pulse signal and inputting the offset correction value into the frequency synthesizer; the isolation distribution amplifier is used for outputting a plurality of rubidium clock signals.

At present, BDS receiver products are mature, and the precision test of a general time service precision module is carried out by taking second pulses provided by a BDS tame clock as a reference. The main technology of the rubidium clock taming and digital purification phase-locked loop in the device for the Beidou ultra-stable low-phase noise crystal oscillator taming rubidium atomic clock is explained in detail below.

1. Rubidium clock tame unit

The rubidium clock taming unit uses 1pps generated by the BDS receiver to perform frequency calibration on the local frequency standard. 1pps generated by the BDS receiver has a certain jitter, but the BDS receiver has better long-term stability; the standard short-term stability of the local rubidium clock is good, but frequency drift exists, so that the advantages of the standard short-term stability and the standard short-term stability of the local rubidium clock are combined by correcting the local frequency reference by 1pps, and the standard short-term stability of the local rubidium clock has the advantage of good long-term stability of a BDS receiver and the characteristic of good short-term stability of the local rubidium clock. The BDS tame clock system is characterized in that the BDS tame clock system is a rubidium clock tame unit, and the rubidium clock tame generally comprises 3 processes of frequency difference measurement, second jitter processing and frequency calibration.

1.1 frequency Difference measurement

The frequency difference measurement generally adopts phase difference measurement, and a period difference is obtained by measuring the phase difference, so that a difference value between frequencies is obtained; typically by measuring the 1pps signal phase difference between the 1pps signal produced by the BDS receiver and the local rubidium clock frequency standard. The phase difference is generally measured by a pulse interval counter, i.e. a counter counts between two 1pps signals with pulses of a certain frequency.

Let the 1pps signal period of BDS be T ₁ The time at which the receiver recovers from the nth second from the test is nT ₁ +Φ _1n . The second period of the local rubidium frequency scale is T ₂ Then the nth second pulse output time is nT ₂ +a, a is the initial phase error. The periodic difference measurement principle is shown in fig. 2.

N second measurement: s is S _n ＝nT ₁ +Φ _1n -nT ₂ -a

Difference between two adjacent seconds: s is S _n -S _n-1 ＝T ₁ -T ₂ +Φ _1n -Φ _1(n-1)

The period is bad:

due to phi _1n A random quantity with a mean value of 0, and therefore:

the period is poor:

when using time interval counting for phase difference measurement, the measurement accuracy depends on the pulse frequency. A crystal oscillator of 10MHz, the measurement accuracy is 100ns; the precision can be improved by adopting a frequency multiplication phase-locked circuit, and if a 10MHz rubidium clock adopts 10 frequency multiplication, the measurement precision of 10ns can be obtained; for example, digital clock management (Digital Clock Manager, DCM) using FPGA can obtain a frequency of up to about 150MHz, so that measurement accuracy of about 6.67ns can be obtained. In order to further improve the measurement accuracy, the quantization error has to be measured.

One method is to convert the quantization error into a voltage amplitude, i.e., T-V method, and obtain an accurate value of the quantization error through high resolution a/D sampling. At present, the method is technically realized by related documents, a set of counter which adopts a capacitance charge-discharge technology and combines a double-channel A/D converter is developed, the clock frequency of the counter is 10MHz, and the measurement resolution reaches 0.4ns. The other method adopts a quantization delay method to measure quantization errors; by utilizing the stable time delay characteristic of the signal propagating in the medium and by quantifying the time delay of the signal, the measurement of short time intervals is realized. The basic principle is shown in figure 3. The signal passes through a series of delay units, and the delay state is collected at high speed and processed under the control of a computer by means of the delay stability of the delay units, so that accurate measurement of short time intervals is realized. The implementation of the quantization delay depends on the delay stability of the delay unit, and the resolution thereof depends on the delay time of the unit delay unit. Part of the references uses delay cells of an FPGA as delay lines, employing 128 delay cells, with a measurement resolution of 100ps.

1.2, second jitter handling

The BDS receiver has the characteristics of long signal transmission distance, easy interference and the like, and the output 1pps signal has a certain jitter. 1pps contains a number of error components: satellite clock errors, ephemeris errors, ionosphere additive delay errors, troposphere additive delay errors, multipath errors, and errors of the receiver itself. Due to the jitter of the 1pps signal, measures need to be taken to cope with the jitter of 1 pps. The jitter of the BDS receiver output 1pps signal mostly belongs to random errors. Due to the existence of the random errors, the front edge of the BDS pulse signal has jitter, which can reach 100ns at maximum, so that the phase discrimination errors also have random jump. The module adopts a Kalman filtering algorithm to filter interference and noise in phase discrimination errors, and extracts needed information.

1.3 frequency calibration

Carrying out digital phase discrimination on 1pps output by the satellite time service receiver and 1pps signal output by local frequency division; the phase discrimination result is sent to a central processing module which is provided with a regulator, and the regulator can obtain a frequency difference according to the phase discrimination result or obtain a regulating value by adopting a feedback control method; the adjustment amount adjusts the frequency of the local frequency source. The frequency calibration unit of fig. 1 can be simplified to the schematic diagram of fig. 4, which is a feedback control system, and a better adjustment can be obtained by PI control.

When PI control is adopted, the PI regulator generates regulating voltage according to the phase discrimination value output by the digital phase discriminator, under the regulating voltage, according to the characteristics of the PI regulator, 1pps output locally can gradually track 1pps of the satellite, if the 1pps of the satellite is stable, the final phase error is 0. The frequency of the local 1pps locked satellite is calibrated after 1 pps.

Further simplifying fig. 4 into a control system block diagram, fig. 5 may be obtained. E (S) is the obtained phase difference, K _P Is a proportionality coefficient, K _i Is an integral coefficient. V (S) is the output of the proportional integrator. For voltage-controlled OCXO, if the input voltage and the output frequency have a certain proportional relationship, the ratio is considered to be equivalent to a proportional link, K is used _F And (3) representing. F (S) represents the output frequency, frequency division corresponds to an integration step, and Y (S) represents the output phase. It can be seen that the satellite discipline system employing PI regulators is a second order system. The transfer function of this second order system is found according to block 5 as follows:

it can be seen that the transfer function is a typical second order system with two poles, a zero, and the denominator can be expressed as:

S ² +K _P ·K _F ·S+K _i ·K _F ＝S ² +2ξw _n ² +w _n ²

damping coefficientResonance frequency->Maximum overshoot->

When the system is built, K _F Is basically stable. From the above, it can be seen that K _P The larger the damping coefficient is, the larger the damping coefficient is; k (K) _i The larger the resonance frequency, the higher the number of oscillations to reach a steady state value increases. From the above analysis, K _P And K is equal to _i The choice of (2) determines the tracking response of the system.

The following details the process of BDS taming rubidium clocks:

a) Frequency calibration: at this stage, the 1pps signal obtained by frequency division of the rubidium clock starts to track 1pps of the BDS, at this time, due to a certain phase difference, the regulation control voltage of the rubidium clock is not established yet, and the frequency of the rubidium clock has a certain deviation, at this stage, the frequency calibration is mainly performed, and the phase difference is gradually eliminated.

b) Frequency locking: after the frequency difference is obtained, an adjustment value is generated according to the frequency control characteristic of the rubidium frequency standard, and the adjustment value is used for adjusting the local frequency source. According to the characteristics of the local frequency source, the regulation modes are various, and when the local rubidium clock is voltage-controlled or can be regulated in a small range by using voltage, the output regulation quantity is voltage; the control voltage is usually realized by adopting a D/A conversion module, and the requirement can be met by adopting a serial D/A chip because the requirement on the D/A conversion rate is not high. To reduce the cost, it is proposed to obtain the control voltage by controlling the RC charging time. When the local frequency source is DDS output, the frequency control word is regulated according to the regulating value.

The method for obtaining the regulating value is various, the regulating value can be obtained by adopting a feedback regulating method, and in the feedback compensation, the PI regulator is widely applied due to the simple structure and good dynamic performance. Because the local rubidium clock is unstable in frequency except for inaccurate frequency, drift exists. The frequency calibration link realizes the calibration of relative frequency deviation, and still cannot solve the problem caused by the instability of the frequency of the rubidium clock. In order to overcome the instability of the self frequency of the rubidium clock, frequency compensation measures are needed. There are two types of frequency compensation measures: one is to carry out frequency compensation according to temperature, establish the relation between temperature and frequency, obtain frequency control voltage according to temperature, realize the compensation; and according to time compensation, establishing a relation between time and control voltage according to a curve of frequency change along with time, which is obtained in advance, so as to carry out compensation.

After the frequency calibration phase is completed, the frequency of the rubidium clock is basically calibrated, the phase difference between the rubidium clock and the 1pps signal of the BDS is maintained in a smaller range, and the frequency locking phase is entered at the moment; at this stage, the control voltage deviation and the rubidium clock frequency drift caused by circuit instability are mainly overcome. At this stage, since the frequency of the rubidium clock is calibrated, the output frequency-divided 1pps signal has high stability, and the 1pps signal of the BDS has a certain jitter, so the influence caused by the 1pps jitter of the BDS needs to be reduced.

By analyzing the BDS tamed rubidium clock process, it can be seen that: in the phase of frequency calibration, it is necessary to quickly realize phase tracking and avoid a large phase overshoot, so a large K can be used _P The method comprises the steps of carrying out a first treatment on the surface of the In the frequency locking stage, the jitter of 1pps of the BDS receiver needs to be avoided, and smaller K can be adopted _P The method comprises the steps of carrying out a first treatment on the surface of the In the frequency locking phase, the frequency is adjusted within a small range, the frequency adjustment should be performed slowly to avoid abrupt phase changes, the control of 1pps signal of BDS should be weakened, K _i Should also be reduced. K (K) _P 、K _i The variation of (2) is shown in fig. 6. After the frequency calibration stage is completed, the control voltage value of the rubidium clock is kept stable, and the control voltage can be changed if the proportional-integral coefficient is changed; to prevent abrupt changes in the control voltage values, the change in the coefficients should be made stepwise. There is thus a parameter adjustment phase between the frequency calibration and the frequency locking phase.

After the Beidou domestication of the rubidium atomic frequency standard, the short-term stability of the rubidium clock and the relative frequency deviation of the Beidou system are maintained, and the domestication relative frequency deviation is better than 1 multiplied by 10 ^-12 (5X 10 in stable condition) ^-13 )。

2. Digital phase-locked loop design

The short-term frequency stability of rubidium clock is generally (1-3) x 10 ^-11 On the left and right, improvements in short term frequency stability are needed. The invention adopts a full digital purification phase-locked loop to lock the crystal oscillator onto the rubidium clock module by selecting a high-stability crystal oscillator, the phase-locked loop module in fig. 1 can be simplified into a schematic diagram shown in fig. 7, the phase-locked loop module comprises a filter, a digital phase discriminator, a digital filter, a first amplifier, a D/A converter and a second amplifier, a clock signal output by the rubidium clock module and outputted by the rubidium Zhong Tongjing oscillator is inputted into the digital phase discriminator for phase discrimination, and then a narrow-band digital filter is used for filtering high-frequency alternating current components and controlling the voltage-controlled constant-temperature crystal oscillator frequency, so that frequency synchronization is realized. The short stability of the crystal oscillator is maintained, and the characteristics of the rubidium clock are also maintained.

The digital phase detector in fig. 7, namely, the digital phase-locked loop, is mainly composed of four parts of a phase detector, a K-mode reversible counter, a pulse add-subtract circuit and a divide-by-N counter as shown in fig. 8. The clocks of the reversible counter and the N frequency divider are provided by an external crystal oscillator, a built-in voltage-controlled oscillator is not needed, the influence of temperature and power supply voltage change on a loop can be greatly reduced, and meanwhile, the system is realized by adopting a programmable chip of the system, so that the integration level and the reliability of the system are improved. Clock of K-mode counter and pulse addition and subtraction circuitMf respectively _c And 2Nf _c ，f _c Is the loop center frequency, typically M and N are integer powers of 2. The two clocks in the present invention use the same system clock signal.

When the loop is out of lock, the exclusive-or gate phase discriminator compares the input signal f _in And output signal f _out The phase difference between the two counter units and generating a counting direction control signal dnup of the K-mode reversible counter; the K modulo-reversible counter adjusts the count value according to the count direction control signal dnup, the dnup is high to count down, and when the count value reaches 0, a borrowing pulse signal borow is output; the direction control signal dnup is low to count up, and when the count value reaches a preset K module value, a carry pulse signal carryo is output; the pulse adding and subtracting circuit performs pulse adding and subtracting operations in the circuit output signal idout according to the carry pulse signal carryo and the borrow pulse signal borow to adjust the frequency of the output signal; the above adjustment process is repeated, when the loop enters the locked state, the output se of the exclusive or gate phase discriminator is a square wave with a duty ratio of 50%, and the K-mode reversible counter periodically generates a carry pulse output carryo and a borrow pulse output borow, which results in the periodic addition and subtraction of half pulses from the output idout of the pulse adding and subtracting circuit. This has no effect on the frequency of the output and can remove noise that appears with equal probability.

The stability of PRS10 is measured by a TSC 5120A phase noise tester by selecting a PRS10 rubidium clock and MV341 (5E-13) high-stability crystal oscillator, and the frequency stability index of a rubidium clock module after the rubidium clock, the crystal oscillator and the crystal oscillator are phase-locked is shown in the following table 1:

TABLE 1 frequency stability index for rubidium clock, crystal Oscillator and rubidium clock Module after Crystal Oscillator phase locking

In the phase locking process, the stability parameter can be improved by adjusting the phase discrimination frequency of the digital phase discriminator, and the ideal effect can be achieved by measuring and selecting 10 Hz. The voltage-controlled end of the crystal oscillator needs to be regulated in real time to follow the change of the rubidium clock frequency, and the phase-locked loop has a certain influence on the short-term stability of the crystal oscillator.

Example two

A method for the ultra-stable low-phase-noise crystal oscillator tame rubidium atomic clock of Beidou is applied to the device in the first embodiment, and specifically comprises the following steps:

a rubidium clock oscillation signal is generated through a high-precision anti-vibration rubidium clock, and a clock signal is generated through a crystal oscillator;

the rubidium clock oscillation signal and the clock signal are sequentially sent to a phase-locked loop module, a frequency synthesizer, an isolation distribution amplifier and a frequency divider for processing, the output end of the frequency divider outputs two paths of rubidium clock frequency division second pulse signals, one path of rubidium clock frequency division second pulse signals is input to a central processing module after passing through the isolation distribution amplifier, and the other path of rubidium clock frequency division second pulse signals are input to a phase discriminator; isolation distribution amplifier outputs multiple rubidium clock signals

Receiving a Beidou second pulse signal remotely transmitted by a Beidou system through a Beidou receiver and performing filtering processing;

the phase discriminator receives the filtered Beidou second pulse signal and one path of rubidium clock frequency division second pulse signal simultaneously and carries out phase discrimination processing, and an output signal of the phase discriminator is sequentially filtered and sampled to obtain a measuring signal comprising phase difference information;

and the central processing module calculates a deviation correction value according to the measurement signal, and the deviation correction value is sent to the frequency synthesizer.

Specifically, the method comprises the following process of the Beidou tamarind rubidium clock:

frequency calibration stage: in the stage, the output end of the frequency divider outputs two paths of rubidium clock frequency-dividing second pulse signals to start tracking the filtered Beidou second pulse signals, frequency calibration is carried out, phase differences are gradually eliminated, and the phase differences between the calibrated rubidium clock frequency-dividing second pulse signals and the Beidou second pulse signals are within a preset range;

parameter adjustment stage: after the frequency calibration stage is completed, the control voltage value of the high-precision anti-vibration rubidium clock is kept stable, and the proportional coefficient and the integral coefficient are gradually changed, wherein the proportional coefficient and the integral coefficient are control parameters when the device adopts PI feedback control;

frequency locking phase: the central processing module generates an adjusting value according to the frequency control characteristic of the rubidium frequency standard, and the adjusting value is used for adjusting the output signal of the local frequency source, namely the frequency synthesizer.

The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be appreciated by persons skilled in the art that the above embodiments are not intended to limit the invention in any way, and that all technical solutions obtained by means of equivalent substitutions or equivalent transformations fall within the scope of the invention.

Claims (5)

1. The utility model provides a device of super steady low phase noise crystal oscillator tame rubidium atomic clock of big dipper which characterized in that includes: the system comprises a Beidou receiver, a Kalman filter, a phase discriminator, a digital loop filter, an A/D (analog to digital) sampler, a central processing unit, a high-precision anti-seismic rubidium clock, a crystal oscillator, a phase-locked loop module, a frequency synthesizer, an isolation distribution amplifier, a frequency divider and a time isolation module;

the output end of the Beidou receiver is connected with a Kalman filter and is used for receiving the Beidou second pulse signals remotely transmitted by the Beidou system and carrying out filtering treatment;

the high-precision anti-vibration rubidium clock is used for generating a rubidium clock oscillation signal, the crystal oscillator is used for generating a clock signal, the phase-locked loop module is used for receiving the rubidium clock oscillation signal and the clock signal, the phase-locked loop module, the frequency synthesizer, the isolation distribution amplifier and the frequency divider are sequentially connected, the frequency divider is used for outputting two paths of rubidium clock frequency division second pulse signals, one path of rubidium clock frequency division second pulse signal is input into the central processing module after passing through the isolation distribution amplifier, and the other path of rubidium clock frequency division second pulse signal is input into the phase discriminator;

the phase discriminator is used for receiving the filtered Beidou second pulse signal and one path of rubidium clock frequency division second pulse signal simultaneously and carrying out phase discrimination processing, and the output end of the phase discriminator is sequentially connected with the digital loop filter and the A/D sampler and is used for carrying out frequency adjustment and phase error control on the output signal to obtain a measurement signal and inputting the measurement signal into the central processing module;

the central processing module is used for calculating an offset correction value according to the measurement signal and the rubidium clock frequency division second pulse signal and inputting the offset correction value into the frequency synthesizer;

the isolation distribution amplifier is used for outputting a plurality of rubidium clock signals.

2. The device for the Beidou ultra-stable low-phase-noise crystal oscillator taming rubidium atomic clock of claim 1, wherein the device is characterized in that: the phase-locked loop module comprises a filter, a digital phase discriminator, a digital filter, a first amplifier, a D/A converter and a second amplifier, wherein an output signal of the rubidium clock module and a clock signal output by the crystal oscillator are input into the digital phase discriminator for phase discrimination, then a high-frequency alternating current component is filtered by the digital filter, and after the output signal of the digital filter is amplified, digital-to-analog converted and amplified in sequence, a feedback control signal is obtained and is input into the crystal oscillator module for controlling the voltage-controlled constant-temperature crystal oscillator frequency of the crystal oscillator, so that frequency synchronization is realized.

3. The device for the Beidou ultra-stable low-phase-noise crystal oscillator taming rubidium atomic clock of claim 1, wherein the device is characterized in that: the digital phase discriminator adopts a structure of an all-digital purification phase-locked loop, and comprises an exclusive-OR gate phase discriminator, a K-mode reversible counter, a pulse addition and subtraction circuit and a divide-by-N reader which are sequentially connected, wherein the exclusive-OR gate phase discriminator is used for receiving an input signal and a feedback signal, and the divide-by-N reader is used for sending two paths of output signals, and one path of output signal is used as a feedback signal to be sent to the input end of the exclusive-OR gate phase discriminator.

4. A method for the ultra-stable low-phase noise crystal oscillator tamed rubidium atomic clock of Beidou, which is applied to the device of any one of claims 1 or 3, and is characterized by comprising the following steps:

a rubidium clock oscillation signal is generated through a high-precision anti-vibration rubidium clock, and a clock signal is generated through a crystal oscillator;

the rubidium clock oscillation signal and the clock signal are sequentially sent to a phase-locked loop module, a frequency synthesizer, an isolation distribution amplifier and a frequency divider for processing, the output end of the frequency divider outputs two paths of rubidium clock frequency division second pulse signals, one path of rubidium clock frequency division second pulse signals is input to a central processing module through a time interval measuring module, and the other path of rubidium clock frequency division second pulse signals are input to a phase discriminator; isolation distribution amplifier outputs multiple rubidium clock signals

Receiving a Beidou second pulse signal remotely transmitted by a Beidou system through a Beidou receiver and performing filtering processing;

the phase discriminator receives the filtered Beidou second pulse signal and one path of rubidium clock frequency division second pulse signal simultaneously and carries out phase discrimination processing, and an output signal of the phase discriminator is sequentially filtered and sampled to obtain a measuring signal comprising phase difference information;

and the central processing module calculates a deviation correction value according to the measurement signal, and the deviation correction value is sent to the frequency synthesizer.

5. The method for the Beidou ultra-stable low-phase noise crystal oscillator tame rubidium atomic clock of claim 4, which is characterized by comprising the following processes of the Beidou tame rubidium clock:

frequency calibration stage: in the stage, the output end of the frequency divider outputs two paths of rubidium clock frequency-dividing second pulse signals to start tracking the filtered Beidou second pulse signals, frequency calibration is carried out, phase differences are gradually eliminated, and the phase differences between the calibrated rubidium clock frequency-dividing second pulse signals and the Beidou second pulse signals are within a preset range;

parameter adjustment stage: after the frequency calibration stage is completed, the control voltage value of the high-precision anti-vibration rubidium clock is kept stable, and the proportional coefficient and the integral coefficient are gradually changed, wherein the proportional coefficient and the integral coefficient are control parameters when PI feedback control is adopted by the device;

frequency locking phase: the central processing module generates an adjusting value according to the frequency control characteristic of the rubidium frequency standard, and the adjusting value is used for adjusting the output signal of the local frequency source.