CN117440711A - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN117440711A CN117440711A CN202311365855.XA CN202311365855A CN117440711A CN 117440711 A CN117440711 A CN 117440711A CN 202311365855 A CN202311365855 A CN 202311365855A CN 117440711 A CN117440711 A CN 117440711A
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- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 158
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000009832 plasma treatment Methods 0.000 claims abstract description 24
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 361
- 239000011241 protective layer Substances 0.000 claims description 39
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 11
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 5
- 239000011787 zinc oxide Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- -1 silicon nitride compound Chemical class 0.000 description 8
- 239000000470 constituent Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 3
- 239000011112 polyethylene naphthalate Substances 0.000 description 3
- 229920000139 polyethylene terephthalate Polymers 0.000 description 3
- 239000005020 polyethylene terephthalate Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229920000089 Cyclic olefin copolymer Polymers 0.000 description 2
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- 101150064205 ESR1 gene Proteins 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- WGCNASOHLSPBMP-UHFFFAOYSA-N hydroxyacetaldehyde Natural products OCC=O WGCNASOHLSPBMP-UHFFFAOYSA-N 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The application provides an array substrate, a preparation method thereof and a display device, the method comprises the steps of forming a buffer layer, forming a semiconductor layer on one side of the buffer layer, forming a gate insulating layer on one side of the semiconductor layer, deviating from the buffer layer, wherein orthographic projection of the gate insulating layer on the buffer layer falls into orthographic projection of the semiconductor layer on the buffer layer, carrying out plasma treatment on the semiconductor layer to enable partial semiconductor in the semiconductor layer to be converted into a conductor, the semiconductor layer after the plasma treatment comprises a semiconductor region and a semiconductor formation region, forming a gate layer on one side of the gate insulating layer, deviating from the buffer layer, enabling orthographic projection of the gate layer on the semiconductor layer to fall into the semiconductor region, and enabling the gate insulating layer and the gate layer to be prepared through different masks. The mask for preparing the gate insulating layer is not limited by the mask for preparing the gate layer, and the length of a semiconductor region in the semiconductor layer to be protected can be adjusted, so that the effective length of a semiconductor channel corresponding to the gate layer is ensured.
Description
Technical Field
The application relates to the field of manufacturing of array substrates, in particular to an array substrate, a manufacturing method thereof and a display device.
Background
The display industry is currently undergoing various changes, and the product types and product properties are also more and more excellent. The IGZO (Indium Gallium Zinc Oxide ) array substrate has the characteristics of large mobility, high on-state current, better switching characteristics and better uniformity, and can be suitable for applications requiring quick response and large current, such as high-frequency, high-resolution and large-size displays, organic light-emitting displays and the like.
However, in the related art IGZO array substrate manufacturing method, plasma treatment is liable to contaminate the semiconductor channel, resulting in shortening of the effective channel length, affecting the stability of the operation of the array substrate.
Disclosure of Invention
The invention aims to provide an array substrate, a preparation method thereof and a display device, which are used for solving the technical problems that in the preparation method of an IGZO array substrate in the related art, plasma treatment is easy to pollute a semiconductor channel, so that the effective channel length is shortened, and the working stability of the array substrate is affected.
In a first aspect, the present application provides a method for manufacturing an array substrate, including;
forming a buffer layer;
forming a semiconductor layer on one side of the buffer layer;
forming a gate insulating layer on one side of the semiconductor layer, which is away from the buffer layer, wherein orthographic projection of the gate insulating layer on the buffer layer falls into orthographic projection of the semiconductor layer on the buffer layer;
performing plasma treatment on the semiconductor layer to convert part of the semiconductor in the semiconductor layer into a conductor, wherein the semiconductor layer after the plasma treatment comprises a semiconductor region and a conductor region;
and forming a gate layer on one side of the gate insulating layer, which is away from the buffer layer, so that orthographic projection of the gate layer on the semiconductor layer falls into the semiconductor region, wherein the gate insulating layer and the gate layer are prepared through different masks.
The preparation method of the array substrate further comprises the following steps:
and forming a protective layer on one side of the semiconductor layer, which is away from the buffer layer, wherein the protective layer is arranged between the protective layer and the grid electrode layer, and the orthographic projection of the protective layer and the grid electrode insulating layer on the buffer layer covers the orthographic projection of the semiconductor layer on the buffer layer.
The protective layer and the grid layer are prepared through the same mask plate, and the material of the protective layer is the same as that of the grid layer.
Wherein before forming the buffer layer, the method further comprises:
forming a bearing substrate;
and forming a shading layer on one side of the bearing substrate.
The preparation method of the array substrate further comprises the following steps:
forming an interlayer dielectric insulation layer on one side of the gate layer, which is away from the buffer layer, wherein the interlayer dielectric insulation layer covers the gate layer, the gate insulation layer and the protection layer;
and forming a second via hole of the first via hole on the interlayer dielectric insulating layer, wherein the first via hole penetrates through the interlayer dielectric insulating layer to be connected with the protective layer, and the second via hole penetrates through the interlayer dielectric insulating layer, the gate insulating layer, the buffer layer and the shading layer in sequence.
Wherein the performing plasma treatment on the semiconductor layer comprises:
inert gas is used to react with the semiconductor layer.
Wherein the material of the semiconductor layer comprises at least one of indium gallium zinc oxide, indium zinc oxide, zinc tin oxide and indium gallium zinc tin oxide; the material of the gate layer includes at least one of titanium, aluminum, molybdenum, copper.
In a second aspect, the present application provides an array substrate, which is prepared by the preparation method of the array substrate, where the array substrate includes:
a buffer layer;
the semiconductor layer is arranged on the buffer layer and comprises a semiconductor region and a conductor region;
the grid insulation layer is arranged on one side, away from the buffer layer, of the semiconductor layer, and orthographic projection of the semiconductor layer on the buffer layer covers orthographic projection of the grid insulation layer on the buffer layer;
the grid electrode layer is arranged on one side, away from the buffer layer, of the grid electrode insulating layer, and orthographic projection of the grid electrode layer on the semiconductor layer falls into the semiconductor region;
the protective layer is arranged on one side, away from the buffer layer, of the semiconductor layer, the protective layer is arranged at intervals with the grid electrode layer, and the semiconductor layer is covered by the protective layer and the grid electrode insulating layer.
The material of the protective layer is the same as that of the grid layer.
In a third aspect, the present application provides a display device, where the display device includes a housing and the array substrate, and the housing is configured to carry the array substrate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application;
fig. 2 is a cross-sectional view of an array substrate according to an embodiment of the present application;
fig. 3 is a cross-sectional view of an array substrate after forming a semiconductor layer according to an embodiment of the present application;
fig. 4 is a cross-sectional view of an array substrate for performing plasma processing according to an embodiment of the present application;
fig. 5 is a cross-sectional view of an array substrate after forming a gate layer according to an embodiment of the present application;
FIG. 6 is a flowchart of a process S400 for manufacturing an array substrate according to an embodiment of FIG. 1;
fig. 7 is a step diagram of S600 in a process of a method for manufacturing an array substrate according to an embodiment of the present application;
fig. 8 is a step S700 diagram in a process of a method for manufacturing an array substrate according to an embodiment of the present application;
fig. 9 is a flowchart of a method included before a process S100 of a method for manufacturing an array substrate according to an embodiment of the present application;
fig. 10 is a flowchart of a method further included after the process S700 of the preparation method of an array substrate according to the embodiment of the present application;
fig. 11 is a schematic diagram of a display device according to an embodiment of the present application.
Description of the reference numerals:
the display device comprises a display device-1, an array substrate-100, a buffer layer-10, a semiconductor layer-20, a semiconductor region-21, a conductive region-22, a gate insulating layer-30, a gate layer-41, a protective layer-42, an interlayer dielectric insulating layer-50, a conductive metal layer-60, a connecting electrode-61, a light shielding layer-72, a first via hole-81, a second via hole-82 and a housing-200.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without undue burden, are within the scope of the present application.
Reference herein to "an embodiment" or "an implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the described constituent elements. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.
In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The meaning of the above terms in the present disclosure can be understood by one of ordinary skill in the art as appropriate.
The display industry is currently undergoing various changes, and the product types and product properties are also more and more excellent. The IGZO array substrate has the characteristics of large mobility, high on-state current, better switching characteristics and better uniformity, and can be suitable for applications requiring quick response and large current, such as high-frequency, high-resolution and large-size displays, organic light-emitting displays and the like.
However, in the related art IGZO array substrate manufacturing method, plasma treatment is liable to contaminate the semiconductor channel, resulting in shortening of the effective channel length, affecting the stability of the operation of the array substrate.
Specifically, the array substrate generally adopts a Top Gate (Top Gate) device structure, and a semiconductor layer in contact with the source and drain electrodes needs to be subjected to plasma treatment. In the related art, the gate and the gate insulating layer (GI) are prepared through a mask, so that during plasma treatment of the semiconductor layer, the semiconductor channel of the corresponding gate in the semiconductor layer is easily polluted, the length of the effective channel is shortened, and unstable phenomena such as TFT drift are easily generated.
The application provides a preparation method of an array substrate, which aims to solve the technical problems that in the preparation method of an IGZO array substrate in the related art, plasma treatment is easy to pollute a semiconductor channel, so that the effective channel length is shortened, and the working stability of the array substrate is affected.
Referring to fig. 1 to 5, the method for manufacturing the array substrate 100 includes, but is not limited to, steps S100, S200, S300, S400 and S500, and the detailed descriptions of the steps S100, S200, S300, S400 and S500 are as follows.
S100: the buffer layer 10 is formed.
The material of the buffer layer 10 includes, but is not limited to, a silicon nitride compound, a silicon oxide compound, and the like. The buffer layer 10 may be used to buffer the impact received by the array substrate 100, so as to avoid displacement or damage of other structural members on the array substrate 100 and influence the working stability of the array substrate 100.
S200: a semiconductor layer 20 is formed on one side of the buffer layer 10.
The material of the semiconductor layer 20 includes, but is not limited to, at least one of indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, and indium gallium zinc tin oxide.
S300: a gate insulating layer 30 is formed on the side of the semiconductor layer 20 facing away from the buffer layer 10, wherein the orthographic projection of the gate insulating layer 30 onto the buffer layer 10 falls into the orthographic projection of the semiconductor layer 20 onto the buffer layer 10.
The orthographic projection of the gate insulating layer 30 on the buffer layer 10 falls within the orthographic projection of the semiconductor layer 20 on the buffer layer 10, in other words, the width of the gate insulating layer 30 is smaller than the width of the semiconductor layer 20, that is, the size of the gate insulating layer 30 is smaller than the size of the semiconductor layer 20 along the first direction D1, wherein the first direction D1 is shown in fig. 4. So that a portion of the semiconductor layer 20 can be exposed with respect to the gate insulating layer 30 to facilitate a subsequent plasma treatment of the exposed semiconductor layer 20.
Specifically, in the present embodiment, both ends of the semiconductor layer 20 along the first direction D1 are exposed from the gate insulating layer 30, so as to facilitate electrical connection with the subsequent source and drain electrodes.
S400: the semiconductor layer 20 is subjected to plasma treatment to convert part of the semiconductor in the semiconductor layer 20 into a conductor, and the semiconductor layer 20 after the plasma treatment includes a semiconductor region 21 and a conductive region 22.
Specifically, the semiconductor layer 20 is subjected to plasma treatment, mainly to a portion of the semiconductor layer 20 where the gate insulating layer 30 is exposed. However, in the case of plasma treatment of the semiconductor layer 20, the portion of the semiconductor layer 20 exposed to the gate insulating layer 30 is subjected to plasma treatment and then is subjected to a conductor treatment, and the portion covered with the gate insulating layer 30 is also subjected to a conductor treatment to some extent by being close to the conductor region 22, so that the size of the conductor region 22 in the first direction D1 is larger than the size of the semiconductor layer 20 exposed to the gate insulating layer 30.
In the present embodiment, the conductive region 22 includes a first conductive region 22 and a second conductive region 22, the first conductive region 22 and the second conductive region 22 are located at both ends of the conductive region 22, respectively, the first conductive region 22 has a size larger than that of the semiconductor layer 20 in which one end is exposed to the gate insulating layer 30, and the second conductive region 22 has a size larger than that of the semiconductor layer 20 in which the other end is exposed to the gate insulating layer 30.
Further, referring to fig. 4 and 6 together, the "performing plasma processing on the semiconductor layer 20" in S400 includes, but is not limited to, step S410, and the detailed description of step S410 is as follows.
S410: inert gas is used to react with the semiconductor layer 20.
Wherein the inert gas includes, but is not limited to, helium (He), argon (Ar), or other gases. Alternatively, in other embodiments, a gas such as nitrogen, ammonia, carbon tetrafluoride, or the like may be used to react with the semiconductor layer 20 to make the semiconductor layer 20 conductive, but since the semiconductor layer 20 is sensitive to hydrogen (H), the inert gas is preferably used to react with the semiconductor layer 20 in this embodiment in consideration of the influence of the subsequent process conditions on the stability of the device, which should not be construed as limiting the present application.
S500: a gate layer 41 is formed on a side of the gate insulating layer 30 facing away from the buffer layer 10, such that an orthographic projection of the gate layer 41 onto the semiconductor layer 20 falls into the semiconductor region 21, wherein the gate insulating layer 30 and the gate layer 41 are prepared by different masks.
Optionally, the method of preparing the gate layer 41 includes, but is not limited to, etching by a dry etching process, a wet etching process, or other processes, and the material of the gate layer 41 includes at least one of titanium, aluminum, molybdenum, copper.
In the related art, the gate and the gate insulating layer (GI) are prepared through a mask, so that during plasma treatment of the semiconductor layer, the semiconductor channel of the corresponding gate in the semiconductor layer is easily polluted, the length of the effective channel corresponding to the gate is shortened, and unstable phenomena such as TFT drift are easily generated.
In the method for manufacturing the array substrate 100 provided in the present application, after the buffer layer 10, the semiconductor layer 20, and the gate insulating layer 30 are sequentially formed, the semiconductor layer 20 is subjected to a plasma treatment, and finally the gate layer 41 is formed. The gate insulating layer 30 and the gate layer 41 are manufactured through different masks, in other words, the mask for manufacturing the gate insulating layer 30 is not limited by the mask for manufacturing the gate layer 41, and the length of the semiconductor region 21 in the semiconductor layer 20 to be protected can be adjusted so that the width of the semiconductor region 21 is larger than the width of the gate layer 41, thereby ensuring the effective length of the semiconductor channel corresponding to the gate layer 41, avoiding unstable phenomena such as TFT offset caused by insufficient effective channel length of the TFT, and reducing the probability of unstable operation of the array substrate 100.
Further, in the plasma treatment, the region where the gate insulating layer 30 covers is also a region where a certain degree of conduction occurs due to the proximity to the conductive region 22 is usually in the range of 2 μm to 3 μm, in other words, the region where one end of the gate insulating layer 30 covers is in the range of 1 μm to 1.5 μm. Therefore, if it is required to ensure that the orthographic projection of the gate layer 41 on the semiconductor layer 20 falls into the semiconductor region 21, the mask for preparing the gate insulating layer 30 and the mask for preparing the gate layer 41 need to be adjusted so that the size of the gate insulating layer 30 is larger than the size of the gate layer 41 in the first direction D1, and the difference between the size of the gate insulating layer 30 and the size of the gate layer 41 ranges from 2 μm to 3 μm, in other words, the exposed size of one end of the gate insulating layer 30 compared with the exposed size of one end of the gate layer 41 ranges from 1 μm to 1.5 μm. Alternatively, in the present embodiment, the dimension of the one end of the gate insulating layer 30 exposed compared to the one end of the gate layer 41 may be 1 μm, or 1.1 μm, or 1.2 μm, or 1.3 μm, or 1.4 μm, or 1.5 μm, or other values within 1 μm-1.5 μm, and in other embodiments, the dimension range of the one end of the gate insulating layer 30 exposed compared to the one end of the gate layer 41 may be adjusted according to the specification of the array substrate 100, which is not limited in this application.
Referring to fig. 2, 5 and 7, in one embodiment, the method for manufacturing the array substrate 100 further includes S600, and the detailed description of step S600 is as follows.
S600: a protective layer 42 is formed on the side of the semiconductor layer 20 facing away from the buffer layer 10, the protective layer 42 being arranged at a distance from the gate layer 41, wherein the front projection of the protective layer 42 and the gate insulation layer 30 onto the buffer layer 10 covers the front projection of the semiconductor layer 20 onto the buffer layer 10.
The front projection of the protective layer 42 and the gate insulating layer 30 onto the buffer layer 10 covers the front projection of the semiconductor layer 20 onto the buffer layer 10, in other words, the protective layer 42 and the gate insulating layer 30 cover the semiconductor layer 20.
In this embodiment, the step S600 "of forming the protective layer 42" on the side of the semiconductor layer 20 facing away from the buffer layer 10 and the step S500 "of forming the gate layer 41" on the side of the gate insulating layer 30 facing away from the buffer layer 10 are performed by one process, and the protective layer 42 and the gate layer 41 are performed by the same mask, and the material of the protective layer 42 is the same as the material of the gate layer 41.
The protection layer 42 covers a portion of the semiconductor layer 20 where the gate insulating layer 30 is exposed, and the protection layer 42 may be used to protect the semiconductor layer 20, so as to avoid the influence of the subsequent preparation process on the material of the semiconductor layer 20, thereby effectively ensuring the performance of the semiconductor layer 20.
The protection layer 42 includes a first protection region and a second protection region, wherein the first protection region covers the first conductive region 22, and the second protection region covers the second conductive region 22.
For example, in one embodiment, referring to fig. 2 and 8, the method for manufacturing the array substrate 100 further includes S700, and the detailed description of step S700 is as follows.
S600: an interlayer dielectric insulating layer 50 is formed on a side of the gate layer 41 facing away from the buffer layer 10, and the interlayer dielectric insulating layer 50 covers the gate layer 41, the gate insulating layer 30 and the protective layer 42.
Optionally, the material of the interlayer dielectric insulating layer 50 includes, but is not limited to, silicon nitride, silicon oxide, etc., and the interlayer dielectric insulating layer 50 may be used to protect the gate layer 41, the semiconductor layer 20, etc. from the attack of external environmental moisture.
However, the interlayer dielectric insulating layer 50, if formed directly on the semiconductor layer 20, also affects the performance of the semiconductor layer 20, and thus, in this embodiment, the protective layer 42 can effectively protect the semiconductor layer 20 and prevent the semiconductor layer 20 from being affected by the process of preparing the interlayer dielectric insulating layer.
Referring to fig. 2 and 9, in one embodiment, S001 and S002 are further included before the buffer layer 10 is formed in S100, and the detailed descriptions of the steps S001 and S002 are as follows.
S001: forming a bearing substrate.
In this embodiment, the carrier substrate may be a flexible substrate, and optionally, the carrier substrate may be made of any one or more of the following materials: polyimide, polyethylene terephthalate (Polyethylene terephthalate, PET), polyethylene naphthalate (Polyethylene naphthalate two formic acid glycol estr, PEN), cyclic Olefin Polymer (COP), polycarbonate (PC), polystyrene (PS), polypropylene (PP), polytetrafluoroethylene (PTFE). In other implementations, the carrier substrate may be a non-flexible substrate, such as glass, ceramic, etc., which is not limited in this application.
S002: a light shielding layer 72 is formed on one side of the carrier substrate.
In the related art, the device of the array substrate is easily affected in its electrical stability by the illumination of the backlight. Therefore, in this embodiment, the light shielding layer 72 may be used to shield the semiconductor layer 20 and other devices from light to affect the transmission stability.
Referring to fig. 2 and 10, in one embodiment, the method for manufacturing the array substrate 100 further includes S800 and S900, and the detailed descriptions of the steps S800 and S900 are as follows.
S800: a second via 82 of a first via 81 is formed on the interlayer dielectric insulating layer 50, the first via 81 penetrates through the interlayer dielectric insulating layer 50 to be connected with the protective layer 42, and the second via 82 penetrates through the interlayer dielectric insulating layer 50, the gate insulating layer 30, the buffer layer 10 and the light shielding layer 72 in sequence.
S900: a conductive metal layer 60 is formed on the interlayer dielectric insulating layer 50.
Specifically, the conductive metal layer 60 includes a source layer, a drain layer, and a connection electrode 61. The source layer and the drain layer are electrically connected to the first protection region and the second protection region through the first via 81, respectively. The connection electrode 61 is connected to the light shielding layer 72 through the second via 82.
The first via 81 and the second via 82 have different depths, and thus the first via 81 and the second via 82 have different times to be formed. Specifically, the second via 82 requires a greater amount of time to erode than the first via 81. However, in the related art, the first via 81 and the second via 82 are generally manufactured using one mask, so when the first via 81 and the second via 82 are formed, the area of the first via 81 is etched first to the protection layer 42 and then is etched continuously, and the protection layer 42 can be used to protect the semiconductor layer 20, so as to avoid the semiconductor layer 20 from being etched to affect the performance thereof.
Referring to fig. 2, in an embodiment, the present application further provides an array substrate 100, where the array substrate 100 is prepared by the preparation method of the array substrate 100. The array substrate 100 includes the buffer layer 10, the semiconductor layer 20, the gate insulating layer 30, and the gate layer 41.
The semiconductor layer 20 is disposed on the buffer layer 10, and the semiconductor layer 20 includes a semiconductor region 21 and a conductive region 22. The gate insulating layer 30 is disposed on a side of the semiconductor layer 20 facing away from the buffer layer 10, and the front projection of the semiconductor layer 20 on the buffer layer 10 covers the front projection of the gate insulating layer 30 on the buffer layer 10.
The orthographic projection of the gate insulating layer 30 on the buffer layer 10 falls within the orthographic projection of the semiconductor layer 20 on the buffer layer 10, in other words, the width of the gate insulating layer 30 is smaller than the width of the semiconductor layer 20, that is, the size of the gate insulating layer 30 is smaller than the size of the semiconductor layer 20 in the first direction D1. So that a portion of the semiconductor layer 20 can be exposed with respect to the gate insulating layer 30 to facilitate a subsequent plasma treatment of the exposed semiconductor layer 20.
Specifically, in the present embodiment, both ends of the semiconductor layer 20 along the first direction D1 are exposed from the gate insulating layer 30, so as to facilitate electrical connection with the subsequent source and drain electrodes.
The gate layer 41 is disposed on a side of the gate insulating layer 30 facing away from the buffer layer 10, and an orthographic projection of the gate layer 41 on the semiconductor layer 20 falls into the semiconductor region 21.
The orthographic projection of the gate layer 41 on the semiconductor layer 20 falls into the semiconductor region 21, so as to ensure the effective length of the semiconductor channel corresponding to the gate layer 41, and avoid unstable phenomena such as TFT offset caused by insufficient effective channel length of the TFT, so as to reduce the probability of unstable operation of the array substrate 100.
The size of the gate insulating layer 30 is larger than the size of the gate layer 41, and the difference between the size of the gate insulating layer 30 and the size of the gate layer 41 ranges from 2 μm to 3 μm, in other words, one end of the gate insulating layer 30 is exposed from 1 μm to 1.5 μm compared to one end of the gate layer 41. It is possible to make the semiconductor region 21 of the semiconductor layer 20 even if the region covered by the gate insulating layer 30 is partially contaminated and conductive, and to ensure the size of the gate layer 41 in the semiconductor region 21 by the orthographic projection of the semiconductor layer 20.
Referring to fig. 2, in an embodiment, the array substrate 100 further includes a protective layer 42, the protective layer 42 is disposed on a side of the semiconductor layer 20 facing away from the buffer layer 10, the protective layer 42 is disposed at a distance from the gate layer 41, and the protective layer 42 and the gate insulating layer 30 cover the semiconductor layer 20.
The front projection of the protective layer 42 and the gate insulating layer 30 onto the buffer layer 10 covers the front projection of the semiconductor layer 20 onto the buffer layer 10, in other words, the protective layer 42 and the gate insulating layer 30 cover the semiconductor layer 20.
The protection layer 42 covers a portion of the semiconductor layer 20 where the gate insulating layer 30 is exposed, and the protection layer 42 may be used to protect the semiconductor layer 20, so as to avoid the influence of the subsequent preparation process on the material of the semiconductor layer 20, thereby effectively ensuring the performance of the semiconductor layer 20.
Referring to fig. 11, the present application further provides a display device 1, where the display device 1 includes a housing 200 and the array substrate 100, and the housing 200 is used for carrying the array substrate 100.
Optionally, the housing 200 includes, but is not limited to, plastic or other relatively rigid material to maximize the protection of the array substrate 100.
Optionally, the display device 1 includes, but is not limited to, a display screen, a mobile phone, a computer, and the like.
While the foregoing is directed to embodiments of the present application, it will be appreciated by those of ordinary skill in the art that numerous modifications and variations can be made without departing from the principles of the present application, and such modifications and variations are also considered to be within the scope of the present application.
Claims (10)
1. The preparation method of the array substrate is characterized by comprising the following steps:
forming a buffer layer;
forming a semiconductor layer on one side of the buffer layer;
forming a gate insulating layer on one side of the semiconductor layer, which is away from the buffer layer, wherein orthographic projection of the gate insulating layer on the buffer layer falls into orthographic projection of the semiconductor layer on the buffer layer;
performing plasma treatment on the semiconductor layer to convert part of the semiconductor in the semiconductor layer into a conductor, wherein the semiconductor layer after the plasma treatment comprises a semiconductor region and a conductor region;
and forming a gate layer on one side of the gate insulating layer, which is away from the buffer layer, so that orthographic projection of the gate layer on the semiconductor layer falls into the semiconductor region, wherein the gate insulating layer and the gate layer are prepared through different masks.
2. The method for manufacturing an array substrate according to claim 1, further comprising:
and forming a protective layer on one side of the semiconductor layer, which is away from the buffer layer, wherein the protective layer is arranged between the protective layer and the grid electrode layer, and the orthographic projection of the protective layer and the grid electrode insulating layer on the buffer layer covers the orthographic projection of the semiconductor layer on the buffer layer.
3. The method for manufacturing an array substrate according to claim 2, wherein the protective layer and the gate layer are manufactured through the same mask, and the protective layer is made of the same material as the gate layer.
4. The method for manufacturing an array substrate according to claim 2, further comprising, before forming the buffer layer:
forming a bearing substrate;
and forming a shading layer on one side of the bearing substrate.
5. The method for manufacturing an array substrate according to claim 4, further comprising:
forming an interlayer dielectric insulation layer on one side of the gate layer, which is away from the buffer layer, wherein the interlayer dielectric insulation layer covers the gate layer, the gate insulation layer and the protection layer;
and forming a first via hole and a second via hole on the interlayer dielectric insulating layer, wherein the first via hole penetrates through the interlayer dielectric insulating layer to be connected with the protective layer, and the second via hole penetrates through the interlayer dielectric insulating layer, the gate insulating layer, the buffer layer and the shading layer in sequence.
6. The method for manufacturing an array substrate according to claim 1, wherein the performing plasma treatment on the semiconductor layer comprises:
inert gas is used to react with the semiconductor layer.
7. The method of manufacturing an array substrate according to claim 1, wherein the material of the semiconductor layer includes at least one of indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, and indium gallium zinc tin oxide; the material of the gate layer includes at least one of titanium, aluminum, molybdenum, copper.
8. An array substrate, characterized in that the array substrate comprises:
a buffer layer;
the semiconductor layer is arranged on the buffer layer and comprises a semiconductor region and a conductor region;
the grid insulation layer is arranged on one side, away from the buffer layer, of the semiconductor layer, and orthographic projection of the semiconductor layer on the buffer layer covers orthographic projection of the grid insulation layer on the buffer layer;
the grid electrode layer is arranged on one side, away from the buffer layer, of the grid electrode insulating layer, and orthographic projection of the grid electrode layer on the semiconductor layer falls into the semiconductor region;
the protective layer is arranged on one side, away from the buffer layer, of the semiconductor layer, the protective layer is arranged at intervals with the grid electrode layer, and the semiconductor layer is covered by the protective layer and the grid electrode insulating layer.
9. The array substrate of claim 8, wherein the material of the protective layer is the same as the material of the gate layer.
10. A display device, comprising a housing and the array substrate according to any one of claims 8-9, wherein the housing is configured to carry the array substrate.
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