JP2014192420A - Semiconductor device, method of manufacturing the same, and display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parasitic capacitance between a gate electrode and a drain electrode, as well as, between the gate electrode and a source electrode, and to shorten a channel length.SOLUTION: A semiconductor device includes an insulating substrate, a gate electrode layer formed on a surface of the insulating substrate, a first insulating layer formed on the gate electrode layer, an oxide semiconductor layer which is formed on the first insulating layer and formed to stride over the gate electrode layer, a second insulation layer formed on the oxide semiconductor layer, and a drain electrode layer and a source electrode layer which are electrically connected to the oxide semiconductor layer and are arranged to face each other across the gate electrode layer when viewed from above. The second insulating layer includes exposure regions in which at least end parts in extension direction of the oxide semiconductor layer are respectively exposed. In the oxide semiconductor layer, a channel region is formed in a region between a pair of exposure regions. The drain electrode layer and the source electrode layer are connected to the oxide semiconductor layer in the exposure region, and a connection portion does not overlap with the gate electrode layer.

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and a display device using the semiconductor device, and more particularly, to a semiconductor device using an oxide semiconductor.

  In recent years, in portable information terminals called smartphones and tablet terminals, the size of the housing is limited, so in order to display more information, the resolution of display devices has rapidly increased. Yes. In a liquid crystal display device or an organic EL display device used for a portable information terminal, a switching thin film transistor is disposed for each pixel, and a display charge is rewritten to each pixel by the switching operation of the thin film transistor. It has become. On the other hand, since the display charge rewriting period for one screen is limited, when the display device is made high-definition, the time allocatable for rewriting per pixel is greatly reduced. There is a demand for higher switching speed.

  As such a thin film transistor having a high switching speed, a so-called oxide semiconductor using an oxide semiconductor layer having higher mobility than amorphous silicon or the like is known. For example, a semiconductor device having a structure shown in FIG. 11 is known. It has been. In this semiconductor device, a gate electrode layer 1102 is formed on the surface of a transparent insulating substrate 1101 such as a glass substrate, and an insulating film (gate insulating film) 1103 is formed on the upper surface so as to cover the gate electrode layer 1102. . A rectangular oxide semiconductor layer 1104 is formed over the gate electrode layer 1102 so as to overlap with the gate electrode layer 1102 with the gate insulating film 1103 interposed therebetween. A protective layer 1105 is formed on the surface of the transparent insulating substrate 1101 over the oxide semiconductor layer 1104 so as to cover the surface of the oxide semiconductor layer 1104. Through holes (contact holes) 1109 reaching the oxide semiconductor layer 1104 from the surface of the protective layer 1105 are formed at both ends of the protective layer 1105, respectively, and the drain electrode 1106 and the source electrode 1107 are formed through the through hole 1109. Are electrically connected to the contact region 1104c of the oxide semiconductor layer 1104, and the channel region 1104a is formed in the region therebetween. A protective insulating film 1108 was formed on the uppermost surface.

  However, since the drain electrode 1106 and the source electrode 1107 are formed so as to overlap with the gate electrode layer 1102 in the configuration of the conventional semiconductor device shown in FIG. There is a problem that the capacitance between the source and the capacitance between the gate and the drain increases. In particular, in the case where the parasitic capacitance of the thin film transistor is large, in order to obtain a sufficient switching speed, it is necessary to increase the amount of current flowing by forming a large channel width. However, there is a problem that the area becomes large, the amount of current accompanying switching increases, and the power consumption increases.

  As a method for solving this problem, there is a semiconductor measure and a method for manufacturing a semiconductor device described in Patent Document 1. The semiconductor device described in Patent Document 1 is configured to have a first source electrode / drain electrode and a second source electrode / drain electrode. In particular, the first source electrode / drain electrode overlaps with the gate electrode, but the parasitic capacitance between the first source electrode / drain electrode and the gate electrode is reduced by setting the film thickness to 50 nm or less. The configuration is to suppress.

JP 2011-86921 A

  However, even in the configuration of the semiconductor device described in Patent Document 1, since the first source electrode / drain electrode and the gate electrode overlap each other, there is a concern about the generation of parasitic capacitance. In the structure of the semiconductor device described in Patent Document 1, the first source electrode and the first drain electrode that are electrically connected to the high-resistance source region and the high-resistance drain region in the oxide semiconductor layer are provided. However, since it is configured to be formed in a thin film layer different from a wiring layer such as a drain line or a source line, there is a concern that the number of processes, that is, the number of processes increases, and the production efficiency decreases.

  The present invention has been made in view of these problems, and an object of the present invention is to reduce the parasitic capacitance between the gate electrode and the drain electrode and between the gate electrode and the source electrode and reduce the channel length. An object of the present invention is to provide a possible semiconductor device, a manufacturing method thereof, and a display device using the same.

(1) In order to solve the above problems, a semiconductor device according to the present invention includes an insulating substrate, a gate electrode layer formed on the surface of the insulating substrate, and a first insulating layer formed on the gate electrode layer ( Gate oxide layer), an oxide semiconductor layer formed on the first insulating layer and straddling the gate electrode layer, and a second insulation formed on the oxide semiconductor layer A semiconductor device having a layer, and a drain electrode layer and a source electrode layer that are electrically connected to the oxide semiconductor layer and arranged to face each other with the gate electrode layer in plan view,
The second insulating layer has an exposed region that exposes at least ends in the extending direction of the oxide semiconductor layer,
A channel region is formed in a region between the pair of exposed regions in the oxide semiconductor layer,
The drain electrode layer and the source electrode layer are connected to the oxide semiconductor layer in the exposed region, and the connection portion does not overlap the gate electrode layer.

(2) In order to solve the above problems, a display device according to the present invention includes a scanning signal line extending in the X direction and arranged in parallel in the Y direction and a scanning signal input thereto, and extending in the Y direction and aligned in the X direction. A thin film transistor for a pixel that is disposed near an intersection of a video signal line to which a video signal is input and the scanning signal line and the video signal line, and controls reading of the video signal in synchronization with the scanning signal A display device comprising a first substrate on which is formed,
The thin film transistor is a display device including the semiconductor device described in (1) above.

(3) In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode layer on a surface of an insulating substrate;
Forming a first insulating film covering the surface of the insulating substrate together with the gate electrode layer;
Forming an oxide semiconductor layer on the first insulating layer so as to straddle the gate electrode layer;
A second insulating layer is formed to cover the oxide semiconductor layer and to expose at least end portions of the oxide semiconductor layer in the extending direction, and to reduce the region where the oxide semiconductor layer is exposed And a process of
A step of forming the drain electrode layer and the source electrode layer that are connected to the oxide semiconductor layer in a region where the oxide semiconductor layer is exposed and in which the connection portion does not overlap the gate electrode layer; It is a manufacturing method of an apparatus.

  According to the present invention, the parasitic capacitance between the gate electrode and the drain electrode and between the gate electrode and the source electrode can be reduced. As a result, the channel length can be reduced and the size of the semiconductor device (thin film transistor) can be reduced.

  Other effects of the present invention will become apparent from the description of the entire specification.

It is a figure for demonstrating the whole structure of the semiconductor device of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is a figure for demonstrating the whole structure of the semiconductor device of Embodiment 2 of this invention. It is a figure for demonstrating the whole structure of the other semiconductor device of Embodiment 2 of this invention. It is a figure for demonstrating the pixel structure in the liquid crystal display device using the semiconductor device of this invention. It is a figure for demonstrating the pixel structure in the organic electroluminescence display using the semiconductor device of this invention. It is a figure for demonstrating the whole structure of the conventional semiconductor device.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and repeated description is omitted. Further, X, Y, and Z shown in the figure indicate an X axis, a Y axis, and a Z axis, respectively.

<Embodiment 1>
FIG. 1 is a diagram for explaining the overall configuration of a semiconductor device according to a first embodiment of the present invention. In particular, FIG. 1A is a top view of the semiconductor device according to the first embodiment, and FIG. It is sectional drawing in the AA 'line shown to Fig.1 (a). The overall configuration of the semiconductor device according to the first embodiment will be described below with reference to FIG. Note that the semiconductor structure of Embodiment 1 is formed by using a well-known photolithography technique, and thus detailed description thereof is omitted.

  The semiconductor device of Embodiment 1 shown in FIGS. 1A and 1B is an oxide semiconductor device having a bottom gate structure, and is gated with a conductive thin film material (for example, a metal thin film material such as aluminum) extending in the Y direction. An electrode layer 102 is formed. In addition, a first insulating layer (gate insulating film) 103 made of a known light-transmitting inorganic insulating film material that covers the upper surface of the insulating substrate (transparent insulating substrate) 101 is formed so as to cover the gate electrode layer 102. An oxide semiconductor layer 104 serving as a channel is formed on the upper surface. At this time, as shown in FIG. 1A, the oxide semiconductor layer 104 of Embodiment 1 is formed in a rectangular island shape extending in the X direction, and the size in the extending direction (the oxide semiconductor layer 104). Is longer than the wiring width of the gate electrode layer 102. That is, the oxide semiconductor layer 104 is formed so as to cross the gate electrode layer 102 with the gate insulating film 103 interposed therebetween, and the gate electrode layer 102 is formed so as to straddle the oxide semiconductor layer 104. Note that the oxide semiconductor layer 104 of Embodiment 1 is formed of, for example, ZnO, InGaZnO (IGZO), ZnInO, ZnSnO, or the like.

  A second insulating layer (protective film, protective layer) 105 made of a light-transmitting inorganic insulating film material is formed over the oxide semiconductor layer 104 so as to cover the top surface of the oxide semiconductor layer 104. Has been. In the portion where the protective layer 105 and the oxide semiconductor layer 104 overlap, the oxide semiconductor layer 104 is disposed on both ends in the extending direction of the oxide semiconductor layer 104, that is, on the X1 side and the X2 side of the oxide semiconductor layer 104. A through hole (opening, contact hole (through hole)) 109 that reaches the layer 104 and exposes the surface of the oxide semiconductor layer 104 is formed. That is, in the configuration of the semiconductor device of Embodiment 1, as illustrated in FIG. 1B, oxidation of a region sandwiched between a pair of through holes 109 formed in the protective layer 105 in a portion overlapping with the oxide semiconductor layer 104 is performed. The physical semiconductor layer 104 forms a channel region (channel layer) 104a having a channel length L, and the protective layer 105 formed on the upper surface of the channel region 104a functions as a channel protective layer. However, as apparent from FIG. 1B, the side wall surface of the through-hole 109 is tapered, so the channel length L is the bottom surface side (insulating substrate 101 side) of the through-hole 109, that is, a pair of through-holes. 109 is a distance between the oxide semiconductor layers 104 exposed from 109.

  In particular, in the configuration of the first embodiment, the through hole 109 is formed by well-known dry etching such as plasma etching, for example. By forming the through-hole 109 by this dry etching, for example, when the through-hole 109 is formed by wet etching using an IGZO film in the oxide semiconductor layer 104 using an acid-based etching solution, a protection made of an inorganic insulating film material is used. This is because the oxide semiconductor layer 104 can be easily prevented from being etched together with the layer 105. However, in the case where the oxide semiconductor layer 104 having resistance to an etching solution is used, the through hole 109 may be formed by wet etching. Further, irradiation with plasma or the like associated with dry etching for forming the through hole 109 reduces the resistance of the oxide semiconductor layer 104 where the surface of the oxide semiconductor layer 104 is exposed due to the formation of the through hole 109. Thus, a low resistance region to be a contact region (contact layer) 104c can be formed. That is, when the exposed oxide semiconductor layer 104 is struck by dry etching, the exposed region is subjected to reduction treatment, and the resistance of this region is reduced.

  At this time, a portion close to the channel region 104a in the region where the through hole 109 is formed is formed so as to overlap with the gate electrode layer 102 in a plan view. On the other hand, the portion far from the channel region 104 a does not overlap with the gate electrode layer 102 in a plan view, that is, the lower layer has a structure in which the gate insulating film 103 is directly laminated on the upper surface of the transparent insulating substrate 101. Therefore, in the structure of Embodiment 1, in the low resistance region formed in the oxide semiconductor layer 104, the drain electrode layer is formed in a region that does not overlap with the gate electrode layer 102, that is, a portion far from (distant from) the channel region 104a. 106 and the end portions of the source electrode layer 107 are connected. In particular, when the intervals between the drain electrode layer 106 and the source electrode layer 107 and the gate electrode layer 102 are R1 and R2, respectively, the intervals R1 and R2 are set in advance as values larger than the misalignment amount. The drain electrode layer 106 and the source electrode layer 107 are not overlapped with the gate electrode layer 102. Also in the formation of the drain electrode layer 106 and the source electrode layer 107, a region where the drain electrode layer 106 and the source electrode layer 107 are not formed in the region exposed from the through hole 109 by forming by well-known dry etching. The portion other than the contact region 104c is further irradiated with plasma resulting from dry etching to reduce the resistance, thereby forming the low resistance region 104b. However, if the resistance of the oxide semiconductor layer 104 has reached the limit of resistance reduction due to the formation of the through hole 109, the oxide accompanying the formation of the drain electrode layer 106 and the source electrode layer 107 The resistance of the semiconductor layer 104 is not further reduced.

  That is, in the structure of the present invention, regions of the oxide semiconductor layer 104 that overlap with the through-hole 109 become the low resistance region 104b and the contact region 104c, and function as the drain electrode and the source electrode in the semiconductor device of the present invention. It is configured. As a result, a region between the pair of through holes 109 formed in the protective layer 105 in a portion overlapping with the oxide semiconductor layer 104 becomes a channel region (channel layer) 104a, and the distance between the pair of through holes 109 is L. In this case, a channel region 104a having a channel length L is formed. However, as described above, a region where the drain electrode layer 106 and the source electrode layer 107 are connected to the oxide semiconductor layer 104 (ohmic contact) in the oxide semiconductor layer 104 exposed from the through hole 109 is a contact region. (Contact layer) 104c.

  The upper layer of the drain electrode layer 106 and the source electrode layer 107 is formed of a light-transmitting inorganic insulating film material so as to cover the upper surface of the insulating substrate 101 as well as the upper surfaces of the drain electrode layer 106 and the source electrode layer 107. A third insulating layer (protective insulating film) 108 is formed.

(Production method)
Next, FIGS. 2 to 6 are views for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention, and will be described in detail below. However, as in FIG. 1, FIGS. 2 (a) to 6 (a) are plan views corresponding to FIG. 1 (a), and FIGS. 2 (b) to 6 (b) are FIGS. It is sectional drawing corresponding to.

a) Step of forming gate electrode layer (FIG. 2)
First, for example, after forming a metal thin film on the surface of the transparent insulating substrate 101 made of a well-known glass substrate, the metal thin film is etched by well-known photolithography to form the gate electrode layer 102 extending in the Y direction. At this time, the gate electrode layer 102 includes, for example, the well-known Mo (molybdenum), Cr (chromium), W (tungsten), Al (aluminum), Cu (copper), Ti (titanium), Ni (nickel), Ta ( Tantalum), Ag (silver), or other metal single films, alloy films thereof, or laminated films thereof. Although not shown, an inorganic transparent insulating film (so-called base film) such as a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), or a laminated film thereof is formed under the gate electrode layer 102. A film may be formed.

b) Step of forming a gate insulating film (first insulating layer) (FIG. 3)
A gate insulating film 103 is formed so as to cover the gate electrode layer 102. That is, the gate insulating film 103 is formed on the upper surface of the insulating substrate 101 so as to cover the surface of the gate electrode layer 102. At this time, the gate insulating film 103 is formed of a known silicon oxide film, silicon nitride film, inorganic transparent insulating film such as Al ₂ O ₃ (aluminum oxide), or a laminated film thereof.

c) Oxide semiconductor layer formation step (FIG. 4)
After the oxide semiconductor layer 104 is formed over the gate insulating film 103, a pattern is formed by photolithography. At this time, both ends of the oxide semiconductor layer 104 are patterned so as to cover the gate electrode layer 102.

  That is, an oxide extending in the X direction intersects with the gate insulating film 103 formed in the lower layer and extends in the Y direction so that the oxide semiconductor layer 104 straddles the gate electrode layer 102 via the gate insulating film 103. The physical semiconductor layer 104 is formed. At this time, in the formation of the oxide semiconductor layer 104 of Embodiment 1, both ends in the extending direction (X direction) are formed to be larger than the width of the gate electrode layer 102 (X direction width), and are formed in a process described later. The side edge portions of the oxide semiconductor layer 104 are formed so as to extend outward (X1 side and X2 side) from the outer side edge portions of the pair of through holes 109 formed. With this configuration, it is possible to prevent poor electrical connection between the drain electrode layer 106 and the source electrode layer 107, which will be described later, due to alignment accuracy when the oxide semiconductor layer 104 and the through hole 109 are formed. It becomes.

d) Step of forming channel protective layer (FIG. 5)
An inorganic insulating film such as a silicon oxide film, a silicon nitride film, Al ₂ O _3, or a stacked film thereof is formed over the oxide semiconductor layer 104, and an opening (through-hole) is formed so as to reach the end of the gate electrode layer 102. 109). By forming the through-hole 109 by dry etching, the oxide semiconductor layer 104 in a region overlapping with the through-hole 109 has a reduced resistance and functions as a source / drain electrode.

  That is, first, the protective layer 105 made of an inorganic insulating film material is formed so as to cover the oxide semiconductor layer 104 on the upper surface of the transparent insulating substrate 101. Next, a pair of through holes 109 reaching the oxide semiconductor layer 104 are formed at positions overlapping with the oxide semiconductor layer 104 by known dry etching. At this time, in the through hole 109 of the first embodiment, the pair of through holes 109 are opposed to each other through the gate electrode layer 102 in a plan view, and each of the pair of through holes 109 has the through holes 109. A part, that is, a part on the side where the pair of through-holes face each other is formed so as to overlap with the gate electrode layer 102.

  By the formation process of the through hole 109, a region 104d in which the resistance of the portion of the oxide semiconductor layer 104 in the region exposed from each through hole 109 is formed is formed. At this time, one of the regions 104d (the left region 104d in the drawing) serves as a drain electrode (drain region), and the other (the right region 104d in the drawing) serves as a source electrode (source region). A channel region 104 a is formed in a region between the pair of through holes 109 in the semiconductor layer 104. Of the protective layer 105 formed so as to cover the insulating substrate 101, the protective layer 105 in the region formed on the upper surface of the channel region 104a functions as a channel protective layer (channel protective film).

  Thus, since the distance in the X direction between the pair of through-holes 109 becomes the channel length L, the formation accuracy of the channel length L can be improved to the etching accuracy without being affected by the alignment accuracy of each thin film layer. Can do. Furthermore, since the Y-direction width of the pair of through holes 109 is the channel width, the channel width formation accuracy is etched without being affected by the alignment accuracy of each thin film layer as well as the channel length. The accuracy can be improved.

e) Step of forming drain electrode layer and source electrode layer (FIG. 6)
First, a metal thin film to be a source / drain electrode layer is formed, and then the formed metal thin film is dry-etched so as to be separated in each of the openings, thereby performing drain electrode layer 106 and source electrode layer 107. To process. The metal thin film material used as the source / drain electrode is, for example, a well-known Mo, Cr, W, Al, Cu, Ti, Ni, Ta, Ag, or other metal single film, an alloy film thereof, or a laminated film thereof. Consists of. In addition, although the dry etching mentioned above is preferable for a process, it is not limited to this.

  That is, as shown in FIG. 6A, the drain electrode layer 106 and the source electrode layer 107 are formed so as to face each other with the gate electrode layer 102 interposed therebetween in plan view. The side edge portions on the gate electrode layer 102 side of 106 and the source electrode layer 107 are formed to be separated from the side edge portions of the gate electrode layer 102 by a predetermined distance. Further, as is apparent from FIGS. 6A and 6B, the side end portions on the gate electrode layer 102 side of the drain electrode layer 106 and the source electrode layer 107 are arranged inside the opening end of the through hole 109. The In other words, the drain electrode layer 106 and the source electrode layer 107 are arranged so that the edge portions on the gate electrode layer 102 side overlap with the through hole 109.

  With this configuration, as illustrated in FIG. 6B, the end portions of the drain electrode layer 106 and the source electrode layer 107 are connected to the surface of the oxide semiconductor layer 104 exposed from the through hole 109. At this time, in the configuration of the oxide semiconductor layer 104 of Embodiment 1, the region exposed from the through hole 109 is the region 104d with reduced resistance, and thus the end of the drain electrode layer 106 and the source electrode layer 107 is formed. A region where the portion and the exposed surface of the oxide semiconductor layer 104 are in contact with each other is a contact region 104c. On the other hand, a region between the channel region 104a and the contact region 104c in the oxide semiconductor layer 104 is further etched by dry etching for forming the drain electrode layer 106 and the source electrode layer 107 by etching the metal thin film. The resistance is reduced to become the low resistance region 104b.

f) Step of forming the protective insulating film (FIG. 1)
By forming an inorganic insulating film such as a silicon oxide film, a silicon nitride film, Al ₂ O _3, or a laminated film thereof as the protective insulating film 108, the semiconductor according to the first embodiment shown in FIGS. A device is formed. Further, although not shown in the semiconductor device of Embodiment 1 shown in FIGS. 1A and 1B, after forming a through hole, a well-known transparent conductive film, flattening film, or the like is formed for a liquid crystal display. Thus, a transparent substrate (TFT substrate, first substrate) on which the thin film transistor is formed, that is, a back plane is completed.

  As described above, in the semiconductor device of Embodiment 1, the oxide semiconductor layer is formed so as to straddle the gate electrode layer via the gate insulating film formed in the upper layer of the gate electrode layer. A protective layer is formed over the layer so as to cover the front surface including the surface of the semiconductor layer, and a pair of layers reaching the surface of the oxide semiconductor layer with the gate electrode layer sandwiched between the protective layers when viewed in plan Through-holes are formed, a part of each through-hole is arranged so as to overlap with the gate electrode layer, the pair of through-holes are formed by dry etching, and the oxide semiconductor in the region where the through-holes are formed A low resistance region is formed in the layer, the gate electrode layer side of each low resistance region and the gate electrode layer are overlapped, and a channel region is formed between the two low resistance regions.

  That is, in each low resistance region, the drain electrode layer and the source electrode layer are formed in the edge portion facing the edge portion overlapping with the gate electrode layer, so that the gate electrode layer and the drain electrode layer or source electrode layer Can be prevented from overlapping with each other through the insulating film. As a result, the parasitic capacitance between the gate electrode layer and the drain electrode layer and the parasitic capacitance between the gate electrode layer and the source electrode layer can be reduced, so that power consumption can be greatly reduced. .

  In the semiconductor device of Embodiment 1, since the drain electrode region and the source electrode region are formed in the oxide semiconductor layer when the through hole is formed, the alignment accuracy is improved when each thin film layer is formed. The channel region can be formed without dependence. That is, since the protective layer between the pair of through-holes 109 formed in the same process becomes a channel protective film, the channel region and the channel protective film considering the alignment accuracy associated with the formation of the channel region and the channel protective film Therefore, the channel length L can be reduced. As a result, the semiconductor device can be reduced in size.

  Further, in the structure of Embodiment 1, the through hole 109 is formed in a region where the protective layer 105 and the oxide semiconductor layer 104 overlap with each other, and thus a signal line extending or connected from the gate electrode layer 102 is used. In addition, it is possible to obtain a special effect that parasitic capacitance can be reduced when signal lines extending or connected from the drain electrode layer 106 and the source electrode layer 107 intersect outside the thin film transistor formation region.

  In the first embodiment, the case where the semiconductor device is formed on the surface of the transparent insulating substrate (TFT substrate) on the liquid crystal side has been described. However, the semiconductor device is formed on the surface of the light-blocking insulating substrate that does not transmit light. It can also be applied to semiconductor devices. In this case, each insulating film made of an inorganic insulating film material may be formed of an inorganic insulating film material that does not have translucency.

  In the semiconductor device of the first embodiment, the case where the outer shape of the through hole 109 is formed in a square shape has been described. However, the outer shape of the through hole 109 is appropriately rectangular according to the channel length L and the channel width. It may be configured to.

  Further, in the structure of Embodiment 1, the through hole 109 is formed in a region where the protective layer 105 and the oxide semiconductor layer 104 overlap with each other; however, the present invention is not limited to this. For example, the protective layer 105 may be formed as a channel protective layer only on the upper surface of the channel region 104a. However, also in this configuration, the intervals between the drain electrode layer 106, the source electrode layer 107, and the gate electrode layer 102 are defined as intervals R1 and R2, respectively. Note that in this structure, when the protective layer 105 serving as a channel protective layer is formed, the surface of the gate insulating film 103 is also partially etched, so that, for example, the drain electrode layer 106 or the source electrode layer 107 Even in a region intersecting with the gate electrode layer 102, there is a concern that the interval in the film thickness direction (Z direction) may be reduced, and thus a through hole 109 is formed in the protective layer 105 covering the surface of the transparent insulating substrate 101. The above-described configuration is preferable.

  Furthermore, in the first embodiment, the case where the through hole 109 is formed by dry etching has been described. However, the present invention is not limited to this. For example, even when the through-hole 109 is formed by wet etching, the drain electrode layer 106 and the source electrode are viewed in plan view by forming at least a contact region 104c described later by plasma irradiation or the like. The layer 107 and the gate electrode layer 102 can be prevented from overlapping each other. Therefore, parasitic capacitance between the drain electrode layer 106 and the gate electrode layer 102 and between the source electrode layer 107 and the gate electrode layer 102 can be significantly reduced.

<Embodiment 2>
FIG. 7 is a diagram for explaining the overall configuration of the semiconductor device according to the second embodiment of the present invention. In particular, FIG. 7A is a top view of the semiconductor device according to the second embodiment, and FIG. It is sectional drawing in the BB 'line shown to Fig.7 (a). Hereinafter, the overall configuration of the semiconductor device of the first embodiment will be described with reference to FIGS. However, the semiconductor device of Embodiment 2 is the same as Embodiment 1 except for the configuration of the drain electrode layer 201 and the source electrode layer 202. Therefore, in the following description, the drain electrode layer 201 and the source electrode layer 202 will be described in detail.

  As is clear from FIG. 7A, the drain electrode layer 201 and the source electrode layer 202 of Embodiment 2 have a size in the Y direction of the drain electrode layer 701 and the source electrode layer 702, that is, the electrode layer width of the through-hole 109. It is formed smaller than the opening width in the Y direction. Furthermore, opposite sides of the drain electrode layer 701 and the source electrode layer 702, that is, side edges near the gate electrode layer 102 are provided in the opening of the through hole 109. In this case, each thin film layer forming the drain electrode layer 701 and the source electrode layer 702 has a side edge portion close to the gate electrode layer 102 and a part of two side portions intersecting with the side edge portion is also a through hole. 109 is provided in the opening. That is, the two corners of the drain electrode layer 701 and the source electrode layer 702 are arranged in the opening of the through hole 109.

  At this time, in the semiconductor device of the present invention, as described above, the channel region 104a is formed by the low resistance region 104b of the oxide semiconductor layer 104 whose surface is exposed from the through hole 109. Even in the configuration of 2, the channel length L and the channel width are the same as those in the first embodiment. Also in the semiconductor device of Embodiment 2, the distances between the drain electrode layer 701 and the source electrode layer 702 and the gate electrode layer 102 are R1 and R2, respectively. Furthermore, the drain electrode layer 701 and the source electrode layer 702 and the gate are separated. The electrode layer 102 is not overlapped. Therefore, also in the configuration of the semiconductor device of the second embodiment, the same effect as that of the first embodiment can be obtained.

  Furthermore, in the semiconductor device of Embodiment 2, the drain electrode layer 701 and the source electrode layer 702 are configured so that the width of the drain electrode layer 701 and the source electrode layer 702 is smaller than the opening width of the through hole 109. The exceptional effect that the width can be reduced and the size of the semiconductor device can be further reduced can be obtained.

  In addition, although the arrangement position of the drain electrode layer 701 and the source electrode layer 702 in Embodiment 2 is arranged in the center of the through hole 109 in the Y direction, the present invention is not limited to this. It may be arranged close to the Y1 side or Y2 side of the opening.

  In the semiconductor device of the second embodiment, the drain electrode layer 701 and the source electrode layer 702 have a width smaller than the opening width of the through hole 109. Therefore, in comparison with the configuration of the semiconductor device of Embodiment 1, the photomask for forming the through-hole 109 and the photomask for forming the drain electrode layer 701 and the source electrode layer 702 in the Y direction. It is conceivable that it is easily affected by the positioning accuracy. For example, as shown in FIG. 8A, it is conceivable that part of the drain electrode layer 701 and the source electrode layer 702 are formed outside the opening of the through hole 109.

  However, also in the semiconductor device of the second embodiment, as described above, the configuration of the channel region 104a is the same as that of the channel region 104a in the semiconductor device of the first embodiment. That is, also in the oxide semiconductor layer 104 of Embodiment 2, the channel length L is determined by the distance between the pair of through holes 109 and the channel width is determined by the opening width of the through holes 109 in the Y direction. Will be.

Therefore, as shown in FIG. 8A, the alignment of the photomask for forming the through-hole 109 and the photomask for forming the drain electrode layer 701 and the source electrode layer 702, for example, the drain electrode layer Even when the 701 and the source electrode layer 702 are formed so as to be shifted in the Y2 direction, the drain electrode region formed in the oxide semiconductor layer 104 and The source electrode region is electrically connected to the drain electrode layer 701 and the source electrode layer 702. (In a photo process for forming an etching mask when forming the drain electrode layer 701 and the source electrode layer 702, misalignment occurred and the formation positions of the drain electrode layer 701 and the source electrode layer 702 were shifted. Even if it is a case, it is an example showing that no problem occurs as a semiconductor device.)
In particular, in the configuration illustrated in FIG. 8A, each thin film layer that forms the drain electrode layer 701 and the source electrode layer 702 has a side portion close to the gate electrode layer 102 and a portion of the side portion in accordance with the occurrence of the shift. A part of one of the two sides that intersect with the end is also provided in the opening of the through hole 109. That is, one corner is disposed in the opening of the through hole 109 in each corner of the drain electrode layer 701 and the source electrode layer 702. However, a partial region on one end side of the drain electrode layer 701 and the source electrode layer 702 extends into the opening of the through hole 109, and a corner region of the drain electrode layer 701 and the source electrode layer 702 is a corner portion of the through hole 109. It becomes the structure arrange | positioned in an area | region.

  Accordingly, as shown in FIG. 8A, even when the formation regions of the drain electrode layer 701 and the source electrode layer 702 are shifted, the sectional view taken along the line CC ′ shown in FIG. As can be seen, the channel region 104a, the low resistance region 104b, and the contact region 104c have the same configuration as that of the semiconductor device shown in FIGS. it can.

<Embodiment 3>
FIG. 9 is a diagram for explaining a pixel configuration in a liquid crystal display device using the semiconductor device of the present invention. In particular, FIG. 9A shows the semiconductor device (thin film transistor) of the present invention shown in Embodiment 1 in each pixel. FIG. 9B is a cross-sectional view taken along the line DD ′ shown in FIG. 9A. However, the liquid crystal display device of Embodiment 3 shows a case where the semiconductor device of the present invention is applied to an IPS (In Plane Switching) type liquid crystal display device.

  In the liquid crystal display device according to the third embodiment, the configuration other than the thin film transistor (semiconductor device) is the same as that of a known liquid crystal display device. Accordingly, in the following description, the transparent insulating substrate (TFT substrate, first substrate) on the side where the thin film transistor for switching is formed among the pair of transparent insulating substrates (glass substrates) arranged to face each other through the liquid crystal layer. The transparent insulating substrate (CF substrate, second substrate) and the backlight device on the side where the color filter and the like are arranged will be omitted. Further, the present invention can also be applied to other types of liquid crystal display devices such as a TN mode and a VA mode.

  As shown in FIG. 9A, video signal lines (drain lines) 901 extending in the Y direction and juxtaposed in the X direction, and scanning signal lines extending in the X direction and juxtaposed in the Y direction ( A region of a pixel is formed in a region surrounded by a gate line 902, and the pixel region is arranged in a matrix in the X direction and the Y direction. In each pixel, the semiconductor device (thin film transistor) of the present invention is formed near the intersection of the drain line 901 and the gate line 902. The thin film transistor is driven ON / OFF in synchronization with the scanning signal input from the gate line 902, and a video signal output to the drain line 901 is read into the pixel electrode 903 while the thin film transistor is ON.

  In the structure of the thin film transistor included in the liquid crystal display device of Embodiment 3, the oxide semiconductor layer 104 is formed so as to cross the gate line 902 extending in the X direction and straddle the gate line 902 in the Y direction. The gate line 902 in the intersecting region forms the gate electrode layer 102. At this time, as apparent from FIGS. 9A and 9B, the protective layer 105 is dry-etched so that it overlaps in the formation region of the oxide semiconductor layer 104 and part of the oxide semiconductor layer 104 also overlaps with the gate line 902. A pair of through holes 109 are formed above and below the gate line 902 in the drawing. As a result, in the thin film transistor of Embodiment 3, as in Embodiment 1, a low resistance region is formed in the oxide semiconductor layer 104 in the region where each through hole 109 is formed.

  In the configuration of the third embodiment, as shown in FIG. 9A, a lead portion 905 extending in the X direction is formed from the drain line 901 extending in the Y direction, and the lead portion 905 is the lower side in the figure. It is the structure which overlaps with a part of through-hole 109 of this. Further, as is apparent from FIG. 9A, the lead-out portion 905 and the gate line 902 are separated from each other at a predetermined interval and extend in the X direction. With this configuration, as illustrated in FIG. 9B, the lead portion 905 is connected to a low-resistance region (contact region 104 c) serving as a drain region in the oxide semiconductor layer 104, and the drain of the thin film transistor of Embodiment 3 An electrode layer is formed.

  On the other hand, of the pair of through-holes 109, a connection portion 906 made of a rectangular metal thin film in the same layer as the video signal line 901 is formed in the upper through-hole 109 in FIG. The portion 906 is configured to overlap a part of the upper through-hole 109 in the drawing. At this time, the connection portion 906 and the gate line 902 are separated from each other at a predetermined interval, and the connection portion 906 does not overlap with the gate line 902. With this configuration, as illustrated in FIG. 9B, the connection portion 906 is connected to the low-resistance region (contact region 104 c) serving as the source region in the oxide semiconductor layer 104, and the source of the thin film transistor of Embodiment 3 An electrode layer is formed. The connection portion 906 is electrically connected to a pixel electrode 903 formed on the upper surface of the protective insulating film 108 through a through-hole 904 formed in the protective insulating film 108, and a common reference voltage (not shown) is supplied. An electric field parallel to the in-plane direction of the transparent insulating substrate 101 is generated between the electrodes and liquid crystal molecules (not shown) are driven.

  Also in the liquid crystal display device having this configuration, a thin film transistor having a small channel length L can be formed, and an area occupied by the thin film transistor in the pixel region can be reduced. That is, in the conventional thin film transistor in which the drain electrode layer and the source electrode layer are formed so as to cover the through hole, a distance that is three times the alignment accuracy when forming each thin film layer between the pair of through holes is required. there were. On the other hand, in the thin film transistor of the present invention, the distance between the pair of through holes 109 can be reduced to the extent that the minimum processing dimension is added to the driving capability required for the thin film transistor. Therefore, the transmittance of the liquid crystal display device can be improved, and the display performance can be improved. In addition, since power consumption of the thin film transistor due to parasitic capacitance can be reduced, power consumption in the liquid crystal display device can be reduced.

  In the liquid crystal display device of the third embodiment, the case where the semiconductor device of the present invention is applied to the thin film transistor formed in each pixel has been described, but the present invention is not limited to this. For example, the present invention can be applied to a driving circuit such as a known video signal generation circuit that generates a video signal or a known scanning signal generation circuit that generates a scanning signal. In this case, the driving circuit is formed in the peripheral portion (frame region) of the display area of the liquid crystal display device, but each thin film transistor constituting the driving circuit can be formed small, and the area of the entire driving circuit can be reduced. As a result, the frame area can be further reduced, and a special effect that a further framed frame can be obtained can be obtained.

<Embodiment 4>
FIG. 10 is a diagram for explaining a pixel configuration in an organic EL display device using the semiconductor device of the present invention. In particular, FIG. 10A shows the semiconductor device (thin film transistor) of the present invention shown in Embodiment 1 in each case. It is a top view at the time of using as a switching element arrange | positioned in a pixel, FIG.10 (b) is sectional drawing in the EE 'line shown to Fig.10 (a). However, the organic EL display device of Embodiment 4 shows a case where the semiconductor device of the present invention is applied to a liquid crystal display device having a top emission structure.

  As shown in FIG. 10B, also in the semiconductor device of Embodiment 4, the oxide semiconductor layer 104 is formed so as to straddle the scanning signal line 1002, similarly to the semiconductor device of Embodiment 3 described above. . In addition, a pair of through-holes 109 are formed in the protective layer 105 by dry etching so that the oxide semiconductor layer 104 overlaps with a region where the oxide semiconductor layer 104 is formed and a part of the scan signal line 1002 also overlaps. ing.

  Furthermore, a lead-out portion 1005 extending in the X direction (extending direction of the scanning signal line 1002) from the video signal line 1001 to which the video signal is supplied is provided in one through hole 109 (the lower through hole in FIG. 10A). 109). Accordingly, the lead portion 1005 is connected to the low resistance region that becomes the contact layer 104c of the oxide semiconductor layer 104 through the edge portion of the through hole 109 to become a drain electrode, and the lead portion 1005 is connected to the scanning signal line 1002. The structure does not overlap with the (gate electrode layer 102).

  On the other hand, in the other through hole 109 (the upper through hole 109 in FIG. 10A), as in the third embodiment, a connecting portion 1006 made of a metal thin film is overlapped with a part of the other through hole 109. Is formed. Accordingly, one edge portion of the connection portion 1006 is connected to the low resistance region that becomes the contact layer 104c of the oxide semiconductor layer 104 via the edge portion of the other through-hole 109, and becomes a source electrode. The connection portion 1006 does not overlap with the scanning signal line 1002 (gate electrode layer 102).

  Further, a planarizing film 1007 made of, for example, a well-known organic insulating film material is formed on the upper surface of the protective insulating film 108, and the protective insulating film 108 and the planarizing film 1007 in a region overlapping with the connection portion 1006 are formed on the upper surface of the protective insulating film 108. A through hole 1004 reaching the connection part 1006 is formed, and the surface of the connection part 1006 is exposed from the through hole 1004. A reflective layer 1003 having conductivity is formed so as to cover the through hole 1004 and the exposed connection portion 1006, and the reflection layer 1003 is electrically connected to the connection portion 1006.

  As described above, the configuration of the thin film transistor (semiconductor device) of the organic EL display device of Embodiment 4 has the same configuration as that of the thin film transistor of Embodiment 3 described above. It becomes possible to further reduce the size, and it is possible to obtain a special effect that further high definition can be achieved.

  Further, when applied to a bottom emission type organic EL display device, it is possible to improve the extraction efficiency of light emitted from the organic EL layer.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment of the invention, and various modifications can be made without departing from the scope of the invention. It can be changed.

101, 1101 ... Insulating substrate, 102, 1102 ... Gate electrode layer 103, 1103 ... Gate insulating film, 104, 1104 ... Oxide semiconductor layer 104a, 1104a ... Channel region, 104b ... Low resistance region 104c, 1104c ... Contact region, 105,1105 ... Protective layer 106,701,1106 ... Drain electrode layer 107,702,1107 ... Source electrode layer, 108,1108 ... Protective insulating film 109,904 ... Through hole 901 , 1001... Video signal lines 902 and 1002... Scanning signal lines 903... Pixel electrodes 905 and 1005.

Claims (11)

An insulating substrate; a gate electrode layer formed on a surface of the insulating substrate; a first insulating layer formed on the gate electrode layer; and the gate electrode formed on the first insulating layer. An oxide semiconductor layer formed so as to straddle the layer, a second insulating layer formed on the oxide semiconductor layer, and electrically connected to the oxide semiconductor layer. A semiconductor device having a drain electrode layer and a source electrode layer arranged to face each other via a gate electrode layer,
The second insulating layer has an exposed region that exposes at least ends in the extending direction of the oxide semiconductor layer,
A channel region is formed in a region between the pair of exposed regions in the oxide semiconductor layer,
The drain electrode layer and the source electrode layer are connected to the oxide semiconductor layer in the exposed region, and the connection portion does not overlap the gate electrode layer.   The space between the exposed regions is formed to be smaller than the width of the gate electrode layer, and the exposed region is formed so that a part of the exposed region overlaps the gate electrode layer in plan view. 2. The semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the exposed region is subjected to a reduction process. The second insulating layer is formed so as to cover the insulating substrate;
The exposed region is a region exposed from a pair of through holes reaching the surface of the oxide semiconductor layer formed in the second insulating layer in a region overlapping with the oxide semiconductor layer,
As viewed in a plan view, the side portions on the near side of the pair of through holes are each formed in a region overlapping the gate electrode layer, and the side portion on the far side is formed in a region not overlapping the gate electrode layer. The semiconductor device according to claim 3.   The pair of through holes are formed by dry-etching the second insulating layer, and the oxide semiconductor layer in a region overlapping with the pair of through-holes is reduced by the dry etching, so that the oxidation 5. The semiconductor device according to claim 4, wherein a region between exposed regions exposed from the pair of through holes in the physical semiconductor layer serves as the channel region.   The drain electrode layer and the source electrode layer are respectively formed on the surface of the second insulating layer, and the drain electrode layer and the source electrode layer are exposed from the through hole. 6. The semiconductor device according to claim 5, wherein the semiconductor device is electrically connected to the oxide semiconductor layer so as to cover a part of a region which does not overlap with the gate electrode layer in a plan view.   A region where the drain electrode layer and the source electrode layer are electrically connected to the oxide semiconductor layer is a contact region, and a low resistance region is formed between the contact region and the channel region. The semiconductor device according to claim 6.   The semiconductor device according to claim 4, wherein a width of the drain electrode layer and / or the source electrode layer is larger than a width of the through hole.   8. The semiconductor device according to claim 7, wherein a width of the drain electrode layer and the source electrode layer is formed smaller than the width of the through hole, and the low resistance region is formed in a C shape. A scanning signal line extending in the X direction and arranged in parallel in the Y direction and receiving a scanning signal, a video signal line extending in the Y direction and arranged in parallel in the X direction and receiving a video signal, and the scanning signal line And a display device including a first substrate on which a thin film transistor for a pixel that is disposed in the vicinity of an intersection of the video signal line and controls reading of the video signal in synchronization with the scanning signal is formed,
A display device, wherein the thin film transistor comprises the semiconductor device according to claim 1. Forming a gate electrode layer on the surface of the insulating substrate;
Forming a first insulating film covering the surface of the insulating substrate together with the gate electrode layer;
Forming an oxide semiconductor layer on the first insulating layer so as to straddle the gate electrode layer;
A second insulating layer is formed to cover the oxide semiconductor layer and to expose at least end portions of the oxide semiconductor layer in the extending direction, and to reduce the region where the oxide semiconductor layer is exposed And a process of
Forming the drain electrode layer and the source electrode layer that are connected to the oxide semiconductor layer in a region where the oxide semiconductor layer is exposed and the connection portion does not overlap the gate electrode layer. A method of manufacturing a semiconductor device.

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