CN101409308A - Thin-film transistor, pixel structure and manufacturing method thereof - Google Patents
Thin-film transistor, pixel structure and manufacturing method thereof Download PDFInfo
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- CN101409308A CN101409308A CNA2007101620266A CN200710162026A CN101409308A CN 101409308 A CN101409308 A CN 101409308A CN A2007101620266 A CNA2007101620266 A CN A2007101620266A CN 200710162026 A CN200710162026 A CN 200710162026A CN 101409308 A CN101409308 A CN 101409308A
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- layer
- film transistor
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- semiconductor layer
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Abstract
The invention relates to a thin film transistor which comprises a gate electrode, a gate insulation layer, a doped semiconductor layer, a channel layer, a source electrode and a drain electrode; wherein, the gate electrode is arranged on a substrate, while the gate insulation layer is arranged on the substrate and covers the gate electrode. The doped semiconductor layer is arranged on the gate insulation layer above the gate electrode. Furthermore, the channel layer is arranged on the doped semiconductor layer. The source electrode and the drain electrode are respectively arranged on two sides of the channel layer. The thin film transistor has lower drain current in an off state.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof, and particularly relevant for a kind of thin-film transistor, dot structure and manufacture method.
Background technology
In recent years, because the manufacture of semiconductor development of technology, the manufacturing of thin-film transistor gets over easily, quick.Being widely used of thin-film transistor, for example computer chip, chip for cell phone or Thin Film Transistor-LCD (thin film transistor liquid crystal displayer, TFT LCD) etc.With the Thin Film Transistor-LCD is example, and thin-film transistor can be used as the switch of charge or discharge.
Figure 1A is the structural profile schematic diagram of existing thin-film transistor.Existing thin-film transistor 100 comprises a glass substrate 110, a grid 120, a gate insulation layer 130, an amorphous silicon layer 140, a N type doped amorphous silicon layer 150, one source pole 160 and a drain electrode 170.Wherein, grid 120 is formed on the glass substrate 110, and the material of grid 120 is a low resistance material.In addition, gate insulation layer 130 cover grid 120 and glass substrate 110 partly.In addition, amorphous silicon layer 140 is formed on the gate insulation layer 130, so that the raceway groove of electric transmission to be provided.Above-mentioned N type doped amorphous silicon layer 150 (ohmic contact layer) covers on the amorphous silicon layer 140 of part, with reduce source electrode 160 and amorphous silicon layer 140 and drain 170 and amorphous silicon layer 140 between impedance.By Figure 1A as can be known, source electrode 160 all is disposed on the N type doped amorphous silicon layer 150 with drain electrode 170.
When the grid 120 of thin-film transistor 100 applies a positive gate voltage Vg, can form electron channel in the amorphous silicon layer 140.On the other hand, put on the data voltage of source electrode 160, will flow to drain electrode 170 by electron channel in the mode of electric current, and this electric current can and increase along with grid voltage Vg rising.When stopping to apply a voltage to grid 120, the electron channel in the amorphous silicon layer 140 just can disappear.In other words, source electrode 160 and drain electrode are between 170 and open circuit.
Figure 1B is the current-voltage curve (I-V Curve) of existing thin-film transistor.Please refer to Figure 1B, it should be noted that when the grid voltage that puts on grid 120 was negative voltage, the electric current in the raceway groove also can be followed the rising of negative voltage and increase.Because existing thin-film transistor 100 when grid 120 applies negative voltage, still has electric current and flows through amorphous silicon layer 140 and form leakage current.Shown in Figure 1B, when grid voltage was-10 volts, the leakage current that source electrode 160 and drain electrode are 170 was about 6.00 * 10
-12Milliampere.
Summary of the invention
In view of this, the present invention proposes a kind of thin-film transistor, and it has lower leakage current when closed condition.
The present invention proposes a kind of method of manufacturing thin film transistor, and it can produce element characteristic good film transistor.
The present invention proposes a kind of dot structure, and it has element characteristic good film transistor of the present invention.
The present invention proposes a kind of one pixel structure process method, and it can effectively produce dot structure of the present invention.
The present invention proposes a kind of thin-film transistor, and it is suitable for being configured on the substrate.Thin-film transistor of the present invention comprises a grid, a gate insulation layer, a doping semiconductor layer, a channel layer and one source pole and a drain electrode.Wherein, gate configuration is on substrate, and gate insulation layer is disposed on the substrate and cover gate.Doping semiconductor layer is disposed on the gate insulation layer of grid top.In addition, channel layer is disposed on the doping semiconductor layer.In addition, an one source pole and a drain electrode are disposed at the both sides on the channel layer respectively.
In thin-film transistor of the present invention, above-mentioned doping semiconductor layer comprises a N type doped amorphous silicon layer.
In thin-film transistor of the present invention, above-mentioned doping semiconductor layer contains pentad, for example is phosphorus, arsenic or other group-v elements.
In thin-film transistor of the present invention, above-mentioned thin-film transistor also comprises an ohmic contact layer, is disposed between source electrode and channel layer and drain electrode and the channel layer.
The present invention proposes a kind of method of manufacturing thin film transistor, and it comprises the following steps.At first, provide a substrate.Then, form a grid on substrate.Afterwards, form a gate insulation layer on substrate, and cover gate.Then, form a doping semiconductor layer on the gate insulation layer of grid top.Then, form a channel layer on doping semiconductor layer.After, the both sides on channel layer form an one source pole and a drain electrode respectively.
In method of manufacturing thin film transistor of the present invention, the material of above-mentioned formation doping semiconductor layer comprises N type doped amorphous silicon.
In method of manufacturing thin film transistor of the present invention, the material of above-mentioned doping semiconductor layer contains pentad, for example is phosphorus, arsenic or other group-v elements.
In method of manufacturing thin film transistor of the present invention, between source electrode and channel layer and drain electrode and the channel layer, also can form an ohmic contact layer.
The present invention proposes a kind of dot structure, is suitable for being configured on the substrate.Dot structure of the present invention comprises a grid, a gate insulation layer, a doping semiconductor layer one channel layer, one source pole and a drain electrode, a protective layer and a pixel electrode.Wherein, gate configuration is on substrate, and gate insulation layer is disposed on the substrate, and cover gate.In addition, doping semiconductor layer is disposed on the gate insulation layer of grid top, and channel layer then is disposed on the doping semiconductor layer.In addition, source electrode and drain electrode are disposed at the both sides on the channel layer respectively.Protective layer covers source electrode and drain electrode at least, and protective layer has a contact window, to expose drain electrode.Pixel electrode then is disposed on the protective layer, and pixel electrode electrically connects through contact window and with drain electrode.
The present invention proposes a kind of one pixel structure process method, and it may further comprise the steps.At first, provide a substrate.Then, form a grid on substrate, form a gate insulation layer again on substrate, and cover gate.Afterwards, form a doping semiconductor layer on the gate insulation layer of grid top.Then, form a channel layer on doping semiconductor layer.In addition, the both sides on channel layer form an one source pole and a drain electrode respectively.Then, form a protective layer and cover in source electrode and the drain electrode, and form a contact window, to expose drain electrode in protective layer.Afterwards, form a pixel electrode on protective layer, and pixel electrode sees through contact window and drain electrode electric connection.
Therefore the channel layer below of thin-film transistor of the present invention can significantly reduce the leakage current of thin-film transistor in closed condition because of disposing doping semiconductor layer.In addition, method of manufacturing thin film transistor of the present invention and existing process-compatible, therefore method of manufacturing thin film transistor of the present invention need not increase extra process apparatus.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Figure 1A is the structural profile schematic diagram of existing thin-film transistor.
Figure 1B is the current-voltage curve of existing thin-film transistor.
Fig. 2 A～Fig. 2 E is the manufacture method of the thin-film transistor of first embodiment of the invention.
Fig. 3 is the current-voltage curve of first embodiment of the invention thin-film transistor.
Fig. 4 A～Fig. 4 G is the production method of pixel structure of second embodiment of the invention.
The main element symbol description:
100,200: thin-film transistor
110,210: substrate
120,220: grid
130,230: gate insulation layer
140,240,251: doping semiconductor layer
150:N type doped amorphous silicon layer
160,260a: source electrode
170,260b: drain electrode
250: channel layer
252: ohmic contact layer
260: metal material layer
270: protective layer
280: pixel electrode
Vg: grid voltage
H: contact window
Embodiment
First embodiment
Fig. 2 A～2E is the manufacturing process generalized section of the thin-film transistor of the first embodiment of the present invention.Please, at first provide a substrate 210 earlier with reference to Fig. 2 A.Then, on substrate 210, form grid 220.Particularly, grid 220 can adopt for example be physical vaporous deposition (PVD) deposit metallic material on substrate 210, relend by one photomask processing procedures this metal material carried out patterning, can finish the making of grid 220.
Then please refer to Fig. 2 B, on substrate 210, form gate insulation layer 230, with cover gate 220.The material of gate insulation layer 230 can be selected silicon nitride (Silicon Nitride) for use or with tetraethoxysilane (Tetra-Ethyl-Ortho-Silicate, TEOS) silica that forms for reacting gas source (SiO).
Please refer to Fig. 2 C afterwards, form doping semiconductor layer 240 on the gate insulation layer 230 of grid 220 tops.In an embodiment of the present invention, the method that forms doping semiconductor layer 240 for example can be selected hydrogen phosphide (Phosphine, PH for use
3), silicomethane (Silane, SiH
4), hydrogen carries out a chemical vapor deposition process by reacting gas source and formed.Specifically, in the present embodiment, the material of doping semiconductor layer 240 contains the doping (dopant) of pentad, therefore doping semiconductor layer for example is a N type doped amorphous silicon layer, and pentad for example is phosphorus or arsenic, in other embodiments, doping semiconductor layer also can be a P type doped amorphous silicon layer, is not limited at this.
Then please refer to Fig. 2 D, form channel layer 250 on doping semiconductor layer 240, and channel layer 250 for example is to form with chemical vapour deposition technique (CVD).On the practice, the material of channel layer 250 comprises amorphous silicon (amorphous silicon).Here be noted that for the contact impedance between metal material and the semi-conducting material (amorphous silicon) is descended can form a doping semiconductor layer 251 in the lump on channel layer 250, its material for example is a N type doped amorphous silicon.
Please refer to Fig. 2 E then, form source electrode 260a and drain electrode 260b in the both sides of channel layer 250 tops respectively.Particularly, source electrode 260a for example is to utilize physical vaporous deposition to deposit a metal material layer 260 on doping semiconductor layer 251 earlier with the formation method of drain electrode 260b, again this metal material layer 260 is carried out a patterning process in the lump with doping semiconductor layer 251.Just can form source electrode 260a and drain electrode 260b behind metal material layer 260 patternings, and just can form an ohmic contact layer 252 behind doping semiconductor layer 251 patternings.So far above-mentioned, thin-film transistor 200 of the present invention roughly completes.
Shown in Fig. 2 E, the thin-film transistor 200 of present embodiment is a bottom-gate (bottom gate) structure, and wherein the material of grid 220 for example is low resistance material such as aluminium, gold, copper, molybdenum, chromium, titanium, aluminium alloy or molybdenum alloy.In addition, source electrode 260a for example is low resistance material such as aluminium, molybdenum, titanium, gold, copper, chromium, silver or tantalum with the material of drain electrode 260b.Particularly, control puts on the voltage on the grid 220, just can open (turnon) or close (turn off) thin-film transistor 200.
It should be noted that doping semiconductor layer 240 can be configured between gate insulation layer 230 and the channel layer 250.Because doping semiconductor layer 240 contains group-v element (for example being phosphorus or arsenic).Therefore, doping semiconductor layer 240 can provide extra electronics, with in and channel layer 250 produce unnecessary hole because of grid 220 is subjected to negative voltage, and then reach the purpose that suppresses leakage current.
Fig. 3 is the current-voltage curve of first embodiment of the invention thin-film transistor.Please refer to Fig. 3, when thin-film transistor of the present invention was negative value at grid voltage Vg, electric current did not rise with negative voltage.When grid voltage Vg was-10 volts, size of current was about 3.00 * 10
-12Ampere.When grid voltage Vg was-10 volts, size of current was up to about 6.00 * 10 compared to the thin-film transistor 100 shown in existing Figure 1B
-12Ampere.This shows that thin-film transistor 200 of the present invention can have the effect that significantly suppresses leakage current generating when grid 220 bears negative voltage.So thin-film transistor 200 of the present invention can have good element characteristic.
Second embodiment
Fig. 4 A～4G is the one pixel structure process method of second embodiment of the invention.Wherein, the thin-film transistor 200 of the grid 220 of this dot structure 300, gate insulation layer 230, doping semiconductor layer 240, channel layer 250, ohmic contact layer 252, source electrode 260a and the drain electrode 260b and first embodiment is similar, it makes flow process shown in Fig. 4 A～4E, does not add to give unnecessary details at this.
Please directly with reference to Fig. 4 F, present embodiment also can form a protective layer 270 after source electrode 260a and drain electrode 260b form, to cover on source electrode 260a and the drain electrode 260b.Wherein, protective layer 270 has a contact window H, to expose drain electrode 260b.In detail, the material of protective layer 270 for example is silicon nitride, silica, silicon oxynitride, carborundum, organosilicon, organic material or above-mentioned combination.
Please refer to Fig. 4 G afterwards, form pixel electrode 280 on protective layer 270, and pixel electrode 280 electrically connects through contact window H and with drain electrode 260b.On the practice, the method that forms pixel electrode 280 for example is that the sputter process with physical vaporous deposition is formed.Generally speaking, the material of pixel electrode 280 for example is indium tin oxide, indium-zinc oxide, aluminium zinc oxide, zinc oxide, indium oxide or other transparent conductive material.So far above-mentioned, dot structure 300 of the present invention roughly completes.
Because doping semiconductor layer 240 is disposed at channel layer 250 belows, therefore when grid 220 was subjected to negative voltage, the leakage current at channel layer 250 places can effectively be suppressed.In other words, pixel electrode 280 can discharge and recharge exactly, and then good display quality can be arranged.
In sum, because the channel layer of thin-film transistor proposed by the invention below disposes doping semiconductor layer, it can effectively suppress the leakage current of thin-film transistor when closed condition.Therefore, thin-film transistor of the present invention has good element characteristic, and dot structure of the present invention can more effectively discharge and recharge.In addition, method of manufacturing thin film transistor of the present invention and existing process-compatible, therefore method of manufacturing thin film transistor of the present invention need not increase extra process apparatus.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (12)
1. a thin-film transistor is suitable for being configured on the substrate, it is characterized in that, this thin-film transistor comprises:
One grid is disposed on this substrate;
One gate insulation layer is disposed on this substrate, and covers this grid;
One doping semiconductor layer is disposed on this gate insulation layer of this grid top;
One channel layer is disposed on this doping semiconductor layer; And
An one source pole and a drain electrode are disposed at the both sides on this channel layer respectively.
2. thin-film transistor as claimed in claim 1 is characterized in that, this doping semiconductor layer comprises a N type doped amorphous silicon layer.
3. thin-film transistor as claimed in claim 1 is characterized in that this doping semiconductor layer contains pentad.
4. thin-film transistor as claimed in claim 3 is characterized in that this doping semiconductor layer contains phosphorus.
5. thin-film transistor as claimed in claim 3 is characterized in that this doping semiconductor layer contains arsenic.
6. thin-film transistor as claimed in claim 1 is characterized in that, also comprises an ohmic contact layer, is disposed between this source electrode and this channel layer and this drain electrode and this channel layer.
7. a dot structure is suitable for being configured on the substrate, it is characterized in that, this dot structure comprises:
One grid is disposed on this substrate;
One gate insulation layer is disposed on this substrate, and covers this grid;
One doping semiconductor layer is disposed on this gate insulation layer of this grid top;
One channel layer is disposed on this doping semiconductor layer;
An one source pole and a drain electrode are disposed at the both sides on this channel layer respectively;
One protective layer covers this source electrode and this drain electrode at least, and this protective layer has a contact window, to expose this drain electrode; And
One pixel electrode is disposed on this protective layer, and this pixel electrode electrically connects through this contact window and with this drain electrode.
8. dot structure as claimed in claim 7 is characterized in that, the material of this doping semiconductor layer comprises N type doped amorphous silicon.
9. dot structure as claimed in claim 8 is characterized in that the material of this doping semiconductor layer contains pentad.
10. dot structure as claimed in claim 8 is characterized in that the material of this doping semiconductor layer contains phosphorus.
11. dot structure as claimed in claim 8 is characterized in that, the material of this doping semiconductor layer contains arsenic.
12. dot structure as claimed in claim 11 is characterized in that, also comprises an ohmic contact layer, is disposed between this source electrode and this channel layer and this drain electrode and this channel layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101620266A CN101409308A (en) | 2007-10-10 | 2007-10-10 | Thin-film transistor, pixel structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101620266A CN101409308A (en) | 2007-10-10 | 2007-10-10 | Thin-film transistor, pixel structure and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101409308A true CN101409308A (en) | 2009-04-15 |
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| CNA2007101620266A Pending CN101409308A (en) | 2007-10-10 | 2007-10-10 | Thin-film transistor, pixel structure and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709329A (en) * | 2012-06-14 | 2012-10-03 | 深超光电（深圳）有限公司 | Thin film transistor and manufacturing method thereof |
| CN107369718A (en) * | 2017-08-07 | 2017-11-21 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor (TFT) and its manufacture method, liquid crystal display panel |
| CN108198823A (en) * | 2018-01-05 | 2018-06-22 | 惠科股份有限公司 | A kind of array substrate and display panel |
| US10510899B2 (en) | 2017-08-07 | 2019-12-17 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Thin film transistor, thin film transistor manufacturing method and liquid crystal display panel |
-
2007
- 2007-10-10 CN CNA2007101620266A patent/CN101409308A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709329A (en) * | 2012-06-14 | 2012-10-03 | 深超光电（深圳）有限公司 | Thin film transistor and manufacturing method thereof |
| CN107369718A (en) * | 2017-08-07 | 2017-11-21 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor (TFT) and its manufacture method, liquid crystal display panel |
| WO2019029009A1 (en) * | 2017-08-07 | 2019-02-14 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor and method for manufacturing thin film transistor, and liquid crystal display panel |
| US10510899B2 (en) | 2017-08-07 | 2019-12-17 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Thin film transistor, thin film transistor manufacturing method and liquid crystal display panel |
| CN108198823A (en) * | 2018-01-05 | 2018-06-22 | 惠科股份有限公司 | A kind of array substrate and display panel |
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Open date: 20090415 |