CN117440599A - Circuit board structure and manufacturing method thereof - Google Patents

Abstract

A circuit board structure and a manufacturing method thereof are provided, wherein the manufacturing method comprises the following steps. A temporary carrier plate is provided. Forming a first build-up structure on the temporary carrier, wherein the first build-up structure comprises a plurality of first circuits. Forming a second build-up structure on one side of the first build-up structure relatively far from the temporary carrier, wherein the second build-up structure comprises a plurality of second circuits, and the line width of the second circuits is larger than that of the first circuits. And bonding one side of the second build-up structure far away from the first build-up structure to the core layer. The temporary carrier is removed from the first build-up structure.

Description

Circuit board structure and manufacturing method thereof

Technical Field

The present invention relates to a circuit board, and more particularly to a circuit board structure and a method for manufacturing the same.

Background

Generally, a multilayer circuit structure of a circuit board is manufactured by build up (build up) or lamination (lamination). For example, the multi-layer circuit structure is manufactured by alternately stacking a build-up structure comprising copper foil (copper foil) and dielectric layers on a core layer (core), wherein the conductive material on the build-up structure can form conductive circuits according to a desired circuit layout, and the blind holes of the build-up structure can be filled with the conductive material to conduct each layer. Therefore, the number of the multilayer circuit structures can be adjusted according to the requirements.

In some applications, a build-up structure is required as a re-routed line layer (redistribution layer, RDL for short) to which the ultra-fine line technology is applied, but because the re-routed line layer is relatively fragile, the order of fabricating the re-routed line layer is arranged after the build-up structure of a general line width. Therefore, conventionally, after a general build-up structure is formed on a core layer, a redistribution layer is fabricated thereon. However, as the number of build-up structures increases, the overall flatness and thickness uniformity are worse, which makes it impossible for the exposure machine to expose the patterns of the rearranged circuit layers with the same focal length on the build-up structures of a general line width, resulting in a problem of a reduction in yield of the rearranged circuit layers.

For this reason, after a build-up structure with a common line width is formed on the core layer, a re-arranged circuit layer is additionally formed on another substrate, and the additionally formed re-arranged circuit layer is bonded to the build-up structure with a common line width by using solder balls. However, based on the limitation of the size and alignment of the solder balls, the rearranged circuit layer cannot be distributed to have the required line width and line distance, and the conductivity of the solder balls is lower than that of copper, and the problems of noise generation during high-frequency transmission, high-frequency signal integrity reduction and the like are also caused.

Disclosure of Invention

Accordingly, one of the objectives of the present invention is to provide a circuit board structure and a method for fabricating the same, which solve the above-mentioned problems associated with the conventional method for fabricating the rearranged circuit layer.

At least one embodiment of the present invention provides a method for manufacturing a circuit board structure, including the following steps: providing a temporary carrier plate; forming a first build-up structure on the temporary carrier, wherein the first build-up structure comprises a plurality of first circuits; forming a second build-up structure on one side of the first build-up structure relatively far from the temporary carrier plate, wherein the second build-up structure comprises a plurality of second circuits, and the line width of the second circuits is larger than that of the first circuits; bonding one side of the second build-up structure away from the first build-up structure to the core layer; and removing the temporary carrier from the first build-up structure.

In at least one embodiment of the present invention, the step of forming the first build-up layer structure on the temporary carrier includes: a plurality of first dielectric layers and a plurality of first circuit layers formed by first circuits are stacked on the temporary carrier in a staggered way in a layer adding process mode; and forming at least one first conductive blind hole penetrating the first dielectric layer and connected with the first circuit layer.

In at least one embodiment of the present invention, the step of forming the second build-up layer structure on a side of the first build-up layer structure relatively far from the temporary carrier plate includes: a plurality of second dielectric layers and a plurality of second circuit layers formed by second circuits are stacked on one side of the first build-up structure relatively far away from the temporary carrier in a staggered manner in a build-up process mode, wherein the first conductive blind holes are connected with one of the second circuit layers; and forming at least one second conductive blind hole penetrating the second dielectric layer and connected with the second circuit layer.

In at least one embodiment of the present invention, the step of bonding the second build-up layer structure to the core layer on a side of the second build-up layer structure remote from the first build-up layer structure includes: forming a bonding layer on the core layer; and arranging a second layer-adding structure on the bonding layer.

In at least one embodiment of the present invention, the step of forming the bonding layer on the core layer includes: forming a dielectric build-up layer on the core layer; forming at least one hole through the dielectric build-up layer, wherein the hole exposes at least one conductive contact of the core layer; and filling at least one conductive paste into the hole, wherein the conductive paste protrudes out of the hole to be connected with one of the second circuit layers of the second build-up structure.

In at least one embodiment of the present invention, the step of disposing the second build-up layer structure on the bonding layer includes: sintering the conductive paste to bond the second build-up structure to the core layer.

In at least one embodiment of the present invention, the step of forming the dielectric build-up layer on the core layer comprises: arranging a protective layer on one side of the dielectric build-up layer far away from the core layer; forming a hole penetrating the dielectric build-up layer and the protective layer; and filling the conductive paste into the holes, and enabling the conductive paste to protrude out of the surface of the protective layer far away from the dielectric build-up layer.

In at least one embodiment of the present invention, the above-mentioned manufacturing method further includes the following steps: at least one alignment target hole is formed on one side of the temporary carrier plate far away from the first build-up layer structure so as to provide alignment when the second build-up layer structure is jointed with the core layer.

In at least one embodiment of the present invention, the above-mentioned manufacturing method further includes the following steps: setting a release layer on one surface of the temporary carrier plate; and removing the temporary carrier plate and the release layer on the temporary carrier plate from the first build-up structure.

At least one embodiment of the present invention provides a circuit board structure, which includes a first build-up structure, a second build-up structure, and a core layer. The first build-up structure comprises a plurality of first circuits and at least one first conductive blind hole connected to at least part of the first circuits. The second build-up structure is arranged on the first build-up structure and comprises a plurality of second circuits and at least one second conductive blind hole connected with at least part of the second circuits. The line width of the second line is larger than that of the first line. The core layer is arranged on one side of the second layer-adding structure far away from the first layer-adding structure. The outer diameters of the first conductive blind holes and the second conductive blind holes are gradually increased towards the direction of the core layer.

In at least one embodiment of the present invention, the circuit board structure further includes a dielectric build-up layer and at least one conductive paste, wherein the dielectric build-up layer is between the core layer and the second build-up layer, and the conductive paste penetrates through the dielectric build-up layer and is connected between the second circuit of a portion of the second build-up layer and at least one conductive contact of the core layer.

Based on the above, since the first build-up structure of the first line with a narrower line width can be formed on the temporary carrier, and the second build-up structure of the second line with a wider line width is formed on the first build-up structure, when the first build-up structure is a rearranged line layer applying the ultra-fine line technology, the rearranged line layer can be manufactured under the environment of relatively high flatness and uniformity of plate thickness, which is helpful for the exposure light source to expose the whole line pattern with the same focal length, thereby improving the accuracy, yield and uniformity of the line shape, line width, line distance, etc. of the rearranged line layer.

In addition, the second build-up structure with thicker line width can be directly formed on the first build-up structure, and then the core layer is bonded on one side of the second build-up structure far away from the first build-up structure to complete the circuit board structure, so that the first build-up structure and the second build-up structure can be completed in the same build-up process, which is not only helpful for simplifying the process and reducing the cost, but also can avoid the traditional method of butting build-up structures with different line widths by using solder balls, thereby avoiding the problems of low conductivity, high-frequency noise increase, low high-frequency signal integrity and the like caused by using solder balls.

In addition, since the first build-up layer structure is formed on the temporary carrier plate before the second build-up layer structure is formed on the first build-up layer structure, the first build-up layer structure is arranged between the second build-up layer structure and the temporary carrier plate. Therefore, before the temporary carrier is removed, the first circuit of the first build-up structure can be in an isolated state so as to avoid the problems of air contact or damage caused by unexpected collision.

The foregoing description of the disclosure and the following description of the embodiments are presented to illustrate and explain the spirit and principles of the invention and to provide a further explanation of the invention as claimed.

Drawings

Fig. 1 to 22 show a step flow of a method for manufacturing a circuit board structure according to an exemplary embodiment of the present invention.

Detailed Description

The embodiments set forth below are described in conjunction with the accompanying drawings to provide a thorough understanding of the present invention and to enable a person skilled in the art to practice the same. It is to be understood that the illustrated embodiments are merely exemplary of some of the examples covered by the scope of the claims and are not intended to limit the scope of what the claims intend to cover. Moreover, for the purposes of illustration and understanding, the features of the drawings may not be to scale. Furthermore, like elements in the accompanying drawings will be denoted by like reference numerals.

In addition, terms such as "substantially," "about," and "substantially" may be used hereinafter to describe a reasonable amount of deviation that may exist for a modified event or circumstance, but still achieve the desired result. It is also possible to use "at least one" in the following to describe the quantity of the object to be described, but it should not be limited to the case of the quantity "only one" unless otherwise explicitly stated. The term "and/or" may also be used hereinafter and should be understood to include all combinations of any and many of the listed items. The terms "forming," "joining," "abutting," "disposing," "configuring," and the like may also be used below to describe the relative positional relationship between various layers, structures, elements, unless otherwise indicated, they may encompass the layers, structures, elements being in direct contact with one another, or there may be one or more intervening layers, structures, elements, etc. between the layers, structures, elements. The terms "first," "second," and the like may also be used below, but this is primarily for distinguishing between elements or operations described in the same language, and not for limiting the order or sequence of elements or operations.

Fig. 1 to 22 show a step flow of a method for manufacturing a circuit board structure according to an exemplary embodiment of the present invention, and fig. 1 to 22 are illustrated in a side cross-sectional view for ease of understanding.

Referring to fig. 1, first, a temporary carrier C is provided. The type and material of the temporary carrier C may be selected according to practical requirements, and the invention is not limited thereto. For example, in the present embodiment, the temporary carrier C may include a substrate 60. The substrate 60 may be, for example, but not limited to, a glass substrate (glass substrate), a silicon substrate (silicon substrate), a ceramic substrate (ceramic substrate), or a combination thereof. Optionally, the temporary carrier C may further include two metal thin film layers 61 disposed on opposite sides (or opposite surfaces) of the substrate 60. The metal thin film layer 61 may be, but is not limited to, a metal layer having a desired thickness. For example, in some embodiments, the metal film layer 61 may be a copper foil (copper foil) with a thickness of about 18 μm, but the arrangement, material and thickness of the metal film layer 61 may be adjusted according to practical requirements, and the invention is not limited thereto.

In addition, in the present embodiment, a release layer R may be disposed on each of opposite sides (or opposite surfaces) of the temporary carrier C, or a release layer R may be disposed on each of surfaces of the metal thin film layer 61 relatively far from the substrate 60. The release layer R may be, for example, but not limited to, a photo-cured release film (photo-curable release film) with a thickness of about 100nm, a thermally cured release film (thermal curable release film), or a laser release film (laser debond release film), but the arrangement, material and thickness of the release layer R may be adjusted according to practical needs, and the invention is not limited thereto.

In addition, optionally, in this embodiment, the surface of the release layer R relatively far from the temporary carrier C may be provided with a metal film layer 62. The metal thin film layer 62 may be, but is not limited to, a metal layer having a desired thickness. For example, in some embodiments, the metal film layer 62 may be, for example, a copper foil with a thickness of about 3 μm, but the arrangement, material and thickness of the metal film layer 62 may be adjusted according to practical requirements, and the invention is not limited thereto.

Next, a first build-up structure 10 (shown in fig. 8) may be formed on the metal film layer 62 on one side of the temporary carrier C by a build-up process. First, referring to fig. 2, a patterned mask layer M may be selectively formed on the metal film layer 62 on one side of the temporary carrier C. Specifically, the patterned masking layer M may be formed, for example, on a side (or, a surface) of one of the metal thin film layers 62 that is relatively far from the release layer R. For forming the patterned mask layer M, a suitable photosensitive dielectric material may be formed on the selected surface, for example, by chemical vapor deposition (chemical vapor deposition, CVD for short) or physical vapor deposition (physical vapor deposition, PVD for short), and then a portion of the photosensitive dielectric material may be removed by exposure and development to pattern the photosensitive dielectric material, thereby obtaining the patterned mask layer M. The patterned mask layer M may expose a portion of the metal film layer 62 in a predetermined pattern, so as to define the pattern and position of the first circuit layer 12 (shown in fig. 3) to be formed later. It should be noted that the pattern of the patterned mask layer M can be designed according to practical requirements, and the invention is not limited thereto.

Next, referring to fig. 3, a suitable metal material (e.g., copper) may be deposited on the exposed portion of the metal film layer 62 not covered by the patterned mask layer M by using a suitable method such as electroplating (electro plating) or electroless plating (chemical plating), so as to form the first circuit layer 12. The first circuit layer 12 may include a plurality of first pads 120 and a plurality of first wires 121, but the present invention is not limited to the number and configuration of the first pads 120 and the first wires 121 of the first circuit layer 12.

Next, referring to fig. 4, the patterned mask layer M is removed to expose the portion of the metal film layer 62 originally covered by the patterned mask layer M, and the first pads 120 and the first lines 121 of the first line layer 12 are left on the metal film layer 62. It should be noted that the thicknesses of the patterned mask layer M and the first circuit layer 12 may be designed according to practical requirements, and the invention is not limited thereto.

Next, referring to fig. 5, a first dielectric layer 11 may be formed on the surface of the metal film layer 62 on which the first circuit layer 12 is disposed, so as to cover the metal film layer 62 and the first pads 120 and the first circuits 121 of the first circuit layer 12. The first dielectric layer 11 may be formed by stacking and pressing a dielectric material having a desired thickness on a selected surface, but the invention is not limited thereto. For example, the first dielectric layer 11 may be, for example, a prepreg (prepreg), a photosensitive dielectric material (photoimageable dielectric, PID), a photosensitive polymer (e.g., benzocyclobutene), an ABF film (Ajinomoto build-up film), a fiberglass resin composite, or a combination thereof.

Optionally, the surface of the first dielectric layer 11 relatively far from the first circuit layer 12 may be provided with a metal film layer 63, and the metal film layer 63 may be, but not limited to, a copper foil with a desired thickness, and in this configuration, the metal film layer 63 and the first dielectric layer 11 may be jointly formed into a copper-clad foil (resin coated cooper foil), which is beneficial for subsequently adding another first circuit layer 12' on the first dielectric layer 11 (as shown in fig. 7).

Next, referring to fig. 6, one or more through holes 110 may be selectively formed on the first dielectric layer 11. For example, the through hole 110 may penetrate the metal film layer 63 and the first dielectric layer 11 to expose the first pad 120 of the first circuit layer 12. The via 110 may be formed, for example, by photolithographic etching, and thus, as shown, the cross-section of the via 110 may be tapered, for example. Specifically, the through holes 110 may have a gradually decreasing aperture toward the temporary carrier C, in other words, the through holes 110 may have a gradually increasing aperture toward a direction away from the temporary carrier C. However, it should be noted that the number and positions of the through holes are not required in the present invention.

Next, referring to fig. 7, optionally, a process as mentioned in fig. 2-4 may be performed on the metal film layer 63, for example, to form a first circuit layer 12' on the metal film layer 63, so as to form a plurality of first conductive blind holes 13 penetrating the first dielectric layer 11 at the positions of the through holes 110. The first circuit layer 12 'may have a similar or different pattern, line width and/or line spacing to the first circuit layer 12, and as shown, the first circuit layer 12' may include a plurality of first pads 120 'and a plurality of first lines 121', but the invention is not limited thereto. Further, since the first conductive blind hole 13 is formed in the through hole 110, the first conductive blind hole 13 also has a configuration in which a cross section is tapered, for example, so as to have an outer diameter gradually decreasing in a direction of the temporary carrier C (or, in other words, an outer diameter gradually increasing in a direction away from the temporary carrier C).

As shown in fig. 7, the first circuit layer 12 is located on a side (or surface) of the first dielectric layer 11 relatively close to the temporary carrier C, and the first circuit layer 12 'is located on a side (or surface) of the first dielectric layer 11 relatively far from the temporary carrier C, in other words, the first circuit layer 12, the first dielectric layer 11 and the first circuit layer 12' are sequentially stacked on the temporary carrier C in a staggered manner. The first conductive blind via 13 may be formed in the first dielectric layer 11 and connect the first pad 120 of the first circuit layer 12 and the first pad 120' of the first circuit layer 12', so that the first circuit layer 12 and the first circuit layer 12' can be electrically connected to each other through the first conductive blind via 13.

Next, referring to fig. 8, a process as mentioned in fig. 5 above may be performed on the first dielectric layer 11, for example, to form a first dielectric layer 11' on the first dielectric layer 11. The first dielectric layer 11' may be, but not limited to, a material and a configuration similar to or the same as those of the first dielectric layer 11, and thus will not be described herein. In detail, the first dielectric layer 11 'may be formed by stacking and pressing a dielectric material having a desired thickness on the surface of the first dielectric layer 11, so as to cover the first dielectric layer 11 and the first pads 120' and the first lines 121 'of the first line layer 12'. Therefore, the first circuit layer 12, the first dielectric layer 11, the first circuit layer 12' and the first dielectric layer 11 can be sequentially stacked on the temporary carrier C in a staggered manner, so that the first build-up structure 10 can be formed on the release layer R on one side of the temporary carrier C. In this embodiment, the first build-up structure is formed on the temporary carrier by using a build-up process, and each first circuit layer and each first dielectric layer may be defined as one build-up layer of the first build-up structure, but the number of build-up layers of the first build-up structure may be adjusted according to the actual requirement, which is not limited in the present invention; for example, the first build-up structure of other embodiments may be formed by stacking only the first dielectric layer and the first circuit layer; alternatively, the first build-up structure of other embodiments may also be a stacked structure formed by staggering a greater number of first dielectric layers and first circuit layers.

Next, as shown in fig. 8, the second build-up structure 20 may be formed, for example, on a side (or surface) of the first build-up structure 10 relatively far from the temporary carrier C by using a build-up process. First, the processes as mentioned in fig. 5 to 7 above may be performed on a side (or, a surface) of the first build-up structure 10 relatively far from the temporary carrier C, so that a plurality of through holes (not shown) exposing the first pads 120' of the first circuit layer 12' are formed on the first dielectric layer 11', and thus, a second circuit layer 22 may be formed on a side (or, a surface) of the first dielectric layer 11' relatively far from the temporary carrier C, and a plurality of first conductive blind holes 13 located in the first dielectric layer 11' may be formed at the through holes, wherein the second circuit layer 22 includes a plurality of second pads 220 and a plurality of second circuits 221, but the number and configuration thereof may be designed according to practical requirements. The first conductive blind via 13 in the first dielectric layer 11' can connect the first pad 120 of the first circuit layer 12' and the second pad 220 of the second circuit layer 22, so that the first circuit layer 12' and the second circuit layer 22 of the first build-up structure 10 can be electrically connected to each other through the first conductive blind via 13.

Next, a second dielectric layer 21 may be formed on the surface of the first dielectric layer 11' on which the second circuit layer 22 is disposed, so as to cover the second pads 220 and the second circuits 221 of the second circuit layer 22. The second dielectric layer 21 may have a similar or different material and configuration to any of the first dielectric layers described above, and thus will not be described herein.

Then, in a similar or identical manner to the above-mentioned manner of forming the through hole 110, a plurality of through holes (not shown) exposing the second pads 220 of the second circuit layer 22 are formed in the second dielectric layer 21, so that a second circuit layer 22' can be formed on a side (surface) of the second dielectric layer 21 relatively far from the temporary carrier C and a plurality of second conductive blind holes 23 can be formed in the through holes. The second circuit layer 22 'may have a similar or identical material and configuration to the second circuit layer 22, and as shown, the second circuit layer 22' may include a plurality of second pads 220 'and a plurality of second circuits 221', but the invention is not limited thereto. In this embodiment, the second circuit layer 22, the second dielectric layer 21 and the second circuit layer 22 'are sequentially stacked alternately on a side (or surface) of the first build-up layer structure 10 relatively far from the temporary carrier C, and the second conductive blind hole 23 is located in the second dielectric layer 21 and can connect the second pad 220 of the second circuit layer 22 and the second pad 220' of the second circuit layer 22', so that the second circuit layer 22 and the second circuit layer 22' can be electrically connected with each other through the second conductive blind holes 23. Also, similar to the first conductive blind holes 13 of the first build-up structure 10, the second conductive blind holes 23 have a configuration with a cross section, for example, a tapered shape, so as to have an outer diameter that gradually decreases in the direction of the temporary carrier plate C (or, in other words, an outer diameter that gradually increases in the direction away from the temporary carrier plate C).

It can be seen that the second circuit layer 22, the second dielectric layer 21 and the second circuit layer 22' are formed in a staggered stack on the side (or, the surface) of the first build-up structure 10 relatively far from the temporary carrier C, which may be similar to or the same as the build-up process for forming the first build-up structure 10, so that the second build-up structure 20 is formed on the side (or, the surface) of the first build-up structure 10 relatively far from the temporary carrier C. In this embodiment, the second build-up structure is directly formed on the first build-up structure by using a build-up process, and each of the second circuit layer and each of the second dielectric layers may be defined as one build-up layer of the second build-up structure, but the number of build-up layers of the second build-up structure may be adjusted according to the actual requirement, which is not limited in the present invention; for example, the second build-up structure of other embodiments may be formed by stacking only the second dielectric layer and the second circuit layer; alternatively, the second build-up structure of other embodiments may also be a stacked structure formed by staggering a greater number of second dielectric layers and second circuit layers.

In the present embodiment, the first build-up structure 10 may be a rearranged line layer (redistribution layer, abbreviated as RDL) applying ultra-fine line technology, and the second build-up structure 20 may be a line layer applying general routing technology, in which case the first lines 121 of the first line layer 12 and the first lines 121 'of the first line layer 12' may have line/spacing (L/S) of ultra-fine lines, and the second lines 221 of the second line layer 22 and the second lines 221 'of the second line layer 22' may have general line/line spacing (L/S) other than ultra-fine lines. Therefore, the line width/line spacing of the first build-up structure 10 is smaller than the line width/line spacing of the second build-up structure 20 compared to the first build-up structure 10 and the second build-up structure 20.

Specifically, in the present embodiment, the line widths/line distances of the first lines 121 and 121 'of the first build-up structure 10 are smaller than the line widths/line distances of the second lines 221 and 221' of the second build-up structure 20, in other words, the line widths/line distances of the second lines 221 and 221 'are larger than the line widths/line distances of the first lines 121 and 121'. For example, the first lines 121 and the first lines 121' may have a line width/line spacing of, for example, less than 10 μm. For example, the second lines 221 and 221' may have a line width/line spacing, for example, between 10 μm and 35 μm. In this case, in order to improve the accuracy, yield, etc. of the first lines 121 and 121', the build-up process of the first build-up structure 10 needs to be performed in an environment with high flatness and uniformity of thickness, and the standard is more severe than that of the build-up process of the second build-up structure 20.

Therefore, as can be seen from the above step flow, the first build-up structure 10 can be formed on the temporary carrier C before the second build-up structure 20 is formed on the first build-up structure 10, which can enable the first build-up structure 10 to build up in an environment with relatively high flatness and uniformity of thickness. Specifically, the temporary carrier C is usually a flat plate body with low processing limit, so the temporary carrier C can have relatively high flatness and uniformity of plate thickness, so the exposure light source can expose the whole line pattern with the same focal length on the temporary carrier C, so that the pattern of the patterned mask layer M has the line width, line spacing, density, precision and uniformity meeting the expected line width, line spacing and other precision, yield and uniformity of the patterns of the first lines 121 and 121'. When the uniformity of the line widths of the first lines 121 and 121 'is improved, the uniformity of the impedance of the first lines 121 and 121' is also improved.

On the other hand, the requirement of the second build-up structure 20 for the flatness and uniformity of the thickness of the environment of the build-up second lines 221 and 221 'can be relaxed, so that the flatness and uniformity of the thickness of the first build-up structure 10 are sufficient to achieve the required accuracy and yield of the build-up second lines 221 and 221' thereon.

In addition, since the first build-up structure 10 and the second build-up structure 20 are sequentially build-up formed on the temporary carrier C, the first build-up structure 10 is interposed between the second build-up structure 20 and the temporary carrier C. Therefore, before the temporary carrier C is removed, the first circuit layer 12 of the first build-up structure 10 can be isolated from the outside, so as to avoid the occurrence of damage caused by air contact or unexpected collision. Also, in the present embodiment, the second build-up structure 20 can be directly formed on the first build-up structure 10 by using a build-up process, which helps to simplify the process and reduce the cost.

Next, optionally, one or more alignment target holes PH may be formed on a side of the temporary carrier C relatively far from the first build-up structure 10 and the second build-up structure 20, for example. The alignment hole PH may penetrate the lamination of the release layer R and the metal film layer 62 on the other side of the temporary carrier C, for example, by laser, so that the second build-up structure 20 can accurately join the core layer 30 according to the position of the alignment hole PH in the subsequent steps. However, it should be noted that the setting of the alignment target hole PH may be selected, and the present invention is not limited thereto. The number, size, formation method, formation position, and the like of the alignment target holes PH are not limited to the present invention.

Next, referring to fig. 9, a core layer 30 is provided. The type and material of the core layer 30 can be selected according to practical requirements, but the invention is not limited thereto. For example, the core layer 30 may be a circuit board (circuit board), which may include a substrate 31, a plurality of via holes 32, and a plurality of patterned circuit layers 33 a-33 d. The material of the substrate 31 is, for example, resin, but the invention is not limited thereto; in other embodiments, the substrate 31 may be made of other suitable insulating materials. The patterned circuit layers 33 a-33 d may be made of any suitable conductive material, but the invention is not limited thereto, and the patterned circuit layers 33 a-33 d may have a line width/line spacing at least greater than 35 μm.

Further, as shown, the patterned circuit layer 33a may be formed on one side (or surface) of the substrate 31, the patterned circuit layer 33b and the patterned circuit layer 33c may be formed in the substrate 31, and the patterned circuit layer 33d may be formed on the other side (or surface) of the substrate 31. However, the patterned circuit layer 33b and the patterned circuit layer 33c in the substrate 31 are shown as schematic, and the invention is not limited thereto; for example, in the core layer of other embodiments, only one patterned circuit layer or more patterned circuit layers may be formed in the substrate according to practical requirements.

The material of the via 32 may be any suitable conductive material, and in this embodiment, the via 32 may be, for example, a plated through hole (plating through hole, PTH) that penetrates the substrate 31 and is connected to the patterned circuit layers 33 a-33 d, so that the patterned circuit layers 33 a-33 d are electrically connected to each other via the via 32. In addition, in the present embodiment, the patterned circuit layer 33a and the patterned circuit layer 33d may have one or more conductive contacts 331 exposed on the outer surface of the substrate 31, so as to facilitate the subsequent formation of a structure (such as the bonding layer 40 shown in fig. 15) on the core layer 30 for bonding the second build-up structure 20.

Next, referring to fig. 10, a solder mask SM may be selectively disposed on one side (or, a surface) of the core layer 30. For example, in the present embodiment, the solder mask layer SM may partially cover the side (or surface) of the core layer 30 on which the patterned circuit layer 33d is disposed, and has one or more openings O to selectively expose part of the conductive contacts 331 of the patterned circuit layer 33d. In the present embodiment, the material of the solder mask SM may include, for example, green paint, photosensitive dielectric material, ABF film or polymer resin material, but the invention is not limited thereto.

Next, referring to fig. 11, a surface treatment layer SF may be selectively formed in the opening O of the solder mask layer SM to cover the conductive contact 331 exposed by the solder mask layer SM, thereby providing an effect of protecting the conductive contact 331. The material of the surface treatment layer SF may be, for example, a suitable metal material or an oxidation-resistant organic film, and may specifically be gold, silver, palladium, nickel, tin or an organic solder mask (organic solderability preservative, abbreviated as OSP), but the invention is not limited thereto.

Next, referring to fig. 12, a dielectric build-up layer 41 may be formed on one side (or surface) of the core layer 30, which is subsequently used to bond the first build-up structure 10 and the second build-up structure 20, for example, to cover the surface of the core layer 30 and the conductive contacts 331. The material of the dielectric build-up layer 41 may be, but is not limited to, prepreg (prepreg) or other suitable materials, but the present invention is not limited thereto.

Next, optionally, the protective layer P may be covered, for example, on a side (or, a surface) of the dielectric build-up layer 41 relatively far from the core layer 30 to provide a protective effect. The material of the protective layer P may be, but not limited to, polyethylene terephthalate (polyethylene terphthalates, abbreviated as PET) or other suitable materials, and the invention is not limited thereto.

Also, optionally, another protection layer P may be covered on a side (or surface) of the surface treatment layer SF and the solder mask layer SM opposite to the core layer 30, for example, to provide a protection effect.

Next, referring to fig. 13, one or more holes H may be formed through the passivation layer P and the dielectric build-up layer 41 to expose at least one conductive contact 331 of the core layer 30. The holes H may be formed by, for example, photolithography, mechanical drilling, laser drilling, or other suitable methods, but the present invention is not limited to the number, location, and forming manner of the holes.

Next, referring to fig. 14, optionally, ultraviolet (UV) light may be used to clean the hole H, for example, to remove surface burrs or impurities in the hole H.

Next, referring to fig. 15, the conductive pastes 42 corresponding to the number of the holes H can be filled into the holes H. The material of the conductive paste 42 may be, but is not limited to, any suitable conductive material. For example, in some embodiments, the conductive paste 42 may be made of copper. In this step, the conductive paste 42 filled in the hole H may protrude from the hole H, and in particular, the conductive paste 42 may protrude at least flush or slightly from the surface of the protection layer P relatively far from the dielectric build-up layer 41.

Next, referring to fig. 16, the protection layer P may be removed from the dielectric build-up layer 41 to expose the surface of the dielectric build-up layer 41. As shown, since the conductive paste 42 may protrude at least flush or slightly from the surface of the protective layer P that is relatively far from the core layer 30 before the protective layer P is removed, it is ensured that the conductive paste 42 protrudes from the surface of the dielectric build-up layer 41 after the protective layer P is removed, while ensuring that the conductive paste 42 has a sufficient protruding amount to bond with a selected structure (e.g., the second pad 220' shown in fig. 17) in a subsequent step. Here, the dielectric build-up layer 41 and the conductive paste 42 may together form a bonding layer 40 on the core layer 30 for a subsequent process of bonding a side of the second build-up structure 20 relatively far from the first build-up structure 10 to the core layer 30.

Herein, referring to fig. 17 to 18, the stacked structure completed in fig. 8 may be docked to the stacked structure completed in fig. 16. Specifically, the second pads 220 'of the second circuit layer 22' of the second build-up structure 20 may be respectively abutted against the conductive paste 42 of the bonding layer 40 along the direction indicated by the arrow, so as to be bonded to the core layer 30 via the bonding layer 40.

In the process, since the temporary carrier C has the alignment target hole PH formed on the side (or the surface) relatively far from the first build-up structure 10 and the second build-up structure 20, the alignment target hole PH can be read by a reading device such as a charge coupled device (charge coupled device, abbreviated as CCD) to be an alignment point, so as to ensure that the second pad 220' of the second build-up structure 20 is abutted against the conductive paste 42 of the bonding layer 40 in a predetermined manner. In addition, in the process of bonding the second pad 220 'of the second build-up structure 20 to the conductive paste 42 of the bonding layer 40, for example, transient-liquid-phase sintering (TLPS) may be performed on the conductive paste 42 to adhere and electrically connect the conductive paste 42 to the second pad 220'. Accordingly, the second pad 220' of the second build-up structure 20 can be electrically connected to the conductive contact 331 on the core layer 30 through the conductive paste 42 of the bonding layer 40.

Next, referring to fig. 19, the temporary carrier C and the release layer R on the temporary carrier C may be removed from the first build-up structure 10 as indicated by the arrow. Specifically, the release layer R may be separated from the metal film layer 62, so that the temporary carrier C and the release layer R are removed from the first build-up structure 10, leaving the metal film layer 62 covering the first build-up structure 10. In the present embodiment, the method for removing the release layer R includes, for example, irradiation, heating, applying mechanical force (e.g. peeling) or laser dissociation to reduce the viscosity of the release layer R, but the invention is not limited thereto.

Next, referring to fig. 20, optionally, any suitable method (e.g., microetching) may be used to remove the metal film layer 62 covering the first build-up structure 10 to expose the first circuit layer 12 and the first dielectric layer 11 of the first build-up structure 10.

Next, referring to fig. 21, optionally, a solder mask SM' may be disposed on a side (or surface) of the first build-up structure 10 relatively far from the second build-up structure 20. The solder mask layer SM 'can partially cover a side (or surface) of the first build-up structure 10 that is relatively far from the second build-up structure 20, and has one or more openings O' to selectively expose the first pads 120 of the first circuit layer 12 of the first build-up structure 10 that is furthest from the second build-up structure 20. In the present embodiment, the material of the solder mask SM' may include, for example, green paint, photosensitive dielectric material, ABF film or polymer resin material, but the invention is not limited thereto.

Next, referring to fig. 22, optionally, a surface treatment layer SF 'may be formed in the opening O' of the solder mask layer SM 'to cover the first pad 120 exposed by the solder mask layer SM', thereby providing an effect of protecting the first pad 120. The material of the surface treatment layer SF' may be, for example, a suitable metal material or an oxidation-resistant organic film, and may be, for example, gold, silver, palladium, nickel, tin or an organic solder mask (organic solderability preservative, abbreviated as OSP), but the invention is not limited thereto.

Through the above steps, the circuit board structure 1 having the core layer 30, the second build-up structure 20 and the first build-up structure 10 stacked together is completed.

As can be seen from the above step flow, since the first build-up structure 10 and the second build-up structure 20 are sequentially formed on the temporary carrier C by the build-up process, and then the second build-up structure 20 is used to butt-joint the bonding layer 40 on the core layer 30, in the circuit board structure 1, the outer diameters of the first conductive blind holes 13 and the second conductive blind holes 23 in the first build-up structure 10 and the second build-up structure 20 are gradually increased toward the core layer 30, in other words, the outer diameters of the first conductive blind holes 13 and the second conductive blind holes 23 are gradually decreased toward a direction away from the core layer 30.

In addition, under this manufacturing process, when the first build-up structure 10 is a rearranged circuit layer using ultra-fine wires, the rearranged circuit layer can be manufactured under an environment with relatively high flatness and uniformity of plate thickness (i.e., the temporary carrier board C), which is conducive to enabling the exposure light source to perform exposure of the whole circuit pattern with the same focal length, so as to improve the accuracy, yield and uniformity of the line shape, line width, line spacing, etc. of the rearranged circuit layer.

In addition, the first build-up structure 10 and the second build-up structure 20 can be completed together in the same build-up process, which not only helps to simplify the process and reduce the cost, but also can avoid the conventional method of butting build-up structures with different line widths with solder balls, thereby avoiding the problems of low conductivity, high frequency noise increase, low high frequency signal integrity, and the like caused by using solder balls.

In addition, the second build-up structure 20 is bonded to the core layer 30 via the conductive paste 42 of the butt-joint layer 40, and in the case that the conductive paste 42 is copper paste, the conductive paste 42 can provide the required conductivity between the second build-up structure 20 and the core layer 30, and also helps to reduce noise during high frequency transmission, thereby helping to improve the integrity of the high frequency signal.

Furthermore, since the first build-up structure 10 is formed on the temporary carrier C first and then the second build-up structure 20 is formed on the first build-up structure 10, the first build-up structure 10 is interposed between the second build-up structure 20 and the temporary carrier C. Therefore, before the temporary carrier C is removed, the first circuit layer 12 of the first build-up structure 10 can be isolated from the outside, so as to avoid the occurrence of damage caused by air contact or unexpected collision.

Finally, it should be noted that, although the above-mentioned step flows are described in the order of the drawings, the present invention is not limited to the order; for example, in other embodiments, the steps of fig. 1-8 and the steps of fig. 9-16 can be performed in different order and according to the actual requirements.

[ symbolic description ]

1 Circuit board structure

10 first build-up layer structure

11,11' first dielectric layer

12,12': first line layer

13 first conductive blind via

20 second build-up layer structure

21 second dielectric layer

22,22': second circuit layer

23 second conductive blind via

30 core layer

31 substrate

32 via hole

33 a-33 d patterning circuit layer

40 bonding layer

41 dielectric build-up

42 conductive paste

60 substrate

61 Metal film layer

62 metal film layer

63 conductive layer

110 through hole

120,120' first connection pad

121,121 first line

220,220': second connection pad

221,221' second line

331 conductive contact

C, temporary carrier plate

H is a hole

O, O': opening

M: patterning mask layer

P protective layer

PH alignment target hole

R is release layer

SF, SF' surface treatment layer

SM, SM' solder mask.

Claims (11)

1. The manufacturing method of the circuit board structure is characterized by comprising the following steps:

providing a temporary carrier plate;

forming a first build-up structure on the temporary carrier, wherein the first build-up structure comprises a plurality of first circuits;

forming a second build-up structure on one side of the first build-up structure relatively far from the temporary carrier, wherein the second build-up structure comprises a plurality of second circuits, and the line widths of the second circuits are larger than those of the first circuits;

bonding one side of the second build-up structure away from the first build-up structure to the core layer; and

the temporary carrier is removed from the first build-up structure.

2. The method of claim 1, wherein forming the first build-up structure on the temporary carrier comprises:

a plurality of first dielectric layers and a plurality of first circuit layers formed by the first circuits are stacked on the temporary carrier in a staggered way in a layer adding process mode; and

at least one first conductive blind hole penetrating the first dielectric layers and connected with the first circuit layers is formed.

3. The method of claim 2, wherein forming the second build-up structure on a side of the first build-up structure that is relatively far from the temporary carrier comprises:

a plurality of second dielectric layers and a plurality of second circuit layers formed by the second circuits are stacked on one side of the first build-up structure relatively far away from the temporary carrier in a staggered manner in a build-up process mode, wherein at least one first conductive blind hole is connected with one second circuit layer; and

at least one second conductive blind hole penetrating the second dielectric layers and connected with the second circuit layers is formed.

4. The method of claim 3, wherein the step of bonding the second build-up structure to the core layer on a side of the second build-up structure remote from the first build-up structure comprises:

forming a bonding layer on the core layer; and

the second build-up structure is disposed on the bonding layer.

5. The method of claim 4, wherein forming the bonding layer on the core layer comprises:

forming a dielectric build-up layer on the core layer;

forming at least one hole through the dielectric build-up layer, wherein the at least one hole exposes at least one conductive contact of the core layer; and

filling at least one conductive paste into the at least one hole, wherein the at least one conductive paste protrudes out of the at least one hole to be connected with one of the second circuit layers of the second build-up structure.

6. The method of claim 5, wherein disposing the second build-up structure on the bonding layer comprises:

sintering the at least one conductive paste to bond the second build-up structure to the core layer.

7. The method of claim 5, wherein the step of forming the dielectric build-up layer on the core layer comprises:

disposing a protective layer on a side of the dielectric build-up layer away from the core layer;

forming the at least one hole through the dielectric build-up layer and the protective layer; and

filling the at least one conductive paste into the at least one hole, and protruding the at least one conductive paste from the surface of the protective layer away from the dielectric build-up layer.

8. The method of manufacturing of claim 1, further comprising:

at least one alignment target hole is formed on one side of the temporary carrier plate far away from the first build-up structure so as to provide alignment when the second build-up structure is jointed with the core layer.

9. The method of manufacturing of claim 1, further comprising:

setting a release layer on one surface of the temporary carrier plate; and

and removing the temporary carrier plate and the release layer on the temporary carrier plate from the first layer-adding structure.

10. A circuit board structure, comprising:

the first build-up structure comprises a plurality of first circuits and at least one first conductive blind hole connected with at least part of the first circuits;

the second build-up structure is arranged on the first build-up structure and comprises a plurality of second circuits and at least one second conductive blind hole connected with at least part of the second circuits, wherein the line width of the second circuits is larger than that of the first circuits; and

the core layer is arranged on one side of the second layer-adding structure far away from the first layer-adding structure;

wherein the outer diameters of the at least one first conductive blind hole and the at least one second conductive blind hole are gradually increased towards the core layer.

11. The circuit board structure of claim 10, further comprising a dielectric build-up layer between the core layer and the second build-up layer and at least one conductive paste extending through the dielectric build-up layer and connected between the second lines of portions of the second build-up layer and at least one conductive contact of the core layer.