CN117438880A - Three-dimensional integrated chip packaging structure and packaging method - Google Patents

Abstract

The application relates to a three-dimensional integrated Chiplet packaging structure and a packaging method, wherein the three-dimensional integrated Chiplet packaging structure comprises: a conductive layer; the chip structure unit comprises a first substrate, a laser chip, an optical chip and an electric chip are integrated on the first substrate, and the chip structure unit is integrally flipped to the conducting layer, so that the laser chip, the optical chip and the electric chip are electrically connected with the conducting layer; and the chip structure unit is integrally and inversely arranged on the second substrate through the conductive layer, so that the laser chip, the optical chip and the electric chip are electrically connected with the second substrate through the conductive layer. The integration level of the laser chip, the optical chip and the electric chip can be improved, and the packaging efficiency is improved. The passive high-efficiency end surface coupling of the laser chip and the optical chip is realized skillfully by means of the first substrate, the chip and the optical chip are jointly formed into the chip structure unit, and then the chip is bonded on the conducting layer through flip-chip bonding, so that the problems of difficult heat dissipation, overlarge volume and the like can be effectively solved.

Description

Three-dimensional integrated chip packaging structure and packaging method

Technical Field

The application relates to the technical field of advanced packaging, in particular to a three-dimensional integrated chip packaging structure and a packaging method.

Background

As transmission rates become higher, in addition to long-distance optical interconnections, inter-cabinet, inter-board and even inter-chip interconnections will also employ higher-speed optical interconnections. Therefore, the photoelectric chip is integrated in a package body in a system-in-package mode, so that photoelectric conversion is realized, and the photoelectric chip is assembled on a main board. However, the silicon optical chip cannot emit light, the laser is a III-V semiconductor device, the laser is used as a light source, and how to integrate the laser with the silicon optical chip and the electric chip is critical.

In the related art, a photoelectric chip integrated packaging structure is formed by directly flip-chip welding a laser chip on a carrier, flip-chip welding the optical chip on the carrier, and then welding an electric chip on the carrier.

However, when the waveguides of the laser chip and the optical chip are subjected to end-face coupling, the requirements on alignment precision in the directions of the X axis, the Y axis and the Z axis are very high, the heat dissipation efficiency of the laser chip and the electric chip is low, and the integration level and the packaging efficiency of each device are low in the packaging process.

Therefore, there is a need to design a new three-dimensional integrated chip package structure and packaging method to overcome the above-mentioned problems.

Disclosure of Invention

The application provides a three-dimensional integrated chip packaging structure and a packaging method, which can solve the technical problems of lower integration level and packaging efficiency of each device in the packaging process in a mode of respectively and independently packaging a laser chip, an optical chip and an electric chip in the related technology.

In a first aspect, embodiments of the present application provide a three-dimensional integrated chip package structure, including: a conductive layer; the chip structure unit comprises a first substrate, a laser chip, an optical chip and an electric chip are integrated on the first substrate, and the chip structure unit is integrally flipped to the conducting layer so that the laser chip, the optical chip and the electric chip are electrically connected with the conducting layer; and the Chiplet structure unit is integrally flipped to the second substrate through the conductive layer, so that the laser chip, the optical chip and the electric chip are electrically connected with the second substrate through the conductive layer.

With reference to the first aspect, in one embodiment, a side of the laser chip, the optical chip, and the electrical chip, which is far from the first substrate, each has a mounting surface, and the laser chip, the optical chip, and the electrical chip are mounted to the conductive layer through the mounting surfaces; defining the assembly direction of the chip structure unit and the conductive layer as a vertical direction, wherein the height difference of the mounting surfaces of the laser chip, the optical chip and the electric chip along the vertical direction is less than or equal to 2um.

With reference to the first aspect, in one embodiment, a direction along which the chip structure unit and the conductive layer are assembled is defined as a vertical direction, and thicknesses of the laser chip, the optical chip, and the electrical chip along the vertical direction are all equal.

With reference to the first aspect, in one embodiment, a heat conducting layer is disposed on one side of the first substrate, and the heat conducting layer and the electric chip are respectively attached to two opposite sides of the first substrate; the three-dimensional integrated chip packaging structure further comprises a shell which is covered outside the first substrate, the shell is attached to the heat conducting layer, and the shell is fixed with the second substrate, so that the first substrate, the laser chip, the optical chip, the electric chip and the conductive layer are packaged in the shell.

With reference to the first aspect, in one embodiment, the housing further includes a heat sink.

With reference to the first aspect, in an embodiment, the laser chip, the optical chip and the electrical chip are all fixedly provided with conductive microprotrusions, and the laser chip, the optical chip and the electrical chip are all electrically connected with the conductive layer through the conductive microprotrusions.

With reference to the first aspect, in one implementation manner, the laser chip has a first waveguide structure therein, and the laser chip is provided with a first coupling end face at the first waveguide structure; the optical chip is internally provided with a second waveguide structure, a second coupling end face is arranged at the second waveguide structure, the axis of the second waveguide structure and the axis of the first waveguide structure are positioned on the same horizontal line, and the second coupling end face and the first coupling end face each other and are parallel.

With reference to the first aspect, in one embodiment, the conductive layer is electrically connected with the second substrate through a conductive bump, and a conductive ball is further disposed at the bottom of the second substrate; the height of the conductive balls along the vertical direction is larger than that of the conductive protrusions along the vertical direction, and the height of the conductive protrusions along the vertical direction is larger than that of the conductive micro-protrusions along the vertical direction.

With reference to the first aspect, in an embodiment, the laser chip, the optical chip and the electrical chip are all fixedly provided with conductive micro-protrusions, a conductive protrusion is disposed at the bottom of the conductive layer, and a conductive hole is disposed in the conductive layer, and the conductive protrusion is electrically connected with the conductive micro-protrusion through the conductive hole.

In a second aspect, an embodiment of the present application provides a three-dimensional integrated chip packaging method, including the following steps:

integrating a laser chip, an optical chip and an electric chip together on a first substrate to form a chip structure unit;

integrally flip-chip the Chiplet structural unit to the conductive layer;

and integrally flip-chip the Chiplet structural unit to the second substrate through the conductive layer, so that the laser chip, the optical chip and the electric chip are electrically connected with the second substrate through the conductive layer.

With reference to the second aspect, in one embodiment, the integrating the laser chip, the optical chip, and the electrical chip together on the first substrate forms a chip structure unit, including:

the thicknesses of the laser chip, the optical chip and the electric chip are adjusted to be equal;

the laser chip, the optical chip and the electrical chip are together fixed to the upper surface of the first substrate to form a chip structure unit.

With reference to the second aspect, in one embodiment, the electrical chip comprises a drive electrical chip and/or a transimpedance amplifier electrical chip.

The beneficial effects that technical scheme that this application embodiment provided include at least:

through all integrate laser instrument chip, optical chip and electric chip and form holistic Chiplet structural unit on first base plate, can improve the integrated level of laser instrument chip, optical chip and electric chip, and at the in-process of encapsulation direct with Chiplet structural unit wholly flip-chip to the conducting layer can, flip-chip Chiplet structural unit and conducting layer together wholly to the second base plate again, realize Chiplet packaging structure, need not divide laser instrument chip, optical chip and electric chip to divide and independently encapsulate many times, the encapsulation efficiency can be improved to whole encapsulation mode, the technical problem that the integrated level and the encapsulation efficiency of each device are lower in the correlation technique has been solved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a three-dimensional integrated chip package structure according to an embodiment of the present application;

fig. 2 is a schematic step diagram of a three-dimensional integrated chip packaging method according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of another three-dimensional integrated chip package structure according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another three-dimensional integrated chip package structure according to an embodiment of the present application.

In the figure:

1. a conductive layer; 11. a conductive hole;

2. a Chiplet building block; 21. a first substrate; 22. a laser chip; 221. a first waveguide structure; 222. a first coupling end face;

23. an optical chip; 231. a second waveguide structure; 232. a second coupling end face; 24. an electrical chip; 25. a mounting surface; 26. conductive microprotrusions;

3. a second substrate; 4. a conductive bump; 5. a conductive ball;

6. a heat conducting layer; 7. a housing; 8. a heat sink.

Detailed Description

In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The embodiment of the application provides a three-dimensional integrated chip packaging structure and a three-dimensional integrated chip packaging method, which can solve the technical problems of lower integration level and lower packaging efficiency of each device in the packaging process in a mode of respectively and independently packaging a laser chip, an optical chip and an electric chip in the related technology.

Referring to fig. 1, a three-dimensional integrated chip package structure provided in an embodiment of the present application may include: a conductive layer 1; a chip structure unit 2, where the chip structure unit 2 includes a first substrate 21, on which a Laser chip 22 (LD), a photo chip 23 (PIC, photonic Integrated Circuit), and an electric chip 24 (EIC, electronic Integrated Circuit) are integrated on the first substrate 21, that is, all the various chips are integrated on the first substrate 21, so that the first substrate 21 fixes the chips as a whole, that is, forms the whole chip structure unit 2, and the chip structure unit 2 is integrally flipped to the conductive layer 1, so that the Laser chip 22, the photo chip 23, and the electric chip 24 are all electrically connected with the conductive layer 1; and a second substrate 3, the chip structure unit 2 is integrally flip-chip mounted to the second substrate 3 through the conductive layer 1, so that the laser chip 22, the optical chip 23 and the electrical chip 24 are electrically connected with the second substrate 3 through the conductive layer 1. That is, the chip structure unit 2 and the conductive layer 1 are fixed together, and when the chip structure unit is flipped to the second substrate 3, the chip structure unit 2 can be fixed to the second substrate 3 together by integrally flipping the conductive layer 1, so as to electrically connect the chip structure unit 2 and the second substrate 3.

In this embodiment, the laser chip 22, the optical chip 23 and the electrical chip 24 are integrated on the first substrate 21 to form the integral chip structure unit 2, so that the integration level of the laser chip 22, the optical chip 23 and the electrical chip 24 can be improved, the integral chip structure unit 2 is directly flipped to the conductive layer 1 in the packaging process, and then the integral chip structure unit 2 and the conductive layer 1 are flipped to the second substrate 3 together, so as to realize a chip packaging structure, the laser chip 22, the optical chip 23 and the electrical chip 24 do not need to be packaged separately for multiple times, and the packaging efficiency can be improved in an integral packaging mode, so that the technical problems of lower integration level and packaging efficiency of various devices in the related technology are solved.

Referring to fig. 1 and 2, in some embodiments, the laser chip 22, the optical chip 23, and the electrical chip 24 each have a mounting surface 25 on a side thereof remote from the first substrate 21, and the laser chip 22, the optical chip 23, and the electrical chip 24 are mounted to the conductive layer 1 through the mounting surfaces 25; defining the assembly direction of the chip structure unit 2 and the conductive layer 1 as a vertical direction, the height difference of the laser chip 22, the optical chip 23 and the mounting surface 25 of the electrical chip 24 along the vertical direction is less than or equal to 50nm. That is, after the laser chip 22, the optical chip 23 and the electrical chip 24 are mounted on the first substrate 21 in this embodiment, the mounting surfaces 25 of the laser chip 22, the optical chip 23 and the electrical chip 24 are substantially on the same horizontal plane, and after the laser chip 22, the optical chip 23 and the electrical chip 24 are flip-chip mounted on the conductive layer 1, it is ensured that the heights of the laser chip 22, the optical chip 23 and the electrical chip 24 are substantially uniform and are on the same horizontal plane.

In this embodiment, the laser chip 22, the optical chip 23 and the electrical chip 24 are preferably fixed to the first substrate 21 by means of adhesive, and the laser chip 22, the optical chip 23 and the electrical chip 24 each have an adhesive surface, the adhesive surface faces the first substrate 21, and the adhesive surface and the mounting surface 25 are distributed on opposite sides of the chip. The optical chip 23 may be a silicon optical chip 23, but may be other types of optical chips 23.

Preferably, the assembly direction of the chip structure unit 2 and the conductive layer 1 is defined as a vertical direction, and the thicknesses of the laser chip 22, the optical chip 23 and the electrical chip 24 along the vertical direction are all equal. In the present embodiment, since the thicknesses of the laser chip 22, the optical chip 23, and the electric chip 24 are all equal, when the laser chip 22, the optical chip 23, and the electric chip 24 are mounted on the same horizontal plane of the first substrate 21, the mounting surfaces 25 of the laser chip 22, the optical chip 23, and the electric chip 24 are located on the same horizontal plane. Wherein, since the thickness of the optical chip 23 and the electrical chip 24 is generally larger than that of the laser chip 22, the thickness of the optical chip 23 and the electrical chip 24 can be thinned by thinning process, so that the thickness of the three chips of the laser chip 22, the optical chip 23 and the electrical chip 24 is equal, and the thinning accuracy and the thickness uniformity of the chips are less than or equal to 50nm. The thickness of the laser chip 22, the optical chip 23 and the electrical chip 24 can be precisely controlled by adopting a mature thinning process, and the precision can be controlled at the nanometer level, so that the laser chip 22, the optical chip 23 and the electrical chip 24 can be precisely aligned in the vertical direction.

In other embodiments, the thicknesses of the laser chip 22, the optical chip 23 and the electrical chip 24 may be different, and the chips having different thicknesses may be realized by grooving the first substrate 21, placing the chips having a large thickness into the grooves, and placing the chips having a smallest thickness on the surface of the first substrate 21, where the mounting surface 25 is a surface for mounting to the conductive layer 1, and the mounting surface 25 exposed to the first substrate 21 after mounting to the first substrate 21 is on the same horizontal plane.

Referring to fig. 1, in some embodiments, the laser chip 22, the optical chip 23 and the electrical chip 24 are each fixedly provided with a conductive micro-protrusion 26, wherein the conductive micro-protrusion 26 may be disposed on the mounting surface 25, and the laser chip 22, the optical chip 23 and the electrical chip 24 are electrically connected to the conductive layer 1 through the conductive micro-protrusion 26.

Referring to fig. 1 and 2, in some alternative embodiments, the laser chip 22 has a first waveguide structure 221 therein, and the laser chip 22 is provided with a first coupling end surface 222 at the first waveguide structure 221; the optical chip 23 has a second waveguide structure 231 therein, and the optical chip 23 is provided with a second coupling end surface 232 at the second waveguide structure 231, the axis of the second waveguide structure 231 and the axis of the first waveguide structure 221 are on the same horizontal line, and the second coupling end surface 232 and the first coupling end surface 222 face each other and are parallel. In this embodiment, after the laser chip 22 and the optical chip 23 are mounted on the first substrate 21, the first waveguide structure 221 and the second waveguide structure 231 can be passively end-face coupled, and the axis of the second waveguide structure 231 and the axis of the first waveguide structure 221 are located on the same horizontal line, that is, the heights of the first waveguide structure 221 and the second waveguide structure 231 in the vertical direction are consistent, so that the coupling precision of the first waveguide structure 221 and the second waveguide structure 231 can be improved, meanwhile, since the mounting surface 25 of the laser chip 22 and the mounting surface 25 of the optical chip 23 are located on the same horizontal plane, and the sizes of the conductive micro-bumps 26 on the mounting surface 25 of the laser chip 22 and the mounting surface 25 of the optical chip 23 are the same, after the laser chip 22 and the optical chip 23 are flip-bonded to the conductive layer 1 through the first substrate 21 and the conductive micro-bumps 26, the heights of the first waveguide structure 221 and the second waveguide structure 231 are also guaranteed to be substantially consistent, and the heights of the first waveguide structure 231 are located on the same horizontal plane, and thus the vertical height of the first waveguide structure 221 and the second waveguide structure 231 can be controlled easily in the packaging process through the first substrate 21, and the technical problem of controlling the vertical height of the relevant laser chip and the optical chip 23 is difficult to control the precision is solved. The passive alignment mounting accuracy of the first waveguide structure 221 of the laser chip 22 and the second waveguide structure 231 of the optical chip 23 is less than or equal to 0.2um.

In this embodiment, the first waveguide structure 221 has a width ranging from 50nm to 2000nm (including but not limited to), and a height ranging from 200nm to 3000nm (including but not limited to); the second waveguide structure 231 has a width ranging between 300 and 1200nm (including but not limited to) and a height ranging between 100 and 600nm (including but not limited to).

In the conventional flip-chip bonding coupling method, when heated, solder ball or coppers pilar Solder melts and collapses or deforms, and the change is typically tens of micrometers or even tens of micrometers, however, the conventional diameter of the waveguide is only a few micrometers, so that the vertical height of the laser and the waveguide of the silicon optical chip 23 is difficult to precisely control, and the coupling accuracy is affected. The thickness of the laser chip 22, the optical chip 23 and the electric chip 24 can be precisely controlled through a conventional and mature thinning process, the precision can be controlled at the nanometer level, the laser chip 22, the optical chip 23 and the electric chip 24 are integrated on the first substrate 21 to form the chip structure unit 2 through the conventional and mature pasting process, and precise alignment coupling in the vertical direction can be realized through the waveguide structures of the laser chip 22 and the optical chip 23 after integration. And the Chiplet structural unit 2 is formed skillfully by means of the first substrate 21, so that the packaging efficiency is effectively improved, and the device integration level is improved.

Further, in some embodiments, the conductive layer 1 is electrically connected with the second substrate 3 through conductive protrusions 4, and conductive balls 5 are further disposed at the bottom of the second substrate 3; the height of the conductive balls 5 along the vertical direction is greater than the height of the conductive bumps 4 along the vertical direction, and the height of the conductive bumps 4 along the vertical direction is greater than the height of the conductive micro-bumps 26 along the vertical direction. In this embodiment, the conductive Micro-Bump 26 may be a Micro Bump, the conductive Bump 4 may be a C4 Bump (Controlled Callapse Chip Connection Bumps, controlled collapse chip pad), and the conductive Ball 5 may be a BGA Solder Ball (Ball Grid Array Solder Ball ). That is, the diameter of the conductive microprotrusions 26 is the smallest, the diameter of the conductive balls 5 is the largest, and setting the diameter of the conductive microprotrusions 26 to be the smallest is beneficial to reducing the diameter difference between the respective conductive microprotrusions 26, thereby reducing the height difference of the laser chip 22, the optical chip 23 and the electrical chip 24 after being mounted on the conductive layer 1.

Preferably, the diameter of the conductive microprotrusions 26 ranges from 2um to 150um, i.e., the minimum diameter of the conductive microprotrusions 26 may reach about 2um, and smaller diameters of the conductive microprotrusions 26 are beneficial to reducing the diameter gap between the respective conductive microprotrusions 26. The diameter of the conductive bump 4 is typically in the range of 100um to 150um, and the diameter of the conductive ball 5 is typically in the range of 200um to 750 um. If there is a gap between the waveguide structure of the laser chip 22 and the surface of the bonding pad and the waveguide structure of the optical chip 23 and the surface of the bonding pad, the gap can be compensated by selecting conductive microprotrusions 26 or conductive bumps 4 or conductive balls 5 with different diameters.

In some alternative embodiments, the laser chip 22, the optical chip 23 and the electrical chip 24 are all fixedly provided with conductive micro-protrusions 26, the bottom of the conductive layer 1 is provided with conductive protrusions 4, and conductive holes 11 are arranged in the conductive layer 1, and the conductive protrusions 4 and the conductive micro-protrusions 26 are electrically connected through the conductive holes 11. In this embodiment, a plurality of conductive vias 11 are disposed in the conductive layer 1, and the plurality of conductive vias 11 can electrically connect the plurality of conductive micro-bumps 26 on one side of the conductive layer 1 with the plurality of conductive bumps 4 on the other side of the conductive layer 1.

Referring to fig. 3, in some embodiments, a heat conducting layer 6 is disposed on one side of the first substrate 21, the heat conducting layer 6 and the electric chip 24 are respectively attached to two opposite sides of the first substrate 21, in this embodiment, the heat conducting layer 6 is attached to an upper surface of the first substrate, and the heat conducting layer 6 is made of a heat conducting material; the three-dimensional integrated chip package structure further comprises a housing 7 covered outside the first substrate 21, the housing 7 is attached to the heat conducting layer 6, and the housing 7 is fixed to the second substrate 3, so that the first substrate 21, the laser chip 22, the optical chip 23, the electric chip 24 and the conductive layer 1 are encapsulated in the housing 7. In this embodiment, the housing 7 is preferably made of metal, and the heat conducting layer 6 is disposed on the surface of the first substrate 21 and contacts with the housing 7, and the heat conducting layer 6 can transfer the heat generated by the chip to the housing 7, so as to dissipate the heat outwards through the housing 7.

Referring to fig. 4, in some alternative embodiments, the housing 7 is further covered with a heat sink 8. The heat sink 8 may be adhered to the surface of the housing 7 through the heat conducting layer 6, and in this embodiment, for a device with relatively high power, a heat sink structure may be selectively designed, so as to further dissipate heat, and the structure is flexible.

The thermal conductive layer 6 (TIM) provided on the first substrate 21 is denoted as TIM1, and the thermal conductive layer 6 provided between the housing 7 and the heat sink 8 is denoted as TIM2.TIM1, also known as primary TIM, is a thermally conductive material between the chip and the package housing 7, in direct contact with the chip having a very large heat generation, requiring low thermal resistance and high thermal conductivity of the TIM1 material, with a Coefficient of Thermal Expansion (CTE) matching that of the silicon wafer. The TIM2 is also known as a secondary TIM, and is a TIM between the package housing 7 and the heat sink 8. TIM2 is less demanding than TIM 1. TIM1 needs to have electrical insulation properties to prevent shorting of electronic components, typically polymer matrix composites; TIM2 has no electrical insulation performance requirements and is typically a carbon-based TIM.

The passive high-efficiency end surface coupling of the laser chip 22 and the optical chip 23 is realized skillfully by means of the first substrate 21, the chip 2 is formed by the electric chip 24, and then the chip is bonded on the conductive layer 1 through flip chip, so that the problems that the laser chip 22 (LD) is difficult to dissipate heat, the packaging integrated volume is overlarge and the like can be effectively solved; the packaging structure is novel, the packaging efficiency is improved, and the cost is effectively reduced.

Referring to fig. 2, the embodiment of the present application further provides a three-dimensional integrated chip packaging method, which may include the following steps:

step 1: the laser chip 22, the optical chip 23 and the electrical chip 24 are integrated together on the first substrate 21 to form the chip structure unit 2. The laser chip 22, the optical chip 23 and the electrical chip 24 may be adhered to the first substrate 21 by using an adhesive, and may be fixed by using an adhesive having a certain heat resistance and a certain thermal conductivity, so that heat generated by the laser chip 22, the optical chip 23 and the electrical chip 24 is conducted to the first substrate 21, and further dissipated through the first substrate 21, and the adhesive has a certain heat resistance, so that the adhesive can be prevented from melting. The first substrate 21 in this embodiment is preferably made of a material with low thermal expansion coefficient, easy thermal conduction, and difficult deformation due to heat and pressure, so that the first substrate 21 has good thermal conductivity, and can improve heat dissipation performance, such as but not limited to a silicon substrate, an alumina ceramic substrate, or an aluminum nitride ceramic substrate.

Step 2: the Chiplet structure unit 2 is integrally flip-chip mounted to the conductive layer 1. The laser chip 22, the optical chip 23 and the electrical chip 24 of the chip structure unit 2 are all provided with conductive microprotrusions 26, and the chip structure unit 2 is electrically connected with the conductive layer 1 through the conductive microprotrusions 26.

Step 3: the chip structure unit 2 is integrally flip-chip mounted to the second substrate 3 through the conductive layer 1, so that the laser chip 22, the optical chip 23 and the electrical chip 24 are electrically connected with the second substrate 3 through the conductive layer 1.

In some embodiments, in step 1, the integrating the laser chip 22, the optical chip 23 and the electrical chip 24 together on the first substrate 21 to form the chip structure unit 2 may include:

step 11: the thicknesses of the laser chip 22, the optical chip 23, and the electrical chip 24 are adjusted to be equal. The thicknesses of the optical chip 23 and the electrical chip 24 may be reduced by a mature thinning process, so that the thicknesses of the laser chip 22, the optical chip 23 and the electrical chip 24 are equal, and if the thickness of the laser chip 22 is not the thinnest of the three chips, the thickness of the laser chip 22 may be reduced, so that the thicknesses of the three chips are equal.

Step 12: the laser chip 22, the optical chip 23, and the electrical chip 24 are fixed together to the upper surface of the first substrate 21, forming the chip structure unit 2.

Preferably, the electrical chips 24 may include driver electrical chips 24 and/or transimpedance amplifier electrical chips 24. That is, the type of the electric chip 24 on the first substrate 21 may be a driving electric chip 24, a transimpedance amplifier electric chip 24, or a driving electric chip 24, a transimpedance amplifier chip, or another type of electric chip 24.

After step 3, step 4: the heat conductive layer 6 is provided on the surface of the first substrate 21, and the case 7 is covered on the first substrate 21, so that the case 7 is bonded to the heat conductive layer 6, and the case 7 is fixed to the second substrate 3, so that the first substrate 21, the laser chip 22, the optical chip 23, the electric chip 24, and the conductive layer 1 are packaged in the case 7.

Step 5: a heat sink 8 is arranged outside the shell 7.

In the description of the present application, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of description of the present application and simplification of the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

It should be noted that in this application, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing is merely a specific embodiment of the application to enable one skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A three-dimensional integrated chip package structure, comprising:

a conductive layer (1);

a Chiplet structure unit (2), wherein the Chiplet structure unit (2) comprises a first substrate (21), a laser chip (22), an optical chip (23) and an electrical chip (24) are integrated on the first substrate (21), and the Chiplet structure unit (2) is integrally flipped to the conductive layer (1) so that the laser chip (22), the optical chip (23) and the electrical chip (24) are electrically connected with the conductive layer (1);

and a second substrate (3), the chip structure unit (2) is integrally flipped to the second substrate (3) through the conductive layer (1), so that the laser chip (22), the optical chip (23) and the electrical chip (24) are electrically connected with the second substrate (3) through the conductive layer (1).

2. The three-dimensional integrated Chiplet package structure of claim 1,

the laser chip (22), the optical chip (23) and the electric chip (24) are provided with mounting surfaces (25) on one side far away from the first substrate (21), and the laser chip (22), the optical chip (23) and the electric chip (24) are mounted on the conductive layer (1) through the mounting surfaces (25);

defining an assembly direction along the chip structure unit (2) and the conductive layer (1) as a vertical direction, wherein a height difference along the vertical direction between the laser chip (22), the optical chip (23) and the mounting surface (25) of the electrical chip (24) is less than or equal to 50nm.

3. The three-dimensional integrated Chiplet package structure of claim 1,

defining the assembly direction of the chip structure unit (2) and the conductive layer (1) as a vertical direction, wherein the thicknesses of the laser chip (22), the optical chip (23) and the electric chip (24) along the vertical direction are all equal.

4. The three-dimensional integrated Chiplet package structure of claim 1,

a heat conducting layer (6) is arranged on one side of the first substrate (21), and the heat conducting layer (6) and the electric chip (24) are respectively attached to two opposite sides of the first substrate (21);

the three-dimensional integrated chip packaging structure further comprises a shell (7) covered outside the first substrate (21), the shell (7) is attached to the heat conducting layer (6), and the shell (7) is fixed to the second substrate (3), so that the first substrate (21), the laser chip (22), the optical chip (23), the electric chip (24) and the conductive layer (1) are packaged in the shell (7).

5. The three-dimensional integrated chip package structure according to claim 4, characterized in that the housing (7) is further covered with a heat sink (8).

6. The three-dimensionally integrated Chiplet packaging structure according to claim 1-5,

the laser chip (22) is internally provided with a first waveguide structure (221), and the laser chip (22) is provided with a first coupling end face (222) at the first waveguide structure (221);

the optical chip (23) is internally provided with a second waveguide structure (231), the optical chip (23) is provided with a second coupling end face (232) at the second waveguide structure (231), the axis of the second waveguide structure (231) and the axis of the first waveguide structure (221) are positioned on the same horizontal line, and the second coupling end face (232) and the first coupling end face (222) face each other and are parallel.

7. The three-dimensional integrated Chiplet package structure of claim 1,

the laser chip (22), the optical chip (23) and the electric chip (24) are all fixedly provided with conductive microprotrusions (26), the bottom of the conductive layer (1) is provided with conductive bulges (4), and conductive holes (11) are formed in the conductive layer (1), and the conductive bulges (4) are electrically connected with the conductive microprotrusions (26) through the conductive holes (11).

8. The three-dimensional integrated Chiplet packaging method is characterized by comprising the following steps of:

integrating a laser chip (22), an optical chip (23) and an electrical chip (24) together on a first substrate (21) to form a chip structure unit (2);

integrally flip-chip the Chiplet structural unit (2) to the conductive layer (1);

the chip structure unit (2) is integrally and inversely arranged on the second substrate (3) through the conductive layer (1), so that the laser chip (22), the optical chip (23) and the electric chip (24) are electrically connected with the second substrate (3) through the conductive layer (1).

9. The three-dimensional integrated chip packaging method according to claim 8, wherein integrating the laser chip (22), the optical chip (23) and the electrical chip (24) together on the first substrate (21) forms a chip structure unit (2), comprising:

the thicknesses of the laser chip (22), the optical chip (23) and the electrical chip (24) are adjusted to be equal;

a laser chip (22), an optical chip (23) and an electrical chip (24) are fixed together to the upper surface of the first substrate (21) to form a chip structure unit (2).

10. The method of three-dimensionally integrated Chiplet packaging of claim 8,

the electrical chip (24) comprises a driver electrical chip (24) and/or a transimpedance amplifier electrical chip (24).