CN117438306A - Trench double-diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents

Trench double-diffused metal oxide semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN117438306A
CN117438306A CN202210813484.6A CN202210813484A CN117438306A CN 117438306 A CN117438306 A CN 117438306A CN 202210813484 A CN202210813484 A CN 202210813484A CN 117438306 A CN117438306 A CN 117438306A
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Prior art keywords
trench
groove
region
gate
forming
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Inventor
许超奇
陈淑娴
张仪
林峰
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to CN202210813484.6A priority Critical patent/CN117438306A/en
Priority to PCT/CN2023/106711 priority patent/WO2024012430A1/en
Publication of CN117438306A publication Critical patent/CN117438306A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

The invention relates to a trench double-diffusion metal oxide semiconductor device and a manufacturing method thereof, wherein the method comprises the following steps: forming a hard mask layer on a substrate by using an active region photomask, and etching to form a first groove by taking the hard mask layer as an etching barrier layer, wherein active regions are arranged on two sides of the first groove; forming a bottom gate and an insulating isolation structure on the bottom gate in the first trench; forming a photoresist layer with an opening on the hard mask layer, wherein the opening is positioned above the source region, and the width of the opening is larger than that of the source region so as to expose the first groove part; etching the exposed insulating isolation structure to form a second groove; filling a gate material into the second trench as a top gate; removing the hard mask layer; source and drain regions are formed. The invention uses the first photoetching plate to etch the insulating isolation structure to form the top gate, and does not need to independently make a photoetching plate for etching the top gate, thereby saving the manufacturing cost.

Description

Trench double-diffused metal oxide semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a groove type double-diffusion metal oxide semiconductor device and a manufacturing method of the groove type double-diffusion metal oxide semiconductor device.
Background
In BCD process development, a plurality of devices such as Bipolar (Bipolar transistor)/CMOS (complementary metal oxide semiconductor device)/DMOS (double diffused metal oxide semiconductor device) are commonly developed, wherein the most widely used device is NLDMOSFET (N-channel lateral double diffused metal oxide semiconductor field effect transistor), so that in the general BCD process development process, the NLDMOS is integrated in a CMOS process platform first. RESURF (reduced surface electric field) technology is commonly used in device development to reduce the surface electric field of the LDMOS drift region and improve the voltage-withstanding performance of the LDMOS. However, a certain drift region length is required to achieve the voltage withstanding requirement, the LDMOS drift region is horizontal, and the VDMOS (vertical double-diffused metal oxide semiconductor) drift region is vertical, so that the device area of the LDMOS is still at a higher level than that of the vertical VDMOS. Typically, VDMOS is back-side extraction and is not compatible with CMOS processes, so VDMOS is rarely used in BCD process development. Therefore, the chip area of the chip obtained based on the existing BCD process platform is difficult to be further reduced.
The applicant proposes that the drain end in a shielded gate trench metal oxide semiconductor field effect transistor (Shield Gate Trench MOSFET, abbreviated as SGT) is led out from the front surface to be changed into a transverse trench double-diffused metal oxide (TrenchDMOS) device structure, so that the device performance of extremely small Rdson (on-resistance) can be achieved by utilizing the advantage of small VDMOS area. And because the drain end and the source end of the device are both on the front surface, the device can be compatible with CMOS process in theory, and the circuit area is further reduced.
Disclosure of Invention
Based on this, it is desirable to provide a method of fabricating a trench double diffused metal oxide semiconductor device for fabricating the foregoing SGT device.
A method of fabricating a trench double-diffused metal oxide semiconductor device, comprising: forming a hard mask layer on a substrate by using an active region photomask, and etching to form a first groove by taking the hard mask layer as an etching barrier layer, wherein active regions are arranged on two sides of the first groove; the active region photoetching plate comprises a source region pattern, a drain region pattern and a first groove pattern positioned between the source region pattern and the drain region pattern, wherein the first groove pattern is the first groove in a region corresponding to the substrate; forming a bottom gate and an insulating isolation structure on the bottom gate in the first trench; forming a first photoresist layer with an opening on the hard mask layer by using a first photoetching plate, wherein the opening is positioned above a source region, the width of the opening is larger than that of the source region so as to expose the first groove part, and the source region is a region corresponding to the source region pattern on the substrate; etching the exposed insulating isolation structure to form a second groove, wherein the insulating isolation structure still remains between the bottom of the second groove and the bottom gate; filling a first gate material into the second trench as a top gate; removing the hard mask layer; forming a source region and a drain region by doping; the first trench is located between the source region and the drain region, the source region is located on one side of the first trench where the top gate is located, and the drain region is located on the other side of the first trench.
According to the manufacturing method of the trench type double-diffusion metal oxide semiconductor device, the first photoetching plate is used for etching the insulating isolation structure to form the top gate, and a single photoetching plate is not needed for etching the top gate, so that the manufacturing cost can be saved, and the process complexity can be reduced. The drain electrode region of the device can be led out from the front surface, so that the device can be compatible with a CMOS process, the manufacturing method of the groove type double-diffusion metal oxide semiconductor device can be applied to a BCD process platform, and the chip area can be effectively reduced while the device performance is optimized.
In one embodiment, the light transmittance of the source region pattern and the drain region pattern of the active region reticle is opposite to the light transmittance of the first trench pattern.
In one embodiment, the width of the source region pattern is greater than the width of the drain region pattern.
In one embodiment, the active region mask includes a plurality of the first trench patterns, the source region is located between two adjacent first trenches, the drain region is located between two adjacent first trenches, and the width of the source region is not less than 0.45 μm.
In one embodiment, the source region has a width of no more than 0.6 microns.
In one embodiment, the width of the second trench is 0.05-0.1 microns.
In one embodiment, the active region photolithography mask further includes a second trench pattern, and one end of the first trench pattern is directly connected to the second trench pattern; the step of forming the first groove by taking the hard mask layer as an etching barrier layer comprises the following steps: etching the hard mask layer to form a first groove and a third groove by taking the hard mask layer as an etching barrier layer; the second groove pattern is the third groove in the area corresponding to the substrate; the step of forming a bottom gate and an insulating isolation structure on the bottom gate in the first trench includes: forming a gate dielectric layer on the inner surface of the first groove and the inner surface of the third groove; filling a second gate material in the first trench and the third trench in which the gate dielectric layer is formed; forming a second photoresist layer on the third groove by using a second photoetching plate to protect a second grid material in the third groove; the second gate material in the third groove is used as an extraction structure; etching the second gate material in the first trench by taking the second photoresist layer as an etching barrier layer to form the bottom gate; and removing the second photoresist layer, and then forming an insulating isolation structure on the bottom gate.
In one embodiment, the step of forming an insulating isolation structure on the bottom gate includes: forming an insulating isolation layer in the first trench and on the hard mask layer; and carrying out chemical mechanical polishing on the insulating isolation layer to obtain the insulating isolation structure, wherein the hard mask layer is a polished blocking layer.
In one embodiment, before the step of forming the hard mask layer on the substrate using the active region photomask, the method further includes a step of forming a first well region in the substrate, the first well region having a same conductivity type as the source region and the drain region, and the first trench and the third trench are formed in the first well region.
In one embodiment, the step of forming an insulating isolation structure on the bottom gate further comprises forming a shallow trench isolation structure between the trench type double-diffused metal oxide semiconductor device and the CMOS device, wherein the hard mask layer is used as a barrier layer for polishing of the shallow trench isolation structure.
In one embodiment, the step of forming a second well region in the substrate after the removing the hard mask layer, the source region being located in the second well region, the second well region having a second conductivity type well region, the source region and the drain region having a first conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.
It is also desirable to provide a trench type double-diffused metal oxide semiconductor device fabricated by the method of fabricating a trench type double-diffused metal oxide semiconductor device as described in any of the foregoing embodiments.
It is also desirable to provide a trench double-diffused metal oxide semiconductor device having a first trench extending from a front surface of a substrate into the substrate, the trench double-diffused metal oxide semiconductor device comprising: the bottom gate is arranged at the lower part of the first groove, and the bottom and the side surfaces of the bottom gate are surrounded by a gate dielectric layer positioned on the inner surface of the first groove; the insulating isolation structure is arranged in the first groove and on the bottom gate; the top gate is arranged in the first groove and is close to one side of the first groove, the top gate is positioned above the bottom gate, and the top gate and the bottom gate are separated by the insulating isolation structure; a source region arranged in the substrate at one side of the first groove where the top gate is arranged; a drain region arranged in the substrate at the other side of the first groove; the width of the source electrode region is larger than that of the drain electrode region, and the drain electrode region and the top gate are separated by the insulating isolation structure.
The width of the source region of the groove type double-diffusion metal oxide semiconductor device is larger than that of the drain region, and the situation that the hard mask for etching the groove is peeled off to influence the yield of the device can be avoided. And the drain electrode region of the device can be led out from the front surface, so that the device can be compatible with a CMOS process, can be applied to a BCD process platform, and can effectively reduce the chip area while optimizing the device performance.
Drawings
For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.
FIG. 1 is a flow chart of a method of fabricating a trench DMOS device in one embodiment;
FIG. 2 is a schematic diagram of a layout of an active area reticle in one embodiment;
fig. 3 a-3 f are schematic cross-sectional views of an embodiment of a device during the process of manufacturing a TrenchDMOS using the method shown in fig. 1;
FIG. 4 is a flow chart of the sub-steps of step S130 in one embodiment;
FIG. 5a is a schematic diagram of a portion of a layout of an active area reticle in another embodiment, and FIG. 5b is a schematic diagram of a corresponding location of the first photoresist layer 292 shown in FIG. 5 a;
fig. 6 is a schematic cross-sectional view of an exemplary TrenchDMOS structure when etching an insulating medium within a trench;
fig. 7 is a photomicrograph of the hard mask that had been exfoliated.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
An exemplary method for fabricating a drain-side front-side extraction TrenchDMOS is to form a bottom gate in a trench, then deposit an insulating medium on the bottom gate, photolithography and etch the insulating medium to form an insulating isolation structure on the bottom gate (requiring protection of the gate material in the trench used to form the extraction structure by photoresist), then fill the gate material on the insulating isolation structure, then remove the drain-side gate material by photolithography and etching, then fill the trench by the insulating medium, and finally CMP (chemical mechanical polishing). This approach requires a separate preparation of a reticle for etching the gate material at the drain end of the trench.
Fig. 1 is a flow chart of a method for manufacturing a trench double-diffused metal oxide semiconductor device according to an embodiment, which includes the following steps:
s110, forming a hard mask layer on the substrate by using the active region photomask.
The active region mask includes a source region pattern 204, a drain region pattern 202, and a first trench pattern 201 between the source region pattern 204 and the drain region pattern 202. Fig. 2 is a schematic diagram of a layout of an active area reticle in an embodiment, in which the active area reticle further comprises a second trench pattern 203. The source region pattern 204, the drain region pattern 202, and the first trench pattern 201 are located in the device region, and the second trench pattern 203 is located in the extraction region.
Fig. 3a is a schematic cross-sectional structure of the wafer after the completion of step S110, wherein the left side of the dash-dot line is the structure of the lead-out area (corresponding to the AA 'section in fig. 2), and the large-width structure of the lead-out area is reduced to a small-width structure for patterning, and the right side of the dash-dot line is the structure of the device area (corresponding to the BB' section in fig. 2). In one embodiment of the present application, the hard mask layer 230 is made of silicon nitride. In one embodiment of the present application, after a hard mask material is deposited on the substrate 210, a photoresist is coated on the hard mask material, then the photoresist is exposed using an active area reticle, after development, the photoresist forms an etching window, and then the hard mask material is etched to obtain the hard mask layer 230.
In one embodiment of the present application, the light transmittance of the source region pattern and the drain region pattern is opposite to that of the first trench pattern. Namely, the first groove pattern on the active region photoetching plate transmits light, and the source region pattern and the drain region pattern do not transmit light; or the source region pattern and the drain region pattern are transparent, and the first trench pattern is opaque.
In the embodiment shown in fig. 3a, a step of forming the first well region 212 is further included before the step S110. In one embodiment of the present application, the first well region 212 is a high voltage well. In one embodiment of the present application, first well region 212 is a first conductivity type well and substrate 210 is a second conductivity type substrate. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.
In the embodiment shown in fig. 3a, an oxide layer 220 may also be formed on the substrate 210 prior to forming the hard mask layer 230. In one embodiment of the present application, the oxide layer 220 is a pad oxide layer, and the material is silicon oxide, such as silicon dioxide.
S120, etching to form a first groove by taking the hard mask layer as an etching barrier layer, wherein the two sides of the first groove are active areas.
Referring to fig. 3b, the corresponding region after the first trench pattern 201 is transferred to the substrate 210 is a first trench 211, and the corresponding region after the second trench pattern 203 is transferred to the substrate 210 is a third trench 213. The first trench 211 is flanked by active regions. In the embodiment shown in fig. 3b, shallow trenches 215 are also required to be formed in the substrate 210 to form shallow trench isolation Structures (STI) between the TrenchDMOS and CMOS.
And S130, forming a bottom gate and an insulating isolation structure on the bottom gate in the first groove.
Bottom gate 242 and insulating isolation structures 224 on bottom gate 242 are formed in first trenches 211 (not labeled in fig. 3 c). In one embodiment of the present application, bottom Gate 242 is a Shield Gate. In one embodiment of the present application, step S130 further forms an extraction structure 248 in the third trench 213 (not shown in fig. 3 c). Since the first trench 211 and the third trench 213 communicate, the bottom gate 242 in the first trench 211 is in direct contact with the extraction structure 248 in the third trench 213, and the bottom gate 242 can be extracted from the front surface of the substrate 210 through the extraction structure 248.
Referring to fig. 4, in one embodiment of the present application, step S130 includes:
and S131, forming a gate dielectric layer on the inner surface of the first groove and the inner surface of the third groove.
In one embodiment of the present application, silicon dioxide may be formed as the gate dielectric layer 222 on the inner surfaces of the first trench 211 and the third trench 213 by thermal oxidation.
And S133, filling gate materials in the first groove and the third groove.
In one embodiment of the present application, the gate material is a polysilicon material, and in other embodiments a metal, metal nitride, metal silicide, or similar compound may be used as the gate material. The first trench and the third trench may be filled with a gate material by a deposition process. In one embodiment of the present application, the excess gate material may be removed by CMP, leaving only the gate material within the first trench 211 and the third trench 213. The gate material in the third trench 213 constitutes the extraction structure 248.
And S135, forming a photoresist layer on the third groove by photoetching to protect the gate material in the third groove.
In one embodiment of the present application, photoresist is coated on the front side of the substrate 210, and then the photoresist is exposed using an extraction structure reticle, and the photoresist layer remaining after development covers the third trench 213.
And S137, etching the gate material in the first groove to form a bottom gate.
And (3) taking the photoresist layer formed in the step S135 as an etching barrier layer, etching the gate material in the first groove 211 to the required bottom gate thickness, and forming the bottom gate 242.
And S139, forming an insulating isolation structure on the bottom gate.
In one embodiment of the present application, the photoresist layer is removed and then an insulating medium is deposited on the front side of the substrate 210 as an insulating isolation structure. In one embodiment of the present application, the insulating medium may be a silicon oxide, such as silicon dioxide. In one embodiment of the present application, step S139 further includes forming shallow trench isolation structures 228 in the shallow trenches 215.
With continued reference to fig. 1, step S130 further includes:
and S140, forming an opening above the source region by photoetching, wherein the width of the opening is larger than that of the source region so as to expose the first groove part.
Referring to fig. 3c, in one embodiment of the present application, a photoresist is coated on the front side of the substrate 210, and then the photoresist is exposed using a first reticle, and a developed first photoresist layer 292 forms an opening 291 over a source region (i.e., a region of the active region reticle corresponding to the source region pattern of the substrate 210). The width of the opening 291 is greater than the width of the source region, thereby partially exposing the first trench 211.
And S150, etching the exposed insulating isolation structure to form a second groove.
Referring to fig. 3d, the second trench 217, the first photoresist layer 292 and the hard mask layer 230 are etched to form an etch stop. In one embodiment of the present application, step S150 is a two-step etching, in which the insulating isolation structure 224 remained on the sidewall of the active region is first etched by dry etching and then rinsed by wet method.
And S160, filling gate materials into the second grooves to serve as top gates.
In an embodiment of the present application, a step of forming a gate dielectric layer is further included before filling the gate material, that is, a gate dielectric layer is formed on the exposed sidewalls of the first trench etched in step S150, and the gate dielectric layer may be made of silicon oxide, for example, silicon dioxide. The gate material filled may be the same as or different from the gate material filled in step S133. I.e., the top gate 244 may be the same material as the bottom gate 242 or may be different. In the embodiment shown in fig. 3e, the material of the top gate 244 and the bottom gate 242 is polysilicon. In one embodiment of the present application, step S160 removes the first photoresist layer 292 prior to depositing the polysilicon. After filling the second trench 217 with the gate material, the excess gate material may be removed by etching back or CMP.
S170, removing the hard mask layer.
In one embodiment of the present application, the hard mask layer 230 may be removed by an etching process.
And S180, forming a source region and a drain region by doping.
Ions of the first conductivity type are implanted by an ion implantation process to form the source region 254 and the drain region 252. The source region 254 is located on one side of the first trench 211 (not shown in fig. 3 f) where the top gate 244 is located, and the drain region 252 is located on the other side of the first trench 211. In the embodiment shown in fig. 3f, step S170 is followed by a step of forming the second well region 258. The second well region 258 serves as a channel region, the source region 254 is located in the second well region 258, and the second well region 258 has the second conductivity type.
According to the manufacturing method of the trench type double-diffusion metal oxide semiconductor device, the first photoetching plate is used for etching the insulating isolation structure to form the top gate, and a single photoetching plate is not needed to be made for etching the top gate, so that manufacturing cost can be saved (in the exemplary scheme, the etching of the insulating isolation structure also needs to use the single photoetching plate to protect the extraction structure), and process complexity is reduced. The drain electrode region of the device can be led out from the front surface, so that the device can be compatible with a CMOS process, the manufacturing method of the groove type double-diffusion metal oxide semiconductor device can be applied to a BCD process platform, and the chip area can be effectively reduced while the device performance is optimized.
For BCD process platforms, shallow trench isolation structures (see shallow trench isolation structures 228 in the previous embodiments) need to be provided between the TrenchDMOS and the CMOS. Referring to fig. 6, since the STI is usually completed before the CMOS process is performed and the hard mask (typically SiN film) is used as a barrier layer for CMP of the STI and other structures, the hard mask remains when the insulating medium in the trench is wet etched. So that peeling (peeling) is easily generated when the width of the active region pattern is small, i.e., the wet etching solution enters the oxide layer between the hard mask and the silicon, resulting in peeling of the hard mask, referring to fig. 7.
Fig. 5a is a schematic diagram of a portion of a layout of an active area reticle in another embodiment (the second trench pattern is omitted). In the embodiment shown in fig. 5a, the active region lithography comprises a source region pattern 304, a drain region pattern 302, and a first trench pattern 301 between the source region pattern 304 and the drain region pattern 302. According to the foregoing, the hard mask peeling easily occurs when the width of the active region pattern is smaller, but increasing the active region width increases the large device area and increases Rdson (on-resistance). Referring to fig. 3d, in the foregoing embodiment, the opening 291 is located above the position of the source region when the insulating isolation structure 224 is etched, and the position of the drain region is covered by the first photoresist layer 292 (the position of the first photoresist layer 292 corresponding to the active region mask layout is shown in fig. 5 b), that is, the opening 291 exposes the source region and a portion of the first trench around the source region. The drain region will not have the problem of hard mask peeling during etching back the insulating isolation structure in the portion of the first trench around the source region exposed by the opening 291. Thus, in one embodiment of the present application, the width of the source region pattern 304 is greater than the width of the drain region pattern 302, by increasing the width of the source region pattern 304 only, thereby avoiding hard mask flaking; while the width of the drain region pattern 302 may be reduced accordingly in order to avoid an increase in the device area or to keep the pitch (pitch) of the device as a whole unchanged. In one embodiment of the present application, the source region width a (see FIG. 3 d) is 0.45 microns or more. The inventor finds that the hard mask is not easy to peel when the corresponding width is more than or equal to 0.5 micron, and the hard mask is easy to peel when the corresponding width is less than or equal to 0.4 micron. In one embodiment of the present application, the source region width a is 0.45-0.6 microns and the drain region width is correspondingly reduced to 0.3-0.45 microns.
In one embodiment of the present application, the width of the second trench 217 is 0.05 to 0.1 micrometers, i.e., the width b of the opening 291 (see fig. 3 c) is 0.1 to 0.2 micrometers greater than the source region width a (see fig. 3 d).
Referring to fig. 5a and 5b together, in one embodiment of the present application, the first photoresist layer 292 intercepts the first trench pattern 301 and the second trench pattern, thereby cutting off the top gate 244, so as to avoid the top gate 244 from being electrically connected to the extraction structure 248.
The present application accordingly provides a trench type double-diffused metal oxide semiconductor device, which may be formed by using the trench type double-diffused metal oxide semiconductor device according to any of the foregoing embodiments. The structure of the trench type double-diffused metal oxide semiconductor device may refer to fig. 3f, which is provided with a first trench 211 (not labeled in fig. 3 f) extending from the front surface of the substrate 210 into the substrate 210, and the trench type double-diffused metal oxide semiconductor device further includes a bottom gate 242, an insulating isolation structure 224, a top gate 244, a source region 254, and a drain region 252. The bottom gate 242 is disposed at a lower portion of the first trench 211, and a bottom and sides of the bottom gate 242 are surrounded by the gate dielectric layer 222 at an inner surface of the first trench 211. The insulating isolation structure 224 is disposed in the first trench 211 and on the bottom gate 242. A top gate 244 is disposed in the first trench 211 and adjacent to one side of the first trench 211, the top gate 244 being located above the bottom gate 242, the top gate 244 being separated from the bottom gate 242 by the insulating isolation structure 224. The source region 254 is disposed in the substrate 210 on the side of the first trench 211 where the top gate 244 is disposed (the source region 254 is also separated from the top gate 244 by a thin gate dielectric layer 222), and is disposed near the front surface of the substrate 210. The drain region 252 is disposed in the substrate 210 at the other side of the first trench 211 and is disposed near the front surface of the substrate 210, and the drain region 252 is separated from the top gate 244 by the insulating isolation structure 224. The width of the source region 254 is greater than the width of the drain region 252.
The width of the source region 254 of the trench type double-diffused metal oxide semiconductor device is larger than that of the drain region 252, so that the situation that the hard mask for etching the trench is peeled off to influence the yield of the device can be avoided. And the drain electrode region 252 of the SGT device can be led out from the front surface, so that the SGT device can be compatible with a CMOS process, can be applied to a BCD process platform, and can effectively reduce the chip area while optimizing the device performance. TrenchDMOS is mainly formed by a vertical drift region, the lateral dimension is reduced, compared with a traditional LDMOS device, the area is reduced under the condition that Breakdown Voltage (BV) is consistent, and Rdson has great advantages. Meanwhile, the TrenchDMOS part does not need to be independent in the circuit because the CMOS technology can be compatible, and a large number of areas can be reduced on the circuit.
In the embodiment shown in fig. 3f, the trench double-diffused metal oxide semiconductor device further comprises a first well region 212. The first well region 212 serves as a drift region of the TrenchDMOS, and the source region 254 and the drain region 252 are located in the first well region 212, thereby constituting a U-shaped drift region. The doping type of the first well region 212 is the same as the source region 254 and the drain region 252. In one embodiment of the present application, the first well region 212, the source region 254, and the drain region 252 have a first conductivity type, and the substrate 210 has a second conductivity type.
In the embodiment shown in fig. 3f, the trench double-diffused metal oxide semiconductor device is further provided with a third trench 213 (not shown in fig. 3 f) in communication with the first trench 211, wherein the third trench 213 is provided with a conductive material, and the bottom gate 242 in the first trench 211 is in direct contact with the extraction structure 248 in the third trench 213, and the bottom gate 242 can be extracted from the front side of the substrate 210 through the extraction structure 248. In one embodiment of the present application, the bottom gate 242 is the same material as the extraction structures 248.
In the embodiment shown in fig. 3f, shallow trench isolation structures 228 are also provided on the front side of the substrate 210 as isolation between TrenchDMOS and CMOS.
In the embodiment shown in fig. 3f, a second well region 258 is further provided in the substrate 210 on the side of the first trench 211 where the top gate 244 is provided. The second well region 258 has a second conductivity type, and the source region 254 is disposed in the second well region 258.
It should be understood that, although the steps in the flowcharts of this application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of this application may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. A method of fabricating a trench double-diffused metal oxide semiconductor device, comprising:
forming a hard mask layer on a substrate by using an active region photomask, and etching to form a first groove by taking the hard mask layer as an etching barrier layer, wherein active regions are arranged on two sides of the first groove; the active region photoetching plate comprises a source region pattern, a drain region pattern and a first groove pattern positioned between the source region pattern and the drain region pattern, wherein the first groove pattern is the first groove in a region corresponding to the substrate;
forming a bottom gate and an insulating isolation structure on the bottom gate in the first trench;
forming a first photoresist layer with an opening on the hard mask layer by using a first photoetching plate, wherein the opening is positioned above a source region, the width of the opening is larger than that of the source region so as to expose the first groove part, and the source region is a region corresponding to the source region pattern on the substrate;
etching the exposed insulating isolation structure to form a second groove, wherein the insulating isolation structure still remains between the bottom of the second groove and the bottom gate;
filling a first gate material into the second trench as a top gate;
removing the hard mask layer;
forming a source region and a drain region by doping; the first trench is located between the source region and the drain region, the source region is located on one side of the first trench where the top gate is located, and the drain region is located on the other side of the first trench.
2. The method of manufacturing a trench double-diffused metal oxide semiconductor device according to claim 1, wherein a width of the source region pattern is larger than a width of the drain region pattern.
3. The method of claim 2, wherein the active region mask comprises a plurality of the first trench patterns, the source region is located between two adjacent first trenches, the drain region is located between two adjacent first trenches, and the source region has a width of not less than 0.45 μm.
4. The method of manufacturing a trench double-diffused metal oxide semiconductor device according to claim 3, wherein the width of the source region is not more than 0.6 μm.
5. The method of manufacturing a trench double-diffused metal oxide semiconductor device according to any one of claims 1 to 4, wherein a width of the second trench is 0.05 to 0.1 μm.
6. The method of manufacturing a trench double-diffused metal oxide semiconductor device according to claim 1, wherein the active region reticle further comprises a second trench pattern, one end of the first trench pattern being directly connected to the second trench pattern;
the step of forming the first groove by taking the hard mask layer as an etching barrier layer comprises the following steps: etching the hard mask layer to form a first groove and a third groove by taking the hard mask layer as an etching barrier layer; the second groove pattern is the third groove in the area corresponding to the substrate;
the step of forming a bottom gate and an insulating isolation structure on the bottom gate in the first trench includes:
forming a gate dielectric layer on the inner surface of the first groove and the inner surface of the third groove;
filling a second gate material in the first trench and the third trench in which the gate dielectric layer is formed;
forming a second photoresist layer on the third groove by using a second photoetching plate to protect a second grid material in the third groove; the second gate material in the third groove is used as an extraction structure;
etching the second gate material in the first trench by taking the second photoresist layer as an etching barrier layer to form the bottom gate;
and removing the second photoresist layer, and then forming an insulating isolation structure on the bottom gate.
7. The method of fabricating a trench double-diffused metal oxide semiconductor device according to claim 6, wherein the step of forming an insulating isolation structure on the bottom gate comprises:
forming an insulating isolation layer in the first trench and on the hard mask layer;
and carrying out chemical mechanical polishing on the insulating isolation layer to obtain the insulating isolation structure, wherein the hard mask layer is a polished blocking layer.
8. The method of claim 6, further comprising the step of forming a first well region in the substrate, the first well region having a same conductivity type as the source and drain regions, prior to the step of forming a hard mask layer on the substrate using the active region reticle, the first and third trenches being formed in the first well region.
9. The method of claim 7, wherein the step of forming an insulating isolation structure on the bottom gate further comprises forming a shallow trench isolation structure between the trench double-diffused metal oxide semiconductor device and a CMOS device, the hard mask layer acting as a barrier layer for polishing of the shallow trench isolation structure, applied to a BCD process platform.
10. A trench double-diffused metal oxide semiconductor device provided with a first trench extending from a front surface of a substrate into the substrate, comprising:
the bottom gate is arranged at the lower part of the first groove, and the bottom and the side surfaces of the bottom gate are surrounded by a gate dielectric layer positioned on the inner surface of the first groove;
the insulating isolation structure is arranged in the first groove and on the bottom gate;
the top gate is arranged in the first groove and is close to one side of the first groove, the top gate is positioned above the bottom gate, and the top gate and the bottom gate are separated by the insulating isolation structure;
a source region arranged in the substrate at one side of the first groove where the top gate is arranged;
a drain region arranged in the substrate at the other side of the first groove;
the width of the source electrode region is larger than that of the drain electrode region, and the drain electrode region and the top gate are separated by the insulating isolation structure.
CN202210813484.6A 2022-07-12 2022-07-12 Trench double-diffused metal oxide semiconductor device and manufacturing method thereof Pending CN117438306A (en)

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