CN117422030A - Dynamic time sequence checking method and device, storage medium and electronic equipment - Google Patents
Dynamic time sequence checking method and device, storage medium and electronic equipment Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000007689 inspection Methods 0.000 claims abstract description 39
- 238000010586 diagram Methods 0.000 claims abstract description 25
- 238000012300 Sequence Analysis Methods 0.000 claims abstract description 15
- 238000012795 verification Methods 0.000 claims abstract description 9
- 238000004088 simulation Methods 0.000 claims description 18
- 238000013461 design Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 14
- 238000004590 computer program Methods 0.000 claims description 10
- 235000013599 spices Nutrition 0.000 claims description 8
- 238000012731 temporal analysis Methods 0.000 claims 2
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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Abstract
The technical scheme of the application provides a method and a device for checking dynamic time sequence, a storage medium and electronic equipment, wherein the method for checking dynamic time sequence comprises the following steps: establishing a time sequence element list and a time sequence checking list corresponding to each time sequence element; obtaining a circuit schematic diagram or a circuit netlist of a circuit to be checked; automatically grabbing sequential elements from the circuit schematic diagram or the circuit netlist based on the sequential element list; according to the time sequence checklist and the grabbed time sequence elements, automatically acquiring a circuit checklist corresponding to the circuit to be checked, wherein the circuit checklist comprises: the names of the captured sequential elements, the hierarchy of the captured sequential elements in the circuit schematic diagram or circuit netlist, and the items of the captured sequential elements to be inspected in dynamic sequential inspection; and carrying the circuit checklist into a simulator for dynamic time sequence analysis to finish verification. The method can improve the accuracy and completeness of the inspection result.
Description
Technical Field
The present disclosure relates to the field of timing analysis technologies, and in particular, to a method and apparatus for checking dynamic timing, a storage medium, and an electronic device.
Background
Dynamic timing analysis (Dynamic Timing Analysis, DTA) is performed by filling a design with simulation stimulus and setting a simulation time period, and then performing timing and functional analysis on the simulation result. The simulation circuit is a netlist in a transistor-level spice format or a gate-level verilog format, needs to be fully verified under different working conditions and different voltages and temperatures, and DTA dynamic time sequence analysis is a very important chip verification method. The timing inspection method of the transistor stage is commonly as follows: verilog a checking method of a measurement function, a circuit checking method of a spice simulator, and the like.
Disclosure of Invention
The technical problem that this application will solve is: the accuracy and completeness of the existing dynamic time sequence checking result are low.
In order to solve the above technical problems, the present application provides a method for checking dynamic time sequences, including: establishing a time sequence element list and a time sequence checking list corresponding to each time sequence element, wherein the time sequence element list comprises the following components: a timing element name, the timing checklist comprising: the time sequence element is used for dynamically checking the items required to be checked in the time sequence; obtaining a circuit schematic diagram or a circuit netlist of a circuit to be checked; automatically grabbing sequential elements from the circuit schematic diagram or the circuit netlist based on the sequential element list; according to the time sequence checklist and the grabbed time sequence elements, automatically acquiring a circuit checklist corresponding to the circuit to be checked, wherein the circuit checklist comprises: the names of the captured sequential elements, the hierarchy of the captured sequential elements in the circuit schematic diagram or circuit netlist, and the items of the captured sequential elements to be inspected in dynamic sequential inspection; and carrying the circuit checklist into a simulator for dynamic time sequence analysis to finish verification.
Optionally, the establishing the sequential element list includes: a list of sequential elements is created based on the library of process elements.
Optionally, the process element library includes: foundry issues a standard design package file.
Optionally, the circuit checklist supports generating a checksyntax for different emulators.
Optionally, the simulator for dynamic time sequence analysis includes: transistor-level simulators in high-speed circuit designs.
Optionally, the transistor-level emulator includes: a spice simulator with timing checks at the transistor level.
The application also provides a dynamic time sequence checking device, which comprises: a creation unit adapted to create a sequential element list and a sequential checklist corresponding to each sequential element, the sequential element list comprising: a timing element name, the timing checklist comprising: the time sequence element is used for dynamically checking the items required to be checked in the time sequence; a circuit acquisition unit adapted to acquire a circuit schematic or a circuit netlist of a circuit to be inspected: an element list grabbing unit adapted to automatically grab sequential elements from the circuit schematic or circuit netlist based on the sequential element list; the inspection list acquisition unit is suitable for automatically acquiring a circuit inspection list corresponding to the circuit to be inspected according to the time sequence inspection list and the captured time sequence elements, wherein the circuit inspection list comprises: the names of the captured sequential elements, the hierarchy of the captured sequential elements in the circuit schematic diagram or circuit netlist, and the items of the captured sequential elements to be inspected in dynamic sequential inspection; and the simulation unit is suitable for bringing the circuit checklist into a simulator for dynamic time sequence analysis to complete verification.
Optionally, the establishing the sequential element list includes: a list of sequential elements is created based on the library of process elements.
Optionally, the process element library includes: foundry issues a standard design package file.
Optionally, the circuit checklist supports generating a checksyntax for different emulators.
Optionally, the simulator for dynamic time sequence analysis includes: transistor-level simulators in high-speed circuit designs.
Optionally, the transistor-level emulator includes: a spice simulator with timing checks at the transistor level.
The present application also provides a computer readable storage medium having stored thereon a computer program for execution by a processor to perform the steps of the above method.
The electronic device comprises a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor executes the steps of the method when running the computer program.
By using the method for checking the dynamic time sequence in the embodiment of the application, the time sequence element list and the time sequence checking list corresponding to each time sequence element are established in advance, and then the circuit checking list corresponding to the circuit to be checked is automatically obtained based on the circuit schematic diagram or the circuit netlist, so that the obtained circuit checking list contains all the time sequence elements corresponding to the circuit to be checked, and the time sequence elements have a hierarchical structure in the circuit checking list. The circuit inspection list is brought into a simulator for dynamic time sequence analysis, so that the accuracy and completeness of inspection results can be improved.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a flow chart of a method for checking dynamic time sequences according to an embodiment of the present application;
fig. 2 is a flow chart of a dynamic time sequence checking device according to an embodiment of the present application.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is obvious to those skilled in the art that the present application may be applied to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, the same reference numerals or the same reference numerals in the figures denote the same elements throughout the specification.
The terminology used in the present application is for the purpose of describing particular example embodiments only and is not intended to be limiting. For example, as used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. The terms "comprises," "comprising," "includes," and/or "including," when used in this specification, are taken to specify the presence of stated integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. When different elements are described in the specification as being associated with each other, the relationship may be direct or indirect. For example, "a and B connected" may be a direct connection between a and B, or an indirect connection between a and B via other elements.
These and other features, as well as the operation and function of the related elements of structure, as well as the combination of parts and economies of manufacture, disclosed herein may be significantly improved upon in view of the following description. All of which form a part of the disclosure of the present specification, refer to the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the disclosure.
Referring to fig. 1, the method for checking dynamic time sequence according to the embodiment of the present application includes:
step S1: establishing a time sequence element list and a time sequence checking list corresponding to each time sequence element, wherein the time sequence element list comprises the following components: a timing element name, the timing checklist comprising: the time sequence element is used for dynamically checking the items required to be checked in the time sequence;
step S2: obtaining a circuit schematic diagram or a circuit netlist of a circuit to be checked;
step S3: automatically grabbing sequential elements from the circuit schematic diagram or the circuit netlist based on the sequential element list;
step S4: according to the time sequence checklist and the grabbed time sequence elements, automatically acquiring a circuit checklist corresponding to the circuit to be checked, wherein the circuit checklist comprises: the names of the captured sequential elements, the hierarchy of the captured sequential elements in the circuit schematic diagram or circuit netlist, and the items of the captured sequential elements to be inspected in dynamic sequential inspection;
step S5: and carrying the circuit checklist into a simulator for dynamic time sequence analysis to finish verification.
The following describes the above steps in detail:
in order to facilitate automatic grabbing of sequential elements in the schematic circuit diagram or the netlist, the file format and the written language of the list of sequential elements established in step S1 need to be matched with the schematic circuit diagram or the netlist, and especially the names of the sequential elements in the list of sequential elements need to be consistent with the schematic circuit diagram or the netlist.
Common timing elements include registers, memory devices, etc., and non-timing elements include inverters, nand gates, etc. Therefore, in step S1, when the time series element list is established, it may be established based on the process element library. The process element library may comprise: foundry issues a standard design package file. The time sequence element list established in this way not only has compatible contents and formats, but also can contain all time sequence elements as much as possible.
In step S1, a timing checklist is also required to be established, where the timing checklist includes: items that the sequential elements need to examine in dynamic sequential examination, such as items that the D flip-flop needs to examine, include: timing checking of the Setup time (Setup time) and Hold time (Hold time) of CK terminal to data_in terminal.
In step S2, a schematic circuit diagram or a netlist of the circuit to be inspected is obtained. The circuit schematic or circuit netlist contains sequential elements and non-sequential elements in the circuit to be checked.
In step S3, sequential elements are automatically grabbed from the schematic circuit diagram or the netlist based on the list of sequential elements established in step S1. The grabbing method can comprise the following steps: name matching. When the names are matched, the names of the time sequence elements can be matched in a full name mode, and the key word matching can be performed.
In the process of grabbing the sequential elements, orderly grabbing is performed according to the circuit schematic diagram or the circuit netlist level, for example, the grabbing is started from a first layer, the grabbing is ended, and then the sequential elements enter a second layer, and the like, and the sequential elements are performed layer by layer. The grabbed time sequence element is marked with the reference number of the level where the time sequence element is located and the referenced cell name so as to facilitate subsequent simulation.
In the prior art, a method for grabbing a time sequence element from a circuit to be inspected exists, namely, a static time sequence analysis tool, a post-simulation, a pre-simulation and the like are utilized to obtain a simulation result, and time sequence parameters are extracted from the simulation result. However, those skilled in the art know that the simulation process needs to add constraint conditions, and the constraint conditions tend to cause missing sequential elements in the simulation result, so that the last sequential element to be grabbed is not comprehensive enough, and the additional simulation procedure also reduces the inspection efficiency. The embodiment directly grabs the time sequence elements from the circuit schematic diagram or the circuit netlist based on the time sequence element list established in advance, so that the probability of missing the time sequence elements can be obviously reduced, and the checking efficiency is improved.
After step S3, all the levels of the timing elements included in the circuit to be inspected and the timing elements are automatically extracted. And then, executing step S4, wherein the time sequence element grabbed in step S3 is used as the time sequence element to be checked in time sequence, and Cell names in the time sequence checking list established in step S1 are uniquely matched with Cell names marked by the time sequence element to obtain a complete circuit checking list corresponding to the circuit to be checked.
In the circuit checklist, all time sequence element names in the circuit to be checked, the levels of the time sequence elements in the circuit schematic diagram or the circuit netlist are covered, and the items of the time sequence elements to be checked in the dynamic time sequence checking are covered. The circuit checklist may support the generation of a checkgrammar for different emulators.
The following is an example:
step S3, grabbing time sequence elements:
X1.I0 (DFF2X)
X1.X2.I1 (DFF2X)
X1.X2.X3.I2 (DFF2X)
step S1, establishing a time sequence checking list:
DFF2X CK(R) DATA_IN setup(5ns),hold(5ns)
SDFF2X CK(R) RSTN recovery(2ns),removal(2ns)
circuit checklist of circuits to be checked:
.chktiming type=setup ref=”X1.I0:CK” refedge=r name=”X1.I0:DATA_IN” edge=x time=”5ns”
.chktiming type=setup ref=”X1.X2.I1:CK” refedge=r name=”X1.X2.I1:DATA_IN” edge=x time=”5ns”
.chktiming type=setup ref=”X1.X2.X3.I2:CK” refedge=r name=”X1.X2.X3.I2:DATA_IN” edge=x time=”5ns”
and finally, executing step S5, and bringing the circuit inspection list corresponding to the circuit to be inspected into a simulator for dynamic time sequence analysis to finish verification. The simulator of the dynamic timing analysis may include: various transistor level emulators in high speed circuit designs. In particular, the transistor-level emulator may be a transistor-level spice emulator with timing checking.
In step S5, if an inspection abnormality occurs during the operation of the simulator, a prompt message is generated. An exception indication may occur, which may be a problem with the circuit checklist, in which case the circuit checklist may be iterated into the simulator again for simulation. And when abnormal prompt occurs, the time sequence inspection finds that the circuit to be inspected has a problem, and the circuit to be inspected needs to be optimally adjusted, in this case, the circuit to be inspected can be modified first, then the circuit inspection list is updated, and the updated circuit inspection list is iterated into the simulator for simulation.
The timing requirements in high-speed circuit design are extremely stringent, and higher requirements are put on the accuracy of timing inspection, so that almost no residual quantity remains. By using the method for checking the dynamic time sequence in the embodiment of the application, the time sequence element list and the time sequence checking list corresponding to each time sequence element are established in advance, and then the circuit checking list corresponding to the circuit to be checked is automatically obtained based on the circuit schematic diagram or the circuit netlist, so that the obtained circuit checking list contains all the time sequence elements corresponding to the circuit to be checked, and the time sequence elements have a hierarchical structure in the circuit checking list. Therefore, the circuit inspection list is brought into a simulator for dynamic time sequence analysis, so that the accuracy and completeness of inspection results can be obviously improved, and the circuit inspection list accords with the dynamic time sequence inspection of transistor-level simulation circuits in high-speed circuit design.
Referring to fig. 2, corresponding to the above-mentioned inspection method, the present embodiment further provides an inspection apparatus for dynamic time sequence, including:
a creation unit 11 adapted to create a sequential element list and a sequential checklist for each sequential element, the sequential element list comprising: a timing element name, the timing checklist comprising: the time sequence element is used for dynamically checking the items required to be checked in the time sequence;
a circuit acquisition unit 12 adapted to acquire a circuit schematic or a circuit netlist of a circuit to be inspected:
an element list grabbing unit 13 adapted to automatically grab sequential elements from the circuit schematic or circuit netlist based on the sequential element list;
a checklist obtaining unit 14, adapted to automatically obtain a circuit checklist corresponding to the circuit to be checked according to the time sequence checklist and the captured time sequence element, wherein the circuit checklist includes: the names of the captured sequential elements, the hierarchy of the captured sequential elements in the circuit schematic diagram or circuit netlist, and the items of the captured sequential elements to be inspected in dynamic sequential inspection;
the simulation unit 15 is adapted to bring the circuit checklist into a simulator of dynamic timing analysis for verification.
The establishing the time sequence element list comprises the following steps: a list of sequential elements is created based on the library of process elements. The process element library comprises: foundry issues a standard design package file.
The circuit checklist supports the generation of checkgrammars for different emulators. The simulator of the dynamic time sequence analysis comprises: transistor-level simulators in high-speed circuit designs. The simulator of the dynamic time sequence analysis comprises: a spice simulator with timing checks at the transistor level.
The present invention also provides a computer-readable storage medium having stored thereon a computer program for execution by a processor to perform the steps of the method described in the above embodiments.
The invention also provides an electronic device comprising a memory and a processor, the memory having stored thereon a computer program capable of being run on the processor, wherein the processor performs the steps of the method according to the above embodiments when the processor runs the computer program.
Those skilled in the art will appreciate after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
Claims (14)
1. A method for checking dynamic time sequences, comprising:
establishing a time sequence element list and a time sequence checking list corresponding to each time sequence element, wherein the time sequence element list comprises time sequence element names, and the time sequence checking list comprises items required to be checked in dynamic time sequence checking of the time sequence elements;
obtaining a circuit schematic diagram or a circuit netlist of a circuit to be checked;
automatically grabbing sequential elements from the circuit schematic diagram or the circuit netlist based on the sequential element list;
according to the time sequence checklist and the grabbed time sequence elements, automatically acquiring a circuit checklist corresponding to the circuit to be checked, wherein the circuit checklist comprises: the names of the captured sequential elements, the hierarchy of the captured sequential elements in the circuit schematic diagram or circuit netlist, and the items of the captured sequential elements to be inspected in dynamic sequential inspection;
and carrying the circuit checklist into a simulator for dynamic time sequence analysis to finish verification.
2. The method of checking dynamic timing according to claim 1, wherein the creating a timing element list includes: a list of sequential elements is created based on the library of process elements.
3. The method of dynamic timing inspection of claim 2, wherein the process element library comprises: foundry issues a standard design package file.
4. The method of dynamic sequential inspection according to claim 1, wherein the circuit checklist supports generation of inspection grammars for different simulators.
5. The method of checking dynamic time series according to claim 1, wherein the simulator of dynamic time series analysis comprises: transistor-level simulators in high-speed circuit designs.
6. The method of checking dynamic timing according to claim 5, wherein the transistor-level simulator comprises: a spice simulator with timing checks at the transistor level.
7. A dynamic time series inspection apparatus, comprising:
the device comprises a creation unit, a display unit and a display unit, wherein the creation unit is suitable for creating a time sequence element list and a time sequence checking list corresponding to each time sequence element, the time sequence element list comprises time sequence element names, and the time sequence checking list comprises items which need to be checked in dynamic time sequence checking of the time sequence elements;
a circuit acquisition unit adapted to acquire a circuit schematic or a circuit netlist of a circuit to be inspected:
an element list grabbing unit adapted to automatically grab sequential elements from the circuit schematic or circuit netlist based on the sequential element list;
the inspection list acquisition unit is suitable for automatically acquiring a circuit inspection list corresponding to the circuit to be inspected according to the time sequence inspection list and the captured time sequence elements, wherein the circuit inspection list comprises: the names of the captured sequential elements, the hierarchy of the captured sequential elements in the circuit schematic diagram or circuit netlist, and the items of the captured sequential elements to be inspected in dynamic sequential inspection;
and the simulation unit is suitable for bringing the circuit checklist into a simulator for dynamic time sequence analysis to complete verification.
8. The dynamic time series checking apparatus according to claim 7, wherein the creating the time series element list includes: a list of sequential elements is created based on the library of process elements.
9. The dynamic time series inspection apparatus of claim 8, wherein the process element library comprises: foundry issues a standard design package file.
10. The dynamic sequential inspection apparatus of claim 7, wherein the circuit checklist supports generation of inspection grammars for different simulators.
11. The dynamic time series checking apparatus according to claim 7, wherein the simulator of the dynamic time series analysis comprises: transistor-level simulators in high-speed circuit designs.
12. The dynamic time series checking apparatus according to claim 11, wherein the transistor-level emulator includes: a spice simulator with timing checks at the transistor level.
13. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program is executed by a processor to implement the steps of the method of any of claims 1 to 6.
14. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program capable of being run on the processor, characterized in that the processor executes the steps of the method according to any of claims 1 to 6 when the computer program is run on the processor.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102799698A (en) * | 2011-05-26 | 2012-11-28 | 国际商业机器公司 | Method and system for planning clock tree of application-specific integrated circuit |
| CN107844678A (en) * | 2017-12-21 | 2018-03-27 | 北京华大九天软件有限公司 | Spice emulation modes comprising IP/Memory timing paths |
| CN112613263A (en) * | 2020-12-31 | 2021-04-06 | 成都海光微电子技术有限公司 | Simulation verification method and device, electronic equipment and computer-readable storage medium |
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- 2023-12-19 CN CN202311751838.XA patent/CN117422030A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102799698A (en) * | 2011-05-26 | 2012-11-28 | 国际商业机器公司 | Method and system for planning clock tree of application-specific integrated circuit |
| CN107844678A (en) * | 2017-12-21 | 2018-03-27 | 北京华大九天软件有限公司 | Spice emulation modes comprising IP/Memory timing paths |
| CN112613263A (en) * | 2020-12-31 | 2021-04-06 | 成都海光微电子技术有限公司 | Simulation verification method and device, electronic equipment and computer-readable storage medium |
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