CN117420878A - Waveform generation circuit - Google Patents
Waveform generation circuit Download PDFInfo
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- CN117420878A CN117420878A CN202311456345.3A CN202311456345A CN117420878A CN 117420878 A CN117420878 A CN 117420878A CN 202311456345 A CN202311456345 A CN 202311456345A CN 117420878 A CN117420878 A CN 117420878A
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- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000009977 dual effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
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Abstract
The invention discloses a waveform generation circuit, which belongs to the field of integrated circuits and comprises a digital-to-analog converter, a clock driving differential circuit, a power supply circuit, a hardware configuration circuit and a data configuration circuit; the clock driving differential circuit is used for providing proper differential waveforms for the digital-to-analog converter; the power supply circuit provides various voltages for the digital-to-analog converter; the hardware configuration circuit provides a proper working mode for the digital-to-analog converter; the data configuration circuit connects the SPI communication interface of the digital-to-analog converter with the microcontroller to carry out instruction transmission and data configuration, thereby realizing the generation of various waveforms. The invention can completely replace the imported digital potentiometer, the required waveform can be modified in real time through the logic code, the resolution of 16 bits can be completely compatible with the precision of the required level, various waveforms can be constructed, the operation is very convenient, and the function is better than that of the original imported digital potentiometer.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a waveform generation circuit.
Background
Currently, in the large background of trade friction, competition among each other starts to reach more and deeper layers, and home-made substitution is needed to obtain advantages in this competition. Under such a background, the related functional chip in the originally designed radio frequency board card needs to find a suitable domestic and non-pseudo-empty package replacing chip.
The digital potentiometer functional circuit is an import chip and can output the level voltage with the resolution of eight bits. When the digital potentiometer chip is connected with a power supply, the MCU gives out corresponding instructions through SPI communication, and the built-in impedance is adjusted according to the instructions so as to provide proper level potential for the next stage. The domestic digital potentiometer has the main solutions of a voltage dividing circuit, a programmable resistor and the like, the manual resistance adjustment is needed in the solutions, and the device is relatively large and is not suitable for being used on a board card, so that the domestic digital potentiometer has no functional chip which can completely replace the domestic digital potentiometer in the process of searching the domestic digital potentiometer.
Considering that the traditional digital potentiometer has the problems of single function and shortfall in the aspect of level adjustment precision, although the digital potentiometer has the corresponding advantages, such as small volume and simple peripheral circuit, in order to match with domestic replacement of companies, a functional circuit which can be used for corresponding functions and has more optimized precision and stronger operability is found, and the functional circuit takes the target as the guide, so that the digital potentiometer can be replaced, and the shortfall of the digital potentiometer can be made up, therefore, a novel DA chip is needed to be built, the functions of the digital potentiometer can be realized, any level and waveform can be realized, and the functions can be realized and upgraded.
Disclosure of Invention
The invention aims to provide a waveform generation circuit which solves the problem that no domestic chip replaces a digital potentiometer and realizes the upgrade of the prior art.
In order to solve the above technical problems, the present invention provides a waveform generation circuit, including: the digital-to-analog converter, the clock drive differential circuit, the power supply circuit, the hardware configuration circuit and the data configuration circuit; the clock driving differential circuit, the power supply circuit, the hardware configuration circuit and the data configuration circuit are all connected with the digital-to-analog converter;
the clock driving differential circuit is used for providing proper differential waveforms for the digital-to-analog converter;
the power supply circuit provides various voltages for the digital-to-analog converter;
the hardware configuration circuit provides a proper working mode for the digital-to-analog converter;
the data configuration circuit connects the SPI communication interface of the digital-to-analog converter with the microcontroller to carry out instruction transmission and data configuration, and realizes the generation of various waveforms.
In one implementation mode, the hardware configuration circuit is externally connected with a resistance-capacitance configuration full-scale output current, a port mode operation signal and an output port; the data configuration circuit is connected with the data converter through a serial communication port, so that the data configuration circuit can be conveniently communicated with various industry standard microcontrollers and microprocessor interfaces.
In one embodiment, the clock driving differential circuit comprises a 100M differential crystal oscillator and an LVDS clock driving circuit, wherein an output end of the 100M differential crystal oscillator is connected with an input end of the LVDS clock driving circuit, and an output end of the LVDS clock driving circuit is connected with an input end of the digital-to-analog converter; wherein,
the 100M differential crystal oscillator is a differential output crystal oscillator, the output logic is a low-voltage differential signal, and the output differential signal enters the LVDS clock drive circuit; the LVDS clock drive circuit processes the input differential signal into a low-jitter clock signal, and the processed differential signal enters the digital-to-analog converter.
In one embodiment, the power supply circuit provides corresponding digital power and analog power for the digital-to-analog converter; wherein, two power supply voltages of 1.8V and 3.3V are provided;
1.8V mainly supplies power to a digital power supply, one path is a clock signal, and the other path is a power supply for the clock signal of the digital-to-analog converter; one way is to the D/A converter1.8VThe digital signal provides a power supply;
the 3.3V power supply mainly supplies power to the digital signal and the analog signal of the digital-to-analog converter.
In one embodiment, the functions provided by the hardware configuration circuit include hardware reset, full scale current output, and reference voltage source.
In one embodiment, the data configuration circuit uses the microcontroller to give a clock signal and an enable signal to the clock of the serial interface, gives corresponding protocol instructions in an instruction period and a data transmission period, and the data converter recognizes the instruction signal written into the SPI register under the instruction operation and receives a 16-bit digital signal so as to convert the 16-bit digital signal into a corresponding analog signal for output.
In one embodiment, SCLK in the data configuration circuit is a serial clock, pins of the serial clock are used to synchronize data of the input/output device, and an internal state machine is run; and CSB in the data configuration circuit is a chip select signal, the chip select signal is effective at a low level and is used for starting and gating a communication period, and when the chip select signal is at a high level, the SDIO pin enters a high-resistance state.
The waveform generation circuit provided by the invention has the following beneficial effects:
(1) The dual-channel high-dynamic-range digital display has the characteristics of simple peripheral circuit, dual channels and a 16-bit high dynamic range;
(2) The circuit is simple to operate and flexible to configure, and a user can access all configuration registers by performing read/write operation through the serial port;
(3) The digital potentiometer not only overcomes the single function that the original digital potentiometer can only adjust the level, but also can realize the programmable differential output current capability to enable the output waveform precision to be higher.
Drawings
Fig. 1 is a schematic diagram of a waveform generation circuit according to the present invention.
Detailed Description
A waveform generation circuit according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a waveform generation circuit, the structure of which is shown in figure 1, comprising a digital-to-analog converter 10, a clock driving differential circuit 20, a power supply circuit 30, a hardware configuration circuit 40 and a data configuration circuit 50; the clock driving differential circuit 20, the power supply circuit 30, the hardware configuration circuit 40, and the data configuration circuit 50 are all connected to the digital-to-analog converter 10. The digital-to-analog converter 10 receives a digital signal and processes an analog signal; clock-driven differential circuit 20 provides digital-to-analog converter 10 with the appropriate differential waveforms; the power supply circuit 30 distributes power supply voltages required by the functions to the modules; the hardware configuration circuit 40 configures the circuit with appropriate hardware circuits; the data configuration circuit 50 configures the serial communication interface to the digital-to-analog converter 10 and processes the logic program edited in the MCU, so that the digital-to-analog converter 10 receives the task code and transfers it to the analog interface for output by the process.
The waveform generation circuit of the present invention can generate arbitrary level signals and various waveforms, and the digital-to-analog converter 10 can receive code instructions sent by the microcontroller to the serial communication data port, and can obtain the required waveform signals with a resolution of 15uV (full scale 1V). Therefore, the waveform generation circuit not only can completely replace an imported digital potentiometer circuit, but also can obtain various waveform signals with higher precision by compiling codes, and is very suitable for various radio frequency circuits and arbitrary waveform generators. In particular, the microcontroller is an MCU or other device having similar functionality, and may be contained in the hardware configuration circuit 40.
With continued reference to fig. 1, the clock-driven differential circuit 20 provides the digital-to-analog converter 10 with a suitable differential waveform, and the clock-driven differential circuit 20 is composed of a 100M differential crystal oscillator and an LVDS clock-driven circuit. The output end of the 100M differential crystal oscillator is connected with the input end of the LVDS clock drive circuit, and the output end of the LVDS clock drive circuit is connected with the input end of the digital-to-analog converter 10; wherein,
the 100M differential crystal oscillator is a differential output crystal oscillator, the output logic is a low-voltage differential signal, and the output differential signal enters the LVDS clock drive circuit. The LVDS clock driver circuit processes the input differential signal into a low-jitter clock signal, and the processed differential signal is then fed into the digital-to-analog converter 10 asDigital-to-analog converter 10Providing a uniform time reference.
The power supply circuit 30 supplies digital power and analog power to the digital-to-analog converter 10. Wherein two supply voltages are provided: 1.8V and 3.3V.1.8V mainly supplies power to a digital power supply, one path is a clock signal, and the clock signal of the digital-to-analog converter 10 is supplied with power; and one way to the digital to analog converter 10A kind of electronic device1.8The V digital signal provides the power supply. The 3.3V mainly supplies power to the digital signal and the analog signal of the digital-to-analog converter 10.
The hardware configuration circuit 40 is connected to corresponding pins of the digital-to-analog converter 10. The external hardware RESET pin RESET is effective in high level, and is set low in the application, and software is used for resetting; full-range output current adjustable FSADJ is connected with a 10K resistor and then enabled at a low level; the reference input/output pin REFIO is connected with the capacitor 0.1uF to the ground for configuration; the signal IQSEL for signal port mode operation is set to a low level in the dual port mode; the differential output ports IOUTP and IOUTN need to be connected with resistors to convert digital signals into analog level inputs, the full-scale voltage is 1V, and the current is set to be 20mA, so that both IOUTP and IOUTN are connected with 50 ohm resistors.
The data configuration circuit 50 and the data converter 10 perform data transmission and exchange, the data configuration circuit 50 uses the microcontroller to give clock signals and enable signals to the serial interface, gives corresponding protocol instructions in the instruction period and the data transmission period, and the data converter 10 can recognize the instruction signals written into the SPI register and receive 16-bit digital signals under the instruction operation, so as to convert the signals into corresponding analog signals for output. Any waveform output can be produced by writing logic code.
It should be noted that, SCLK in the data configuration circuit 50 is a serial clock, and pins of the serial clock are used to synchronize data of the input/output device and run an internal state machine; the CSB in the data configuration circuit 50 is a chip select signal, which is active low for starting and gating one communication cycle, and when the chip is selected high, the SDIO pin enters a high impedance state. The chip select signal should remain low throughout the SPI communication.
The waveform generation circuit provided by the invention can generate various waveforms through codes. When the power supply system supplies power, the LVDS clock drive circuit works to provide 100M differential input for the digital-to-analog converter, the digital-to-analog converter starts to work, corresponding clocks, enabling codes and logic codes are configured for SPIs in the data configuration circuit, corresponding levels are configured for I/O ports of the data configuration circuit, or various waveforms are configured for the SPIs. Therefore, the high-performance potential generating circuit can completely replace an imported digital potentiometer, the required waveform can be modified in real time through logic codes, the resolution of 16 bits can be completely compatible with the precision of the required level, various waveforms can be constructed, the operation is very convenient, and the function is better than that of the original imported digital potentiometer. The circuit can also be widely applied to various radio frequency detection circuits.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (7)
1. A waveform generation circuit, comprising: the digital-to-analog converter, the clock drive differential circuit, the power supply circuit, the hardware configuration circuit and the data configuration circuit; the clock driving differential circuit, the power supply circuit, the hardware configuration circuit and the data configuration circuit are all connected with the digital-to-analog converter;
the clock driving differential circuit is used for providing proper differential waveforms for the digital-to-analog converter;
the power supply circuit provides various voltages for the digital-to-analog converter;
the hardware configuration circuit provides a proper working mode for the digital-to-analog converter;
the data configuration circuit connects the SPI communication interface of the digital-to-analog converter with the microcontroller to carry out instruction transmission and data configuration, and realizes the generation of various waveforms.
2. The waveform generation circuit of claim 1, wherein the hardware configuration circuit is externally connected with a resistor-capacitor configuration full-scale output current, a port mode operation signal and an output port; the data configuration circuit is connected with the data converter through a serial communication port, so that the data configuration circuit can be conveniently communicated with various industry standard microcontrollers and microprocessor interfaces.
3. The waveform generation circuit of claim 1, wherein the clock driven differential circuit comprises a 100M differential crystal oscillator and an LVDS clock drive circuit, an output of the 100M differential crystal oscillator being coupled to an input of the LVDS clock drive circuit, an output of the LVDS clock drive circuit being coupled to an input of the digital-to-analog converter; wherein,
the 100M differential crystal oscillator is a differential output crystal oscillator, the output logic is a low-voltage differential signal, and the output differential signal enters the LVDS clock drive circuit; the LVDS clock drive circuit processes the input differential signal into a low-jitter clock signal, and the processed differential signal enters the digital-to-analog converter.
4. The waveform generation circuit of claim 1, wherein said power supply circuit provides corresponding digital and analog power to said digital-to-analog converter; wherein, two power supply voltages of 1.8V and 3.3V are provided;
1.8V mainly supplies power to a digital power supply, one path is a clock signal, and the other path is a power supply for the clock signal of the digital-to-analog converter; the other path is to provide power for 1.8V digital signals of the digital-to-analog converter;
the 3.3V power supply mainly supplies power to the digital signal and the analog signal of the digital-to-analog converter.
5. The waveform generation circuit of claim 1, wherein the functions provided by the hardware configuration circuit include hardware reset, full scale current output, reference voltage source.
6. The waveform generation circuit of claim 1, wherein the data configuration circuit is configured to provide a clock, enable and enable signal to the serial interface by the microcontroller, and provide corresponding protocol commands in command cycles and data transfer cycles, and the data converter recognizes the command signal written to the SPI register under command operation and receives the 16-bit digital signal for conversion to a corresponding analog signal output.
7. The waveform generation circuit of claim 6, wherein SCLK in said data configuration circuit is a serial clock having pins for synchronizing data of input/output devices and running an internal state machine; and CSB in the data configuration circuit is a chip select signal, the chip select signal is effective at a low level and is used for starting and gating a communication period, and when the chip select signal is at a high level, the SDIO pin enters a high-resistance state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311456345.3A CN117420878A (en) | 2023-11-03 | 2023-11-03 | Waveform generation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311456345.3A CN117420878A (en) | 2023-11-03 | 2023-11-03 | Waveform generation circuit |
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| CN117420878A true CN117420878A (en) | 2024-01-19 |
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| CN202311456345.3A Pending CN117420878A (en) | 2023-11-03 | 2023-11-03 | Waveform generation circuit |
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| CN (1) | CN117420878A (en) |
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- 2023-11-03 CN CN202311456345.3A patent/CN117420878A/en active Pending
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